Abstract: A Steered Frequency Phase Lock Loop (SFPLL) comprises a phase loop that functions like a normal phase locked loop (PLL) and locks to the input signal, and a frequency loop that uses a reference frequency to influence the phase loop and effectively confines the output frequency of the phase loop and the SFPLL to be in a range of frequencies close to the reference frequency. The reference frequency is chosen to be very close to the input signal frequency that it is desired the SFPLL lock to. The SFPLL comprises a phase detector (10), a frequency detector (22), first and second gain components (12, 24), first, second and third filter components (14, 18, 26), a summer (16) and a voltage controlled oscillator (VCP)(20). By a judicious choice of the gains in the phase and frequency loops the SFPLL can be designed so that the range of frequencies to which the SFPLL will lock can be confined to an arbitrarily small region around the reference frequency (.omega.'.sub.r).

Abstract: A transmitter and a phase locked loop (30) for a transmitter are disclosed. The phase locked loop (30) upconverts the frequency of a baseband signal to a frequency for radio transmission. As well as the usual components, the phase locked loop (30) comprises a modulator (39) for modulating a baseband signal (f.sub.bb) onto a carrier (f.sub.ref /R) and forwarding the resultant modulated signal (f.sub.c) to one of the inputs of the phase detector (33). It also comprises a low pass filter (38) in its forward path between the phase detector (33) and the voltage controlled oscillator (34) for passing signals having baseband signal frequencies. A mixer (35) and main frequency divider (36) are provided in the feedback path to downconvert the transmit signal (f.sub.tx). This low division eliminates large amounts of multiplicative noise within the loop bandwidth, and therefore enables a large loop bandwidth to be used. Consequently, the settling time of the phase locked loop is improved.

Abstract: For a possible simple structure, dispensing with ceramic filters, an FM demodulator for demodulating sound-FM signals comprises a controllable amplifier (1) which receives the sound signals converted to intermediate frequencies, said amplifier having a gain which is adjusted by means of an amplitude control circuit (4) and whose output signal is applied to the amplitude control circuit and to the phase-locked loop which supplies a demodulated sound signal in the locked-in state from its output, said phase-locked loop including a loop filter (7) which comprises a filter (8, 9, 10) of at least the second order with a pole at the frequency f=0, and a limit-detection circuit (13) which feeds back the operating frequency of the phase-locked loop to a predetermined frequency range when said phase-locked loop leaves this frequency range around a predeterminable nominal demodulation frequency, the amplitude control circuit (4) controlling the controllable amplifier (1) in dependence upon its output signal and a signa

Abstract: A digital compensation filtering technique is provided that enables indirect phase locked loop modulation with a digital modulation data stream having a bandwidth that exceeds, perhaps by an order of magnitude, the bandwidth characteristic of the phase locked loop. A modulation data receiver is provided for receiving from a modulation source digital input modulation data having a bandwidth that exceeds the cutoff frequency characteristic of the phase locked loop frequency response. A digital processor is coupled to the modulation data receiver for digitally processing the input modulation data to amplify modulation data at frequencies higher than the phase locked loop cutoff frequency.

Abstract: A circuit comprising a plurality of phase locked loop circuits, a control circuit and a plurality of storage elements. Each of the plurality of phase locked loop circuits may present a recovered data signal and a recovered clock signal in response to one of a plurality of serial data streams, a clock signal and one of a plurality of indication signals. The control circuit may present a counter signal in response to the recovered clock signals. The plurality of storage elements may each be configured to present one of the indication signals in response to the clock signal, a select signal and the counter signal.

Abstract: A high-performance voltage controlled oscillator without use of variable capacitance (varicap) diodes which is easy in fabrication in an semiconductor IC form. The voltage controlled oscillator includes:a differential amplifier having a differential pair of transistors (Q.sub.1, Q.sub.2); an LC resonance circuit having a coil (L.sub.0) and a capacitor (C.sub.0); a phase shift circuit for receiving a differential output of the differential amplifier via a buffer of transistors (Q.sub.3, Q.sub.4) and for providing its output for the differential amplifier in a positive feedback mode; and a current control circuit for variably controlling an operating current (Ie) of the phase shift circuit according to a controlled voltage applied from a circuit other than those in the voltage controlled oscillator.

Abstract: A Radio Frequency (RF) transponder (tag), method, and system, whereby the tag has a low current tag oscillator, the oscillation frequency of the tag oscillator set by RF signal from a base station.

Abstract: A carrier phase synchronizing circuit is disclosed, that comprises an AFC loop and a PLL, the AFC loop including an AFC complex multiplexing device, an LPF, a PLL complex multiplying device, a phase detector, a loop filter, an AFC filter, and a NCO, the PLL including a PLL multiplying device, a phase detector, a PLL filter, and a NCO. A loop range, a frequency control width, and a control time interval of each of the AFC filter and the PLL filter are controlled corresponding to a time change amount of the frequency error that is detected in the PLL.

Abstract: A frequency synthesizer includes a controlled oscillator which is responsive to a frequency control input signal, to generate an output frequency. A programmable frequency divider is responsive to the output frequency and to a divider control input, to divide the output frequency by a first integral ratio or by a second integral ratio in response to the divider control input, to thereby produce a divided signal. A phase comparator is responsive to a reference frequency signal and to the divided signal, to compare the reference frequency signal and the divided signal, and thereby produce a first error signal. A sigma-delta modulator is responsive to a modulation input to produce the divider control input. A loop filter is responsive to the first error signal, to thereby produce the frequency control input signal. Ripple compensation signals and direct modulation signals may also be provided, to provide a three-point modulator for a frequency synthesizer. Analog and digital embodiments may also be provided.

Abstract: An improvement on the phase-locked loop (PLL) circuit, in which an amplifier is disposed at the modulating signal input end of the PLL, and the output end of the amplifier is connected in series to a resistor and an inductor, followed by a resistor connected to a higher DC bias as well as a variable capacitance diode connected to ground. In such a way, the variable capacitance diode is under the higher bias and thus has a smaller capacitance change, while having its Q-value property opposite to the resonance curve formed by the crystal unit of an oscillator which is associated in parallel with the variable capacitance diode, thereby forming in a good compensation for the linearity of the circuit architecture and achieving an ideal frequency deviation and a reduced distortion caused by the modulation.

Abstract: Signal processing apparatus (410) includes a phase-locked oscillator (200, 236, 310, 330, 390), having a closed loop with both forward (204) and feedback (206) paths, that is a part of a larger closed loop (438). The larger loop (438) is phase locked to the phase-locked oscillator (200, 236, 310, 330, 390) by a signal derived from the larger closed loop (438) that modulates the feedback path (206), and by an output frequency of the phase-locked oscillator (200, 236, 310, 330, 390) that is delivered to the larger loop (438). Modulating the feedback path (206) either adds pulses to the feedback path (206) or removes pulses, thereby causing irregularities in the flow of pulses. A low-pass filter (210) in the feedback path (206) obviates these irregularities, thereby also obviating incidental frequency modulation (IFM) in the output of the phase-locked oscillator (200, 236, 310, 330, 390).

Abstract: A frequency synthesizer (100) is utilized for producing an output signal (124) which is phase locked to a reference signal (110) operating at a reference frequency. The frequency synthesizer (100) comprises a main phase lock loop (PLL) (102), and a tracker PLL (128). The main PLL (102) includes a phase detector (112), two frequency dividers (108, 126), a loop filter (116), a notch filter (118), and a controlled oscillator (122). The tracker PLL (128) phase locks to the reference signal (110), and biases the notch filter (118) in order to maintain an accurate lock on the notch frequency which is proportional to the reference frequency. All circuits are integrated in the same monolithic device in order to track parametric tolerances such as transconductances of the operational transconductance devices included in the tracker PLL (128) and the notch filter (118).

Abstract: Device of the phase-locked loop type for demodulating a frequency-modulated signal. Device for frequency demodulation, using a phase-locked loop. According to the invention, for linearizing the variation of the frequency of a local oscillator (11) as a function of its control signal (Vb), a variable capacitance (Cv) is formed by an electronic module (20) which supplies the equivalent of a capacitance whose variation as a function of the control voltage (Vb) has a linearity deviation which is established for compensating the linearity deviation of the frequency of the oscillator as a function of the value of the capacitance (Cv).

Abstract: A biphase stable FPLL includes a lock switch, operated in response to a frequency lock condition, that forces a predetermined voltage on the input of the third multiplier to guarantee that the loop locks up in a phase that produces a desired polarity of demodulated signal. A frequency lock indicator operates the lock switch to force the predetermined voltage on the third multiplier irrespective of the actual lock up phase of the loop. If the lock up phase is wrong, the voltage reversal causes the VCO to slip 180.degree. in phase and the loop locks up in its other bistable state.

Abstract: A PLL circuit includes a sampling pulse generator and a loop circuit using a sample and hold circuit as a phase detector. The sampling pulse generator generates a sampling pulse signal at each level transition of an NRZ input signal. The sample and hold circuit samples a clock signal and hold a voltage signal corresponding to a voltage of the clock signal according to the sampling pulse signal. A voltage-controlled oscillator included in the loop circuit generates the clock signal whose frequency is controlled based on tho voltage signal received from the sample and hold circuit through a loop filter. The voltage signal remains at an appropriate level even when the NRZ input signal remains at the same level for a relatively long time. The sampling pulse generator includes a delay circuit for delaying the NRZ input signal and an exclusive-OR circuit receiving the NRZ input signal and the delayed signal.

Abstract: A FPLL has first second and third multipliers with the first multiplier supplying demodulated signals to a limiter and the second multiplier supplying signals to the loop filter. A VCO and phase shift circuit supply quadrature signals to the first multiplier and to the third multiplier which is relocated to an AC path in the loop to avoid the effects of offsets due to stray DC voltages and currents. The limiter output is applied to the third multiplier. The third multiplier supplies its output to the second multiplier. An integrated circuit embodiment using an exclusive OR gate as the third multiplier is also shown.

Abstract: A signal generator has a variable reference oscillator, a variable oscillator and a phase locked loop for generating an output having jitter and wander. The variable reference oscillator generates a reference having a varying phase offset over a first phase modulation frequency interval and a constant output over a second phase modulation frequency interval. The variable oscillator generates a constant output over the first phase modulation frequency interval and a variable output over the second phase modulation frequency interval. The phase locked loop includes a phase detector, a phase summing node and oscillator with the phase detector coupled to receive the outputs of the variable reference oscillator and the oscillator, and phase summing node coupled to receive the outputs of the variable oscillator and the phase detector.

Abstract: A DC frequency modulation circuit for modulating audio signals wherein the high frequencies of the audio signals are modulated by a first phase locked loop and the low frequencies of the audio signals, along with the DC signals, are filtered by a low pass filter, applied through an A/D converter, and modulated by a direct digital frequency synthesizer. The two modulated signals are then mixed by a second phase locked loop.

Abstract: Device for continuous phase modulation, produced from a frequency synthesizer including a variable oscillator and a phase-locked loop with, in series, a frequency division circuit, a phase comparator and a low-pass filter. In order to reduce modulation in the loop, the modulation is applied not only to the input of the synthesizer but also, in compensation, in the loop. In order to eliminate the modulation residue in the loop, a control signal for the oscillator is derived by a circuit which performs a correlation between the residue of the modulation and the output signal from a filter producing the same filtering effect as the loop, and which receives the modulation signal from the input of the synthesizer.

Abstract: A highly efficient linear amplifier and/or modulator and demodulator comprising first and second feedback loops is provided. Each loop processes a component of the input signal and the component signals are recombined at, for example, a summing junction 18. The feedback signals for each loop are dependent upon the output signal and are in phase quadrature. The input signal is separated into I and Q signals, which are also in phase quadrature, by a component separator 10.

Abstract: An VCO generates a high-frequency signal based on a modulating signal and a phase-locking control signal. A first distributor separates the high-frequency signal into two parts, one of which is outputted as an oscillator output signal. An n-multiplier and a microwave amplifier for n-multiplication adjust the level of the reference signal while the frequency of it is multiplied by `n`. A second distributor separates the output from the microwave amplifier for n-multiplication into two parts, one of which is made to be a comparative signal, the other is made to be a locally oscillated signal. A frequency mixer and a microwave amplifier for frequency mixing produce an intermediate frequency signal using the other output from the first distributor and the locally generated signal. The phase comparator compares the intermediate frequency signal with the comparative signal to output an error signal. An LPF generates the phase-locking control signal by removing unwanted signals from the error signal.

Abstract: A frequency-locked loop (100) employs a controllable oscillator (102) for generating an output signal having a frequency, optional sampler (104), coupled to oscillator (102), for sampling the frequency of the output signal, a divider (106), coupled to optional sampling circuit (104), for dividing the output signal frequency to generate a prescaled signal and a microprocessor (108), coupled between the divider 106 and oscillator (102), for comparing the prescaled signal to a reference signal and generating a control signal for correcting frequency shifts based upon the comparison. The control signal generated by microprocessor (108) is non-continuous. During that time when microprocessor (108) generates no control signals, power is removed from various frequency-locked loop circuitry.

Abstract: A phase locked loop including an in-phase detector (IPD), a quadrature phase detector (QPD), a frequency detector (FD), a squelch, a filter, and a voltage controlled oscillator (VCO). The in-phase detector has an IPD sample input, an IPD input, and an IPD output, where the IPD sample input is coupled to a data input. The quadrature phase detector has a QPD sample input, a QPD input, and a QPD output, where the QPD sample input is coupled to the data input. The frequency detector has a first FD input coupled to the IPD output, a second FD input coupled to the QPD output, and a FD output. The squelch has a squelch input, an enable input, and a squelch output where the squelch input is coupled to the IPD output and the squelch enable is coupled to the FD output. The filter has a filter input coupled to the squelch output and a filter output. The voltage controlled oscillator has a VCO input coupled to the filter output, a VCO in-phase output, and a VCO quadrature output.

Abstract: A demodulator circuit (100) and method for producing a demodulated signal V.sub.OUT from an input signal V.sub.IN. A frequency detection circuit (101) produces a quadrature signal V.sub.QUAD which is compared to the input signal V.sub.IN to produce a detected output signal. The phase and frequency of the quadrature signal V.sub.QUAD are responsive to a control signal I.sub.CONTROL. The demodulator circuit (100) has an output terminal (114) which provides the demodulated signal V.sub.OUT. Nonlinearity in the demodulated output signal V.sub.OUT in relation to a modulating signal is reduced by a linearizing feedback circuit (102). Automatic tuning is provided by a tuning feedback circuit (103). The output signals produced at the respective output terminals (114) and (113) of the linearizing feedback circuit (102) and tuning feedback circuit (103) are summed to produce the control current I.sub.CONTROL.

Abstract: A method of demodulating an FM carrier wave and an FM demodulation circuit are described which use a phase locked loop. An FM input signal including the carrier wave is supplied to a phase detector in the phase locked loop. The output of the phase detector is filtered and used to generate a signal for use in controlling a voltage controlled oscillator having an output also connected to the phase detector. The phase locked loop is tuned to a selected carrier wave frequency and a variable gain setting of a variable gain circuit in the phase locked loop is selected to select a desired loop gain. The signal for use in controlling the voltage controlled oscillator is varied by the variable gain circuit to alter the amount by which the frequency of the output of the voltage controlled oscillator changes in relation to a given output of the phase detector. The variable gain setting is selected to select a required bandwidth for demodulation.

Abstract: An FM demodulator demodulating an FM modulated input signal through a PLL circuit, which includes a phase comparator a loop filter, a DC amplifier, a BB amplifier, and a VCO, and outputting the demodulated signal further includes a feedback circuit connected in parallel to DC amplifier and having a resistance which is a function of an external control voltage. The feedback circuit may be connected in parallel to both DC amplifier and BB amplifier. A PIN diode is typically used as a resistance variable element in the feedback circuit.

Abstract: An FM detecting circuit using phase locked loop (PLL) is disclosed. A reference voltage unit generates a reference voltage. A phase detector detects a phase difference between an FM signal and another frequency signal. A low-pass filter receives the output signal from the phase detector, and outputs a detected signal by passing only low frequency signals. A DC component detector receives the output signal from the low-pass filter, and detects a DC component. A voltage controlled amplifier receives the reference voltage and the voltage output from the DC component detector, and outputs a constant level voltage by controlling a gain based upon the difference between the two received voltages.

Abstract: Receiver section (200) includes a compensation network (202) which compensates for undesired effects caused by synthesized LO (204). Compensation network (202) substantially duplicates the amplitude and phase delay of synthesized LO (204) allowing for a substantially flat demodulated frequency response to be achieved at output (122) which is independent of the bandwidth of synthesized LO (204).

Abstract: A phase detector of a phase-lock-loop circuit measures a phase error between an output signal of an oscillator and a synchronizing signal. When a difference between the phase error that is measured in a pair of horizontal line periods exceeds a first magnitude, that is indicative of phase error inconsistency, the phase of the oscillator output signal is not corrected and the phase-lock-loop circuit operates in an idle mode of operation.

Abstract: In accordance with a loop open/close control signal, an analog switch closes or opens a loop including a voltage controlled oscillator, a variable frequency divider, a phase comparator, and a first loop filter, the analog switch, and a second loop filter. In order to reduce the change of frequency caused when the open loop state is set immediately after the output frequency is changed, the second loop filter uses a capacitor which shows properties of a small change of capacitance in response to an applied voltage and a small hysteresis. In another embodiment, the voltage controlled oscillator includes a second diode, one terminal of which is grounded, connected in reverses parallel to a first diode switch which switches the output oscillation frequency ranges of the voltage controlled oscillator.

Abstract: A transceiver (10) includes a dual port phase and magnitude balanced synthesizer modulator (60). The modulator (60) couples a modulation input to a voltage controlled oscillator (40) and to a reference oscillator (42) that are coupled together in a phase locked loop (44). The modulator 60 includes a magnitude balancing circuit (64) that divides a modulation input representing data or the like into a first modulation input signal applied to the reference oscillator (42) and a second modulation input signal for the voltage controlled oscillator (40). A phase balancing circuit (68) induces a negative phase shift in the second modulation input signal that is coupled to the voltage controlled oscillator (40) in order to compensate for the phase lag of the reference oscillator loop (44).

Abstract: A transmitter has an oscillator (101, 201, 303, 401, 501) that operates at frequency k multiplied by f.sub.c, thus the oscillator (101, 201, 303, 401, 501) outputs a signal at an output frequency, kf.sub.c. Coupled to the oscillator (101, 201, 303, 401, 501) is a frequency modifier (103, 205, 307, 405, 505), for modifying the oscillator output frequency by factor 1/k, thereby producing a signal at frequency f.sub.c at the frequency modifier output. Coupled to the frequency modifier output is a modulator (105, 215, 301, 407-417, 507-517) for producing a modulated output signal substantially centered at frequency f.sub.c.

Abstract: A high-speed bit synchronizer comprising a phase comparator for detecting a phase relationship between a center of an eye pattern of input NRZ data and a rising transition of a clock pulse from a voltage controlled oscillator (VCO) whenever the input NRZ data makes a transition, a frequency comparator for detecting a frequency relationship between a multiple of a period of the clock pulse from the VCO and a multiple of a period of an external reference clock pulse whenever the external reference clock pulse makes a rising or falling transition, phase and frequency comparator gain limiters for limiting gains of the phase and frequency comparators, respectively, a frequency synchronous signal detector for generating frequency synchronous and asynchronous signals in response to an output of the frequency comparator, a phase difference output controller for controlling the transfer of an output of the phase comparator gain limiter in response to an output of the frequency synchronous signal detector, a low pass f

Abstract: A frequency modulation signal demodulator receives an intermediate frequency signal to demodulate a FM signal. The frequency modulation signal demodulator includes a voltage-controlled oscillator having variable capacitance diodes. The voltage-controlled oscillator varies the oscillating frequency of a signal by controlling a voltage across the variable capacitance diodes using a DC voltage. Also included is a phase comparator which produces a phase difference by comparing the phase of the intermediate frequency signal to the phase of the signal from the voltage-controlled oscillator and provides a direct current voltage signal corresponding to the phase difference. Also included is a differential amplifier which has an adjustable reference voltage source. The differential amplifier amplifies the direct current voltage signal to produce a demodulated signal. The demodulated signal is negatively fed back to the voltage-controlled oscillator as the direct current signal.

Abstract: An up/down counter within a phase locked loop is gated to count high frequency clock pulses during the first cycle of the input signal. Upon detection of a transition in the input signal indicating the end of the first cycle, the direction of the count is reversed until the count is reduced to zero, thereby assuring equal widths for the first and second half cycles of each output cycle. The system may be implemented with or without a voltage controlled oscillator. In the latter implementation, the count in the up/down counter at the time of a reversal in the count direction is compared with the count in a preset counter. A difference counter compares the differences in a count in the two counters and adjusts the count in the preset counter to match that in the up/down counter at the time of transition. The widths of the successive cycles, rather than half cycles, may be made by doubling the output frequency relative to the input frequency.

Abstract: A modulator for digital modulation is described to produce a modulated output from a voltage controlled oscillator in a phase locked loop during transmission of a random modulating input. The input voltage is applied to a coupling capacitor and when transmission ceases, the state of charge on the capacitor will not change because of a biasing circuit which comprises two resistors fed by a tri-state buffer which holds the input terminal of the capacitor at the average level between logic zero and logic one when no modulation is applied.

Abstract: An oscillator provided with an oscillation circuit provided with two oscillation transistors comprising a differential pair and a resonance circuit connected in common to the bases of the oscillation transistors. The bases of the oscillation transistors are short-circuited by a coil, a center tap coil is connected in parallel to the resonance circuit, and variable capacitive diodes in the resonance circuit are driven by a coil connected to a mixing circuit. Due to this, it is possible to prevent the occurrence of low frequency noise, possible to realize a completely balanced operation, possible to avoid the oscillation carrier flowing into the power source and ground, and possible to reduce the noise in a television picture.

Abstract: An apparatus (500) for generating first and second output signals having predetermined frequency shifts relative to a frequency provided by a reference signal is included in a system comprising a phase-locked loop (206) coupled to the reference signal for generating the first and second output signals. The apparatus (500) includes pulse deletion circuitry (204) coupled to the reference signal and the phase-locked loop (206) for deleting pulses from the reference signal at a first deletion rate to generate the first output signal and for deleting pulses from the reference signal at a second deletion rate to generate the second output signal.

Abstract: An oscillator capable of setting a desired frequency by using only two resonators without setting up any additional adjustment processes, and a synthesizer tuner circuit with an AM synchronous detect circuit.

Abstract: Circuitry for simultaneously generating a set of carriers having preselected frequencies in the amplitude modulation broadcast band includes a circuit for producing a train of pulses having a crystal-controlled pulse repetition frequency equal to the separation in frequency between successive assignable frequencies in the broadcast band, each pulse in the train having a pulsewidth approximately equal to the reciprocal of the frequency of the lower end of the broadcast band and having a rise time approximately equal to the reciprocal of the frequency of the upper end of the broadcast band, so that the spectrum of the train of pulses includes components having frequencies equal to all of the assignable frequencies in the broadcast band, the pulse train being applied to a set of phase-locked oscillators connected in parallel, each oscillator being tuned to a different one of the selected components of the train of pulses.

Abstract: A frequency synthesizer which comprises a voltage controlled oscillator; a unit for outputting a value corresponding to a differential phase of a reference signal at a predetermined frequency as a first differential phase; a unit for sampling an oscillating signal corresponding to an output of the voltage controlled oscillator K times per period of a repeating frequency f.sub.r (f.sub.

Abstract: An apparatus for generating output signals having predetermined frequency shifts relative to a frequency provided by a reference signal is included in a system (500) comprising a phase-locked loop (206) coupled to the reference signal for generating the first and second output signals. The apparatus comprises pulse addition circuitry (204) coupled to the reference signal and the phase-locked loop (206) for adding pulses to the reference signal at a first cyclical rate to generate the first output signal and for adding pulses to the reference signal at a second cyclical rate to generate the second output signal.

Abstract: In a radio transmitter, a PM input signal is provided directly to a frequency synthesizer. The synthesizer includes a PLL having a reference frequency input signal and a controlled frequency output signal. The PLL includes a frequency divider which is directly connected in a feedback circuit path between the controlled frequency output signal and the PLL's phase-detector. The frequency divider has a frequency control input signal for setting a division ratio N for the divider, and a PM circuit has as input signal the PM input signal and the frequency control input signal. The PM circuit provides an offset signal to the phase detector output, so that the PLL creates a correcting phase signal resulting from the offset signal. The magnitude of the offset signal changes as a function of the change in the value of N.

Abstract: A phase-locked loop frequency modulation circuit that compensates for the inability of a phase-locked loop to pass low-frequency content of an input modulation signal, and that may be utilized with existing communication apparatus, such as a cellular telephone voice radio, for accurate data transmission without having to modify such apparatus, includes a compensation circuit for processing an input modulation signal to provide a compensation signal that is added to a loop filter output signal by processing the input modulation signal to provide the same effect as adding the input modulation signal to an integrated input modulation signal that is filtered by a filter having the same transfer function as the loop filter to provide the compensation signal.

Abstract: An FM demodulation circuit comprises, an oscillation circuit (3) whose oscillation frequency is varied by a control signal, a phase comparator means (2) for comparing phases of signals between an FM signal to be demodulated and the output signal of the oscillation circuit (3) and generating a comparison signal corresponding to the phase difference, an additional voltage determining circuit (7) for determining an additional voltage based upon the comparison signal, and an adder (5) for adding the comparison signal and the additional voltage, and supplying the added result as the control voltage. The additional voltage may be a value which makes the comparison signal level at a center level of the operable range of the phase comparator (2).

Abstract: A signal receiving device is kept tuned by a tuning signal, which supplied to a tuning input of a tunable circuit in the signal receiving device. The tuning signal is supplied from a memory. The signal receiving device has an operating state and a calibrating state. The calibrating state serves to determine the tuning signal and to store it in the memory. In the calibrating state, a broadband signal source supplies a broadband signal to a band-pass filter. The band-pass filter is tuned to and passes a reference signal to the tunable circuit which provides the signal receiving device with selectivity in the operating state. The response of the tunable circuit to the reference signal is monitored and a tuning signal is selected for which it is measured that the tunable circuit is tuned to the reference signal which is passed by the band-pass filter.

Abstract: A modulation circuit utilized in a mobile radio communication transmitter includes an amplifier for amplifying a modulation signal and a modulator having a voltage-controlled oscillator for generating a frequency modulation signal corresponding to the modulation signal. An amplifier controller applies a first predetermined constant direct current voltage V.sub.1 to a power source of the amplifier when the frequency of the modulation signal is less than a predetermined frequency f.sub.3, and for a second predetermined constant direct current voltage V.sub.2 to a power source of the amplifier when the frequency of the modulation signal is higher than the frequency f.sub.3. Thus, when the frequency of the modulation signal is less than the frequency f.sub.3, the amplitude of the modulation signal which is added to the voltage-controlled oscillator decreases by a predetermined value compared with the case where the frequency of the modulation signal is higher than the frequency f.sub.3.

Abstract: A data transmitter (100) operating at a transmit frequency provides a modulated data signal (114) by adjusting a reference frequency signal (108). The method of modulating an N-level data signal (102) inputted to the transmitter (100) provides for inputting, to a signal processor (201), a frequency deviation value. Using the frequency deviation value, the signal processor (201) then determines a maximum rate of enabling the frequency adjustment. Further, a deviation ratio corresponding to one of the N-levels is determined, and an increment value is then calculated (302) using this deviation ratio. Lastly, the frequency adjustment is enabled (312, 320) using the calculated increment value.

Abstract: A phase-locked loop incorporates a quadrature modulator for generating constant envelope phase or frequency modulation. Locating the quadrature modulator within the feedback loop or feeding the output signal of the quadrature modulator into the feedback loop permits accurate constant envelope phase modulation of the loop reference oscillator and completely suppresses undesired AM and PM components of the modulated signal.

Abstract: A D.C. modulated phase locked oscillator (60, 80, 100, 140, 160, 190, 220, 264, or 290) includes a phase locking oscillator (70, 90, 128, 180, 192, 222, 266, or 292) and a D.C. modulator (72, 92, 130, 156, 182, 194, 224, 268, or 294). Both a forward path (14) and a feedback path (16) are D.C. modulated. D.C.