Abstract: A frequency synthesizer used for a frequency modulation (FM) transceiver which uses negative feedback to make the modulation characteristics linear and stable over a wide frequency range. The negative feedback is comprised of a frequency mixer, which mixes the outputs of a local oscillator and a voltage controlled oscillator, and a frequency divider and demodulator, which act on the output of the frequency mixer and supply the demodulated output signal to an adder, where it is added in reverse phase to the modulating signal.

Abstract: In a timing synchronizing circuit wherein a timing signal is regenerated from a baseband signal subjected to a bandwidth limitation, there are provided a voltage controlled oscillator whose oscillation frequency varies in accordance with a control signal, an A/D converter which samples and shapes the baseband signal by utilizing the output of the voltage controlled oscillator, a decision circuit for deciding the polarity of a differential coefficient of the baseband signal at an optimum sampling point on the basis of an output of the A/D converter, and a logic circuit responsive to the output of the decision circuit to apply a logical operation to a decision signal derived from the A/D converter and which decides whether or not the baseband signal shifts from a level corresponding to the optimum sampling point, thereby producing the control signal for the voltage controlled oscillator.

Abstract: A circuit for minimizing non-linearity of an FM-demodulator which is in the form of a phase control circuit whereby its voltage controlled oscillator is controlled by adjusting the voltage applied to a capacitive diode coupled thereto so as to adjust the zero-axis crossing of the demodulator to coincide with the center frequency of the input signal to be demodulated.

Abstract: A modulated signal level detecting circuit comprising a synchronized detector 1 of the modulated input signal, a phase-locked loop 5, 14, 16 connected to the input signal for providing a reproduced carrier wave of the input signal, a switch 21 included in the phase-locked loop, and a signal level detecting circuit 22, 23 for detecting the level of the unmodulated signal and opening the switch and thereby breaking the loop when this level exceeds a fixed limit.

Abstract: In a compensated VCO circuit arrangement for providing constant modulation level over a wide frequency band a VCO is disclosed having a linear VCO gain factor vs. control voltage curve over the wide frequency band of interest. A compensation network is coupled to the VCO to provide an audio output having a linear output level vs. control voltage curve. By appropriately matching the two linear curves the variation in modulation level over the frequency band of interest is substantially reduced.

Abstract: A carrier recovery circuit for use in a demodulator for a 2.sup.n -phase PSK modulated signal which comprises a phase-locked loop including a voltage-controlled oscillator (7) and an automatic frequency control (AFC) loop for avoiding the false lock phenomenon. The AFC loop is comprised of two differentiating circuits (21, 25), two mixer circuits (22, 26), and a difference circuit (27), and forms a symmetrical structure so as to exclude undesired noise, thereby carrying out a stable AFC operation.

Abstract: A phase locked loop is frequency modulated by means of a modulation signal pplied to the loop filter thereof. The circuit is designed with two time constants, one of which determines the square wave modulation response thereof and the other the loop settling time. Each of these time constants is chosen to optimize the loop modulation response and the loop settling time.

Abstract: The invention relates to a device for regenerating a carrier wave from a BPSK or QPSK modulation signal. The device multiplies the received signal by two or four depending on whether it has a BPSK or QPSK modulation. The multiplication delivers a reference signal. The device also has a locked loop comprising a voltage-controlled oscillator. A frequency divider is connected between the oscillator output and a second input of a comparator, the output of which is connected to the control input of the oscillator. The central frequency of the oscillator is equal to three times the nominal frequency f.sub.o of the received modulated signal. The output of the oscillator is connected to one input of a mixer having another input which receives the reference signal and the output of which is connected to the first input of the phase comparator. The frequency divider divides by three to deliver the regenerated carrier wave. Identical band-pass filters have a central frequency equal to f.sub.

Abstract: In an FSK demodulator, the output of the phase detector of a phase locked loop (PLL) is capacitively coupled to one input of an FSK voltage comparator, the capacitive coupling blocking d.c. and d.c. being restored at the comparator input by diodes connected between the two comparator inputs. The other input of the comparator is supplied with a reference voltage corresponding to a nominal center frequency of the FSK signals. A buffer amplifier permits rapid charging of the coupling capacitor, which is set to a determined state when there is no phase lock of the PLL. The arrangement facilitates demodulation of narrow-band FSK signals whose center frequency is subject to change.

Abstract: A frequency control system with a phase-locked loop for automatically adjusting the frequency of an alternating signal and an external signal derived coherently therefrom to the variant zero phase-shift frequency of a phase shifter adapted to receive the external signal, the control system comprising: a phase shifter responsive to the external signal for introducing a frequency sensitive bipolar phase-shift to the external signal to produce a phase shifted external signal thereat, the phase shifter introducing zero phase-shift at a drift-prone frequency, f.sub.o ; an alternating signal source for generating the alternating signal of adjustable frequency covering a range of frequencies including frequency, f.sub.

Abstract: A frequency modulator for radio frequency (RF) signals is described that symmetrically modulates the RF signal with either binary signals or voice signals without distorting the amplitude of the binary signal near bit edges. The inventive frequency modulator includes a reference signal generator, a phase comparator for comparing the reference signal and a feedback signal to provide an error signal, a filter for filtering the error signal, a voltage-controlled oscillator (VCO) responsive to the filtered error signal for generating an output signal, a divider for dividing the VCO output signal by a predetermined number to provide the feedback signal, circuitry coupled to the VCO for modulating the VCO output signal with the binary signal, and circuitry coupled to the divider for varying the predetermined number of the divider between a first predetermined number and a second predetermined number in response to the binary signal.

Abstract: In an FM demodulation circuit which demodulates an FM signal by the use of a phase-lock loop constructed of a phase comparator, a loop filter and a voltage-controlled oscillator, the loop filter is a variable loop filter whose loop band width is varied in correspondence with the modulation band width and the carrier/noise ratio of the input signal by a base band processing circuit.

Abstract: A combined phase-locked loop frequency demodulator and frequency synthesizer for frequency-modulated wave receivers using two phase-locked loops respectively for synthesis and for demodulation. In this device, the frequency-modulated signal is applied to one of the inputs of a first phase comparator whose other input is coupled to the output of a voltage-controlled oscillator, which output is also coupled, through a prescaler and a programmable frequency divider mounted in cascade, to one of the inputs of a second phase and frequency comparator whose other input is coupled to the output of a crystal-controlled reference oscillator. The output of the first comparator is coupled by means of a first low-pass or bandpass filter to a first input of an analog adder whose second input is coupled by means of a second low-pass filter, having a relatively low upper cut-off frequency, to the output of the second comparator.

Abstract: A clock recovery system including a VCO responsive to a voltage signal for generating a clock signal. A phase detector includes a register and a PROM, the register counting the clock signal to derive the output clock signal. The PROM is responsive to input data and the count in the register to detect and store information concerning relative phase relationships. A counter contains a count from which the control voltage for the VCO is derived. The PROM is operable to alter the count in the counter, thereby performing frequency adjustments, and to alter the count in the register to perform phase adjustments. Also, a converter, operable by the phase detector, may also derive a voltage signal for damping purposes.

Abstract: An absolute differentiator receives a self-clocking digital input signal, and its output is applied to a series of delay elements. The outputs of the differentiator and the delay elements are coupled to an OR-gate. The output of the OR-gate is applied to a phase-locked loop to produce a recovered clock signal. The delay elements can be variable with a delay controlled by an output signal from the phase-locked loop, to thereby track a varying center frequency of the digital input signal.

Abstract: A linearity test signal generator alternately provides a burst of a modulation frequency and no modulation to the modulation input of the frequency modulator oscillator (FMO) under test. A programmable divider is connected to the output of said frequency modulated oscillator to produce a binary output signal which is applied to the automatic phase control circuit. This circuit in turn develops a DC control signal which is applied to the control input of said frequency modulated oscillator to maintain the average oscillator frequency constant. This DC control voltage gives an indication of the shift in the average free running frequency of the oscillator while being modulated, caused by oscillator non-linearity. The voltage is first sampled when the oscillator is unmodulated to produce a reference voltage which is stored and then compared to a sample of the DC control voltage when the oscillator is being modulated.

Abstract: An AFC loop for controlling the frequency of a VCO including an A to D converter and divider for providing pulses at some frequency equal to or lower than the output of the VCO, a source of stable reference pulses and a counter constructed to count to a predetermined number and count the reference pulses in synchronism with the divided pulses, a second divider connected to divide the reference pulses by the predetermined number and means for subtracting the output of the second divider from the counter to provide a control voltage for the VCO which is proportional to the drift in frequency of the VCO from a mean frequency.

Abstract: A pseudo clock generator produces pulses synchronous with, and having a period equal to one-half of the clock signal within a phase shift keyed encoded data stream. A phase lock circuit, having a stable period equal to that of the data clock signal tends to lock to the pseudo clock signal. Logic detects the condition of the phase lock signal being in phase lock with said data clock signal and in response thereto, masking circuitry prevents the pseudo clock generator from responding to input data transitions which occur outside of a predetermined masking window.

Abstract: A feedback circuit for controlling the phase of a local oscillator provided with frequency adjusting means and delivering a local carrier wave for demodulating a data signal transmitted by single side band amplitude modulation, the said feedback circuit comprising at least one sign multiplier (21) producing the product of the sign of the local demodulation carrier shifted by a phase difference of .pi./4 multiplied by the sign of the data signal to be demodulated, followed by a sign coincidence auto-correlator (22) which controls the said frequency adjusting means and correlates two versions of the signal delivered by the sign multiplier (21), one of the two versions being delayed relative to the other by an odd multiple of one fourth of the period of the carrier used for the amplitude modulation on transmission.

Abstract: The binary state of each cycle of a biphase modulated input signal is detected by a "D" flip-flop when it is clocked by a locally-generated reference signal. When the binary state of the input signal has a first value at clocking, the reference signal is passed through a first exclusive OR gate unchanged. When the binary state of the input signal has the opposite value, the reference signal is inverted by the same OR gate. The output of the first OR gate and the input signal are applied to a second exclusive OR gate to provide a pulse train having a duty cycle indicative of the phase error between the input signal and the reference signal. The latter pulse train is filtered and used to adjust the phase of the reference oscillator until the phase error is eliminated and the circuit is in balance. The binary state of the flip-flop is indicative of the binary state of the input signal.

Abstract: Three sample and hold circuits (26, 30 and 34) sample a received pulse amplitude modulated signal at twice the data bit frequency or timing of the received signal. The clock to the sample and hold circuits is timed so that three consecutive samples, two mid-bit samples and a transition sample are held in the circuits (26, 30 and 34) once every two sample periods. The mid-bit samples are added together by an adder (32) and divided by two in a divider (38) to provide an average. The transition sample is subtracted from this average in a subtractor (36) to produce an error signal. The error signal is normalized in a multiplier (44) using the reciprocal of the difference in magnitude between the two mid-bit samples to produce a normalized signal. A clock signal is generated by a voltage controlled oscillator (52) in response to the normalized signal at twice the bit frequency or bit timing and in synchronism therewith.

Abstract: A phase-locked loop is disclosed that exhibits flat modulation characteristics over a wide range of carrier frequencies for either frequency or phase modulation at rates that are both within and outside the loop bandwidth. The disclosed arrangement is a programmable divide-by-N phase-locked loop frequency synthesizer wherein the feedback path includes a second phase-locked loop that serves as a tracking filter. Modulation is supplied to the main phase-locked loop via a first modulation path that couples the modulating signal to the frequency control terminal of the phase-locked loop voltage-controlled oscillator and via a second modulation path that couples the modulating signal to the phase-locked loop phase detector.

Abstract: A frequency modulator including a free-running oscillator which is frequency modulated and which is frequency stabilized by means of a reference oscillation by way of a phase control loop having a phase detector and a loop filter. In order to be able to process d.c. components with such a frequency modulator, given a keyed modulation signal, and without abandoning the limitation of the modulation spectrum, the modulation signal is supplied to a control input of the oscillator both by way of a modulation filter and by way of the phase control loop. For this purpose, the phase control loop includes, between the oscillator output and the phase detector, a frequency divider having a division ratio controlled by the modulation signal.

Abstract: A system of frequency-shifting of frequency modulated signals, continuously above or below a pre-established frequency, the shift being possibly also null. The system includes a source of frequency modulated signals, the frequency of which is to be shifted; a reference oscillator; a first phase locked loop to which is applied the signals from the signal source and the output of the reference oscillator, the arrangement being such that the first phase locked loop will be locked to a conversion frequency above or below the frequency of the signal source.

Abstract: The invention relates to a method of regenerating the modulation carrier wave of an original modulated signal (SL) which has symmetrical frequency components about the carrier. A phase discriminator (D1) which receives two image signals (SL, S11) of the original signal controls the frequency of a local oscillator (OL), the frequency spectrum of one of the image signals being inverted with respect to that of the original signal and the difference in frequencies between these two image signals being twice that between the local carrier and the carrier of the original signal. Application to the synchronous demodulation of a television signal.

Abstract: The output frequency of a variable frequency oscillator is compared with that of a reference frequency source by means of a phase detector and the resultant error signal is integrated and applied as a negative feedback signal to the input of the oscillator whereby drift of the oscillator output frequency is minimized. Deviation, modulation index, dynamic stability and linearity are enhanced by means of a pulse generator that is synchronized with a modulating input signal supplied to the oscillator for supplying a keying signal to the phase detector during a portion of each cycle of the modulating input signal.

Abstract: A frequency modulator comprising an oscillator the output frequency of which is dependent upon the amplitude of a modulating signal, modulating signal control means via which the modulating signal is fed to the oscillator to produce a corresponding frequency modulation on the output signal from the oscillator, a discriminator responsive to the frequency modulation for producing a corresponding amplitude signal, and a comparator responsive to the corresponding amplitude signal and to the modulating signal for providing a control signal which is fed back to control the gain provided by the signal control means so as to maintain constant the amplitude of the amplitude signal with respect to the modulating signal, whereby operation of the modulator is linearized.

Abstract: A phase locked loop provides frequency modulation over an extended frequency range by summing a modulation signal with the loop signal at two separate points within the loop. The modulation signal is directly applied to the control input terminal of the voltage controlled oscillator. In addition, the modulation signal is processed to compensate for the transfer functions of loop components, and the processed signal is summed with the loop signal at an additional point between the output terminals of the phase detector and the lowpass filter of the loop. The processing of the modulation signal consists of preshaping of the signal to compensate for the transfer functions of loop circuitry located between the voltage controlled oscillator and the summing junction.

Abstract: A biphase shift keyed modulated carrier is input to an analog delay line having a plurality of sampling taps time spaced along the line. The modulated input carrier is sampled at a rate four times the carrier frequency to produce amplitude samples of the input. The taps of the delay line are divided into two groups comprising alternate tap sets and the amplitude samples of each group are summed for decoding the I and Q channels of a modulated carrier. The summed signal of each of the channels is input to an individual sample and hold circuit which aliases the carrier frequency to baseband. The output of the first sample and hold circuit of each channel is provided to a second sample and hold circuit for the respective channels. The second sample and hold circuit of each channel is clocked at a data rate derived from a bit timing loop.

Abstract: A frequency synthesizer including a phase lock loop comprising a voltage controlled oscillator, a four phase modulator for modulating the oscillator output signal, a phase detector for comparing the phases of a reference signal and the output signal of the modulator and filter means for supplying the phase detector output signal back to the oscillator. The two most significant bits of an arithmetic synthesizer are supplied to the modulator to produce, in the absence of additional modulating signals, discrete increments of 90.degree. phase shift in the oscillator output signal. To eliminate phase jitter, the remaining lower order bit positions of the arithmetic synthesizer are converted to analog voltages which are supplied into the phase lock loop to effect a gradual phase shift between the otherwise discrete 90.degree. phase shifts. Continuous phase, constant amplitude output signal is thereby produced having a frequency translated by the phase shifts introduced by the arithmetic synthesizer.

Abstract: An automatic modulation leveling circuit gain controlled by the tuning voltage level into the voltage controlled oscillator of an FM frequency synthesizer providing a normalized modulation gain. The automatic modulation leveling circuit is used in a basic 10 KHz tuning increment direct synthesizer with a skewed frequency standard deriving four intermediate tuning steps of 2.5 KHz each. The leveling circuit includes an amplifier with gain to both DC and AC set by the ratio of a feedback resistor to the value of an input resistor that is a photo resistor subject to resistance change with light variance of a light emitting diode as driven by a second amplifier in the circuit.

Abstract: Frequency-modulated electrical signal generator comprising two oscillators, the first delivering a modulated output frequency and driving a mixer which receives in addition the output of the second oscillator. The latter is phase-controlled by a loop comprising the mixer, a filter and a first phase comparator which receives an intermediate frequency. The first oscillator is controlled by a loop including the second oscillator followed by an adjustable frequency divider and a second comparator receiving a reference frequency.

Abstract: A phase locked loop including a voltage-controlled oscillator and a divider is used to derive a clock timing signal from a received data stream having a given bit transmission rate. The divider may be programmable so that the circuit can derive a clock from a data stream having any one of a plurality of integrally-related bit rates. A second phase locked loop (having a second programmable divider) is inserted in the feedback path to permit clock recovery from data streams having fractionally-related bit rates.

Abstract: An RF-IF signal receiving circuit of a television receiver controls a tuner which receives an amplitude modulated RF signal and converts it to an IF signal and an IF signal carrier generator for demodulating the amplitude modulated signal from the IF signal by synchronous detection, using a phase synchronous loop. A sweep voltage generator of a voltage-controlled oscillator in the phase synchronous loop comprises an envelope detector which is DC-coupled to an output of an amplitude synchronous detector and a low pass filter in order to enhance the pull-in range of the phase synchronous loop.

Abstract: A circuit device for generating a synchronous signal in synchronism with a steady wave component of an input signal and including a first phase-locked loop using the input signal as a reference signal, a second phase-locked loop using an output signal of a voltage controlled oscillator (VCO) of the first phase-locked loop as a reference signal, and a feedback circuit for feeding back and adding an output signal of a VCO of the second phase-locked loop to the input signal. The synchronous signal is stably obtained at the output of the VCO of the second phase-locked loop, even if the level of the steady wave component is relatively low. The level of the fed back signal may be controlled in response to the level of the steady wave component whereby the oscillation of the circuit device may be prevented.

Abstract: A new and improved apparatus and method for phase detection in binary signal tracking loops wherein two bandpass detectors are alternately interchanged between electrical connection with two local code reference tracking signals in order to cancel any adverse effect of gain imbalance in the bandpass detectors and direct current offset or drift. The incoming signal is multiplied with the two local reference signals in a mixer circuit to form first and second product signals which are each separately provided to two bandpass detectors to form error signals. A dither generator controls a first switching circuit to alternately interconnect the two local reference signals to the mixer circuit during the step of multiplying and also controls a second switching circuit to alternately interconnect the error signals to a summing circuit to form a composite error signal representing a difference in levels of the two error signals from the detectors.

Abstract: In the frequency measuring system disclosed herein, a control signal is generated which is related to the value of function of the input signal for a selectable delay time. The average value of the control signal is employed to control the clock rate of a shift register which is used to obtain a delayed version of the input signal, the input signal being digitized and fed into the shift register. This feedback path forms a servo-loop which adjusts the clocking rate of the shift register in correspondence with the frequency of any coherent component in the input signal, even though the input signal may be a composite comprising many random components.

Abstract: An FM demodulator and detector suitable for integration including a phase locked loop for locking to an FM signal and recovering the modulating signal and squelch circuitry coupled to the phase locked loop for gating out the recovered modulating signal. The phase locked loop includes an emitter coupled multivibrator whose phase shifted output is applied together with the FM signal to the squelch circuitry for quadrature phase detection, followed by filtering to derive an indication signal for controlling the gating of the recovered modulating signal.

Abstract: The delay elements of a signal energy transmission network are divided into separate portions through which the transmitted energy is phase shifted by substantially equal amounts. A phase correction circuit reverses the phase shift through one of the divided delay portions by providing a locked oscillator operating at twice the frequency of the signal at a reference phase angle and subtracting therefrom the input frequency of the signal phase shifted through said one of the divided delay portions in order to maintain a constant frequency vs. phase relationship.

Abstract: A device for decoding a Miller-encoded message in the form of binary data at a clock frequency F. The decoder comprises: a transition detector which provides a very short pulse at each transition in the encoded message; first means controlled by a local clock at frequency F to pass only those short pulses which have the same phase; second means for stretching the short pulses passed by the first means to a duration of (1/2F); a local clock phase lock loop acting on a voltage-controlled oscillator of the local clock and responsive to the output signal of the second means; and a flip-flop to sample the output of the second means under the control of the local clock.

Abstract: A phase space locked loop system used for performing indirect frequency modulation. A phase locked loop is comprised of a phase detector coupled to a low pass filter coupled to a voltage controlled oscillator with a feedback loop to the phase detector. Input signals provided by a crystal controlled oscillator are fed to the phase detector. A phase difference other than 90.degree. between the voltage controlled oscillator output and the input signal will result in the phase detector generating an error voltage which is filtered by the low pass filter to alter the voltage controlled oscillator until its phase is 90.degree. from the input signal. A modulating signal is injected into the phase locked loop which causes the voltage controlled oscillator to momentarily change frequency until the output of the phase detector changes enough to balance the modulating signal.

Abstract: A circuit for receiving an incoming RF signal incurring frequency drift and producing a local signal for tracking the incoming signal includes a phase-locked loop and means incorporated in the loop which compensate or correct for the frequency drift so as to maintain the loop locked on the incoming signal. The loop is defined by a phase detector, a DC amplifier and a voltage controlled oscillator connected in series. The correction means is coupled in parallel with the loop amplifier between the loop detector and amplifier at its one end and between the amplifier and a DC bias voltage supply terminal for the amplifier at its opposite end.

Abstract: A vibration noise filtering system for use in airborne radar master oscillator, RMO, systems is disclosed. Master and slave crystal oscillators are used, the slave oscillator being phase locked to the master oscillator governed by a phase locked loop, PLL, having a predetermined low frequency bandwidth. The master oscillator is structurally coupled directly to a source of vibration of the aircraft, while the slave oscillator is isolated and supported from the vibration source by a mechanical passive isolator having a resonant frequency well within the low frequency bandwidth of the PLL. The output of the slave oscillator which is the source of the RMO signal has a phase spectral density within the phase stability requirements of a typical RMO across the operating modulating frequency ranges of both air-to-ground and air-to-air radar modes.

Abstract: Apparatus and method are provided to discriminate between true locking of a phase-locked loop on the main lobe of an information signal, and false locking on a side lobe thereof. The energy in the locked signal is sensed and compared with the signal energy at fixed frequency increments, preferably twice the bit clock rate frequency, above and below the lock frequency. A greater energy content at the increment frequencies than at the locked frequency indicates a false lock condition and is used to inhibit the loop from entering a locked mode.

Abstract: Frequency-modulated phase-locked loop oscillator with a special modulator bypassing the phase-locked loop to inject modulation voltage directly into the voltage-controlled oscillator of the loop to broaden the bandwidth of modulation.

Abstract: A phase-locked demodulator for demodulating a phase-difference modulated carrier having a repeated phase offset increment introduced therein. The demodulator includes, in common with conventional phase locked demodulators, a mixer having a first input connected to receive the modulated carrier and a reference carrier generator such as a voltage controlled oscillator (VCO) connected in a phase-locked feedback loop forming the second input to the mixer. In order to reduce the number of output levels, the VCO is tuned to a frequency Fr=Fc.+-.Fb[(.alpha.)/360] where Fc is the carrier frequency, Fb is the baud rate and .alpha. is the repeated phase offset. In this way the phase offset increment introduced into the modulated carrier is substantially cancelled out thereby leaving only the phase changes containing data information.

Abstract: A composite signal consisting of a plurality of signals of different frequencies is applied via a cancelling circuit to a phase-locked loop circuit which is adapted to be locked with a certain signal contained in the composite signal to generate a signal synchronous with this certain signal. A cancelling signal generated from a cancelling signal generating circuit is applied, in addition to the composite signal, to the cancelling circuit when the phase-locked loop circuit is in the locked state, thereby cancelling, by this cancelling signal, those signals contained in the composite signal other than the certain signal. Thus, only the certain signal is inputted from the cancelling circuit to the phase-locked loop circuit when the latter is in the locked state.

Abstract: A limiter circuit is installed in a servomechanism that establishes a signal at the output terminal of a filter contained therein, in the absence of an input signal within the lock range of the servomechanism, in a manner that maintains the charge on the filter consistent with the established output signal, thus providing favorable initial conditions for rapid reacquisition and smooth reacquisition transients.

Abstract: A first generator provides a reference pulse train having a predetermined reference frequency. A second generator including a voltage controlled oscillator provides a bit clock having a repetition frequency locked to the repetition frequency of the bits of digital data. A first divider coupled to the first generator divides the reference frequency by a selected one of a first division factor and a second division factor different than the first division factor. A fourth divider coupled to the second generator divides the repetition frequency of the bit clock by a selected one of a third division factor and a fourth division factor different than the first, second and third division factors. A phase comparator coupled to the first and second dividers compare the phase of the output signals of the first and second dividers and produces a control signal proportional to the phase difference between the output signals of the first and second dividers.

Abstract: A device for controlling, by means of a phase comparator which receives an nput signal, the phase or frequency output of a voltage controlled oscillator connected with the phase comparator in a phase locked loop, this loop being also provided with a branch circuit including a high pass filter or appropriate characteristics.