Synchronized, Triggered Or Pulsed Patents (Class 331/55)
  • Patent number: 9673827
    Abstract: The present invention relates to a technique capable of implementing a frequency synthesizer circuit separated into a frequency synthesizer circuit part and an injection locked PLL circuit part and sequentially performing a frequency synthesizer lock operation and an injection lock operation to implement fast frequency and phase locking. The present invention comprises: a frequency synthesizer configured to perform a frequency and phase lock operation according to fractional number information and a first reference cock signal supplied from outside and thereby output a reset signal and a second reference clock signal; and an injection locked PLL configured to start a frequency lock operation after being reset by the reset signal inputted when the frequency synthesizer is frequency-locked, receive the second reference clock signal as a reference clock, multiply the second reference clock signal by an integer multiple of target frequency, and output an output clock signal.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: June 6, 2017
    Assignee: POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Jae Yoon Sim, Seung Hwan Hong
  • Patent number: 9606172
    Abstract: An aging detection circuit is provided. The aging detection circuit is configured on a chip and includes a testing circuit and an aging signal generation circuit. The testing circuit is electrically coupled to the aging signal generation circuit. The testing circuit generates an output signal. The aging signal generation circuit includes a signal generation circuit and a selection circuit. The signal generation circuit generates multiple input signals having different frequencies. The selection circuit selectively outputs one of the input signals as an aging signal to an input terminal of the testing circuit or feeds back the output signal generated by the testing circuit to the input terminal of the testing circuit.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: March 28, 2017
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shi-Hao Chen, Yi-Ming Wang, Ting-Hao Wang, Hung-Chun Li
  • Patent number: 9191020
    Abstract: Communications data interface sampling systems configured effectively with fully-symmetric dual-loop traveling wave oscillators providing high frequency evenly spaced multiple phases to represent analog-in-nature continuous signals as digital stream of samples with best approximation to the original signal.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: November 17, 2015
    Assignee: WAVEWORKS, INC.
    Inventors: Ahmet Tekin, Ahmed Emira, Suat Utku Ay, Enver Cavus, Ahmed Mohieldin
  • Patent number: 9143136
    Abstract: A Pumped Distributed Wave Oscillator (PDWO) that provides a high purity accurate signal source with multiple oscillation phases. High-accuracy, high-frequency oscillation phases open paths to high performance phased-array transceiver design. Additional noise-canceling, noise-shaping circuit techniques result in enhanced sensitivity in radio design.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: September 22, 2015
    Assignee: WAVEWORKS, INC.
    Inventors: Ahmet Tekin, Ahmed Emira
  • Patent number: 9121912
    Abstract: A loading state determiner for determining a loading state of an electric power source including a source impedance includes a voltage drop determination circuit which is implemented to provide, based on a detection of an instantaneous current provided under load by the power source to a load, an electric quantity describing a voltage drop at a source impedance of the power source. Further, the loading state determiner includes an evaluation circuit which is implemented to obtain, based on electric quantity describing the voltage drop at the source impedance of the power source and an electric quantity describing a terminal voltage of the power source, a load state signal carrying information on an instantaneous relation between the terminal voltage of the power source and a no-load voltage of the power source.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: September 1, 2015
    Assignee: Hahn-Schickard-Gesellschaft fuer angewandte Forschung e.V.
    Inventors: Dominic Maurath, Bernd Folkmer
  • Patent number: 9035706
    Abstract: A ring-oscillator-based on-chip sensor (OCS) includes a substrate having a semiconductor surface upon which the OCS is formed. The OCS includes an odd number of digital logic stages formed in and on the semiconductor surface including a first stage and a last stage each including at least one NOR gate including a first gate stack and/or a NAND gate including a second gate stack. A feedback connection is from an output of the last stage to an input of the first stage. At least one discharge path including at least a first p-channel metal-oxide semiconductor (PMOS) device is coupled between the first gate stack and a ground pad, and/or at least one charge path including at least a first n-channel metal-oxide semiconductor (NMOS) device is coupled between the second gate stack a power supply pad.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: May 19, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Min Chen, Vijay Kumar Reddy
  • Publication number: 20150130545
    Abstract: A circuit includes a coupling structure and a first inductive device. The coupling structure includes two or more conductive loops and a set of conductive paths electrically connecting the two or more conductive loops. The first inductive device is magnetically coupled with a first conductive loop of the two or more conductive loops.
    Type: Application
    Filed: June 30, 2014
    Publication date: May 14, 2015
    Inventors: Huan-Neng CHEN, Chewn-Pu JOU
  • Publication number: 20150130543
    Abstract: A circuit includes a first oscillator and a second oscillator. The first oscillator includes an inductive device, a capacitive device, and an active feedback device configured to output a first output signal having a predetermined frequency according to electrical characteristics of the inductive device of the first oscillator and electrical characteristics of the capacitive device of the first oscillator. The second oscillator includes an inductive device, a capacitive device, and an active feedback device configured to output a second output signal having the predetermined frequency according to electrical characteristics of the inductive device of the second oscillator and electrical characteristics of the capacitive device of the second oscillator. The inductive device of the first oscillator and the inductive device of the second oscillator are magnetically coupled.
    Type: Application
    Filed: November 8, 2013
    Publication date: May 14, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chewn-Pu JOU, Huan-Neng CHEN
  • Patent number: 9000849
    Abstract: A phase-modification circuit is described. This phase-modification circuit reduces jitter by injecting a divided reference clock in a phase-locked loop from an auxiliary oscillator and by effectively gradually and completely transferring its phase to a master oscillator. The phase-correction strength in the phase-modification circuit is increased by successively coupling an edge in the divided reference clock over many cycles of a clock in the master oscillator. By increasing the correction strength, the phase error is effectively nulled out, thereby reducing the total absolute peak jitter. Moreover, because the correction is gradual and successive, the phase-modification circuit also significantly reduces the cycle-to-cycle jitter and half-cycle or edge jitter.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: April 7, 2015
    Assignee: Oracle International Corporation
    Inventors: Suwen Yang, Frankie Y. Liu
  • Patent number: 8981854
    Abstract: A clock distributor includes a first oscillator and a second oscillator, to each of which a signal controlling an oscillation frequency is input and to one of which a clock is input; a wiring portion that connects the first oscillator and the second oscillator; a first conversion element that converts an output from the first oscillator into electric current, and outputs a result to a first connection portion connecting to the wiring portion; a second conversion element that converts voltage of the first connection portion into electric current, and outputs a result to the first oscillator; a third conversion element that converts an output from the second oscillator into electric current, and outputs a result to a second connection portion connecting to the wiring portion; and a fourth conversion element that converts voltage of the second connection portion into electric current, and outputs a result to the second oscillator.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: March 17, 2015
    Assignee: Fujitsu Limited
    Inventors: Yasumoto Tomita, Hirotaka Tamura
  • Patent number: 8975972
    Abstract: An oscillator system includes a first oscillator, a second oscillator, and a changeover component. The first oscillator is configured to generate a first signal at a selected frequency. The second oscillator is configured to generate a second signal at about the selected frequency. The changeover component is configured to generate a changeover output signal according to the first signal and the second signal.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Michael Aichner, Mattias Welponer Bachmayer, Martin Flatscher
  • Patent number: 8975973
    Abstract: A voltage controlled oscillation circuit oscillates at an oscillation frequency corresponding to a control voltage. Injection locked oscillation circuits oscillate at an oscillation frequency corresponding to an output signal from the voltage controlled oscillation circuit. A mixer circuit performs a frequency conversion based on output signals from the injection locked oscillation circuits. A synchronization determiner determines the synchronous status between the injection locked oscillation circuits in accordance with an output signal from the mixer circuit. The injection locked oscillation circuits synchronize with each other at a frequency that is an integral multiple of the oscillation frequency of the voltage controlled oscillation circuit.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: March 10, 2015
    Assignee: Panasonic Corporation
    Inventor: Junji Sato
  • Patent number: 8975936
    Abstract: An integrated circuit includes a plurality of resonant clock domains of a resonant clock network. Each resonant clock domain has at least one clock driver that supplies a portion of clock signal to an associated resonant clock domain. The resonant clock network operates in a resonant mode with inductors connected to pairs of resonant clock domains at boundaries between the resonant clock domains. Each inductor forms an LC circuit with clock load capacitance in the pair of resonant clock domains to which the inductor is connected.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: March 10, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Visvesh S. Sathe, Samuel D. Naffziger
  • Patent number: 8947171
    Abstract: Coupled timing oscillators are described. The coupling may be electrical, mechanical, or electromechanical in some instances. In some cases, the timing oscillators include mechanical resonators. Any number of timing oscillators may be coupled. The coupled timing oscillators may be operated cooperatively to produce an oscillating signal with improved signal characteristics, such as phase noise and jitter.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: February 3, 2015
    Assignee: Sand 9, Inc.
    Inventor: Pritiraj Mohanty
  • Patent number: 8928416
    Abstract: A transceiver includes a phase lock loop (PLL) and a clock data recovery circuit (CDR). The phase lock loop generates a first level control signal. The clock data recovery circuit, coupled to the phase lock loop, locks an incoming data signal to generate a data recovery clock according to a second level control signal. Wherein the clock data recovery circuit receives the first level control signal to further control a frequency range of the data recovery clock.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: January 6, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventor: Haibing Zhao
  • Patent number: 8902007
    Abstract: A clock distributor includes unit circuit parts each including an oscillator, a first element configured to convert output voltage of the oscillator into a current, a second element having a voltage current conversion characteristic of an opposite phase to that of the first element, the second element being feedback connected to the first element and the oscillator, a third element configured to convert output voltage of the oscillator into a current, a fourth element having a voltage current conversion characteristic of an opposite phase to that of the third element, the fourth element being feedback connected to the third element and the oscillator; a wiring part to connect a connection part of the first and second elements of a unit circuit part to a connection part of the third and fourth elements of another unit circuit part; and a synchronization circuit connected to the oscillator of a unit circuit part.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: December 2, 2014
    Assignee: Fujitsu Limited
    Inventors: Yasumoto Tomita, Hirotaka Tamura
  • Patent number: 8860513
    Abstract: An apparatus comprises a ring oscillator comprising a plurality of delay cells connected in cascade, a main injection apparatus comprising a plurality of main buffers, wherein the main buffers receive a reference clock from their inputs and the outputs of the main buffers are coupled to respective inputs of the delay cells and a replica injection apparatus comprising a plurality of replica buffers, wherein the replica buffers receive the reference clock from their inputs and the replica buffers are configured such that the replica buffers are tri-stated and each output is connected to ground when the ring oscillator operates in an injection-locked mode and each output is connected to ground through a capacitor when the ring oscillator operates in a calibration mode.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: October 14, 2014
    Assignee: Futurewei Technologies, Inc.
    Inventor: Euhan Chong
  • Patent number: 8773182
    Abstract: A stochastic beating time-to-digital converter (TDC) can include triggered ring oscillator (TRO) and a stochastic TDC (sTDC). The TRO, when triggered by a reference signal edge, can generate a periodic TRO signal with a TRO period that is a selected ratio of a voltage-controlled oscillator (VCO) period. The TRO period can be greater than or less than the VCO period by the specified ratio. The sTDC with an event triggered memory can include an sTDC component with a plurality of groups of latches. Each group of latches can be configured to sample and store a VCO state at an edge of a TRO signal. The sTDC component can trigger a capture of a select number of VCO states of the group of latches when one latch in the group of latches transitions to a different digital state referred to as a transition edge.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: July 8, 2014
    Assignee: Intel Corporation
    Inventors: Ofir Degani, Ashoke Ravi, Hasnain Lakdawala, Rotem Banin
  • Patent number: 8704603
    Abstract: A tunable Injection-Locked Oscillator (ILO) having a wide locking range is used in a Local Oscillator (LO) of a wideband wireless transceiver to generate differential signals. The ILO includes a resonator with an adjustable natural oscillating frequency. In one example, the ILO is part of a quadrature divider that can lock onto a Phase-Locked Loop (PLL) output signal in a wide frequency band while achieving lower power consumption and lower phase noise than a differential latch type divider. The ILO is tuned by disabling a Voltage-Controlled Oscillator (VCO) from driving the ILO, adjusting the natural oscillating frequency, making a measurement indicative of the natural oscillating frequency, and determining whether the measurement is within a predetermined range. If the measurement is below the predetermined range, capacitances of resonators within the ILO are decreased, whereas if the measurement is above the predetermined range, capacitances of the resonators are increased.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: April 22, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Mazhareddin Taghivand, Jeongsik Yang
  • Patent number: 8674774
    Abstract: There is provided an aging diagnostic device including: a reference ring oscillator (101) that constitutes a ring oscillator using an odd-numbered plurality of logic gates constituted using a CMOS circuit; a test ring oscillator (102) that constitutes a ring oscillator using an odd-numbered plurality of logic gates having the same configuration as that of the logic gate; a load unit (104) that inputs a load signal to the test ring oscillator (102); a control unit (105) that simultaneously inputs a control signal instructing a start of oscillation of the reference ring oscillator (101) and the test ring oscillator (102) to the reference ring oscillator (101) and the test ring oscillator (102); and a comparison unit (103) that compares differences in the amount of movement of pulses within the reference ring oscillator (101) and the test ring oscillator (102), respectively, in the same time.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: March 18, 2014
    Assignee: NEC Corporation
    Inventors: Eisuke Saneyoshi, Koichi Nose, Masayuki Mizuno
  • Patent number: 8638175
    Abstract: A circuit including a first oscillator configured to oscillate at a first frequency; a second oscillator configured to oscillate at a second frequency, the second frequency being different from and one of a harmonic or sub-harmonic of the first frequency; and a coupling between the first oscillator and the second oscillator configured to injection lock at least one of the first oscillator and second oscillator to the other of the first oscillator and second oscillator.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: January 28, 2014
    Assignee: STMicroelectronics International N.V.
    Inventor: Prashant Dubey
  • Patent number: 8610511
    Abstract: The high-frequency digitally controlled oscillator includes fully digital cells capable of being ported to any CMOS fabrication process. The oscillator has a basic modular architecture comprising a digitally controlled digital ring oscillator (DRO) having a plurality of delay stages, a counter divider and a selection multiplexer. The DRO generates the basic (intrinsic) high frequency range and the counter provides the remaining ranges through division by multiples of two. The multiplexer provides a selection mechanism for the required range of frequencies. Load capacitances to the delay stages are added/removed to control delay via utilization of a unique capacitive cell driven synchronously by two ring oscillators such that the capacitance could be added or removed utilizing the Miller effect. Moreover, multiple capacitive load cells can be added to the same stage.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: December 17, 2013
    Assignees: King Fahd University of Petroleum and Minerals, King Abdulaziz City for Science and Technology
    Inventor: Muhammad E. S. Elrabaa
  • Patent number: 8576019
    Abstract: An electronic high frequency induction heater driver, for a variable spray fuel injection system, uses a scalable array of zero-voltage switching oscillators that utilize full and half-bridge topology with inductors between semiconductor switches wherein the semiconductor switches are synchronous within each bridge for function, and each bridge is synchronized for function along the entire array. The induction heater driver, upon receipt of a turn-on signal, multiplies a supply voltage through a self-oscillating series resonance, wherein one component of each tank resonator circuit comprises an induction heater coil magnetically coupled to an appropriate loss component so that fuel inside a fuel component is heated to a desired temperature.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: November 5, 2013
    Assignee: Continental Automotive Systems, Inc
    Inventors: Perry Czimmek, Mike Hornby
  • Patent number: 8576018
    Abstract: An electronic high frequency induction heater driver, for a variable spray fuel injection system, uses a scalable array of zero-voltage switching oscillators that utilize full and half-bridge topology wherein the semiconductor switches are synchronous within each bridge for function, and each bridge is synchronized for function along the entire array. The induction heater driver, upon receipt of a turn-on signal, multiplies a supply voltage through a self-oscillating series resonance, wherein one component of each tank resonator circuit comprises an induction heater coil magnetically coupled to an appropriate loss component so that fuel inside a fuel component is heated to a desired temperature.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: November 5, 2013
    Assignee: Continental Automotive Systems, Inc.
    Inventors: Perry Czimmek, Mike Hornby
  • Patent number: 8570108
    Abstract: An injection-locked oscillator circuit includes a master oscillator, a slave oscillator, and an injection lock control circuit. The slave oscillator is decoupled from the master oscillator (for example, due to an unlock condition). When the slave is free running, its oscillating frequency is adjusted (for example, as a function of a supply voltage). After an amount of time, the slave is to be relocked to the master (for example, due the unlock condition no longer being present). The slave oscillating frequency is made to be slightly lower than the master oscillating frequency. The slave is then only recoupled to the master upon detection of an opposite-phase condition between the master oscillator output signal and the slave oscillator output signal. By only recoupling the slave to the master during opposite-phase conditions, frequency overshoots in the slave oscillating frequency are avoided that may otherwise occur were the recoupling done during in-phase conditions.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: October 29, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Ashwin Ragunathan, Marzio Pedrali-Noy, Sameer Wadhwa
  • Patent number: 8558623
    Abstract: An oscillator including two groups of elementary junctions having giant magnetoresistance effect traversed by electric currents, the junctions of each of the two groups being in series and energized by respective main currents and the voltages across the terminals of the groups being added together to provide a voltage on an output of the oscillating circuit. The voltage across the terminals of one or more junctions of a first group is applied to a first input of a phase comparator and the voltage across the terminals of one or more junctions of the other group is applied to another input of the phase comparator, the phase comparator providing on two outputs secondary currents of the same amplitude and of opposite signs, which are dependent on the mean phase difference between the voltages applied to the inputs, the secondary currents each being added to a respective main current.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: October 15, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Mykhailo Zarudniev, Eric Colinet, Patrick Villard
  • Patent number: 8558624
    Abstract: A semiconductor integrated circuit capable of reliably detecting oscillation stop of a vibrator-type oscillation circuit and reliably restarting the oscillation circuit when oscillation stop is detected is provided. The semiconductor integrated circuit includes one or more main oscillation circuits configured to generate a main clock signal by a vibrator, a ring oscillator configured to always operate independently of the main oscillation circuit, a main clock detection circuit configured to monitor the main clock signal on the basis of an output clock signal of the ring oscillator and to determine an operation state of the main oscillation circuit, and an switch circuit configured to switch a combination of elements making up the main oscillation circuit in response to a detection result of the main clock detection circuit.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: October 15, 2013
    Assignee: Panasonic Corporation
    Inventor: Kazuhisa Raita
  • Patent number: 8552804
    Abstract: An apparatus includes an adjustable oscillator circuit configured to generate an output signal having a frequency that varies responsive to a frequency control signal and a frequency reference generator circuit configured to produce a frequency reference signal. The apparatus further includes a calibration circuit configured to determine a relationship of the output signal to the frequency reference signal and to enable and disable the frequency reference generator circuit based on the determined relationship.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: October 8, 2013
    Assignee: Integrated Device Technology Inc.
    Inventors: Chenxiao Ren, Tao Jing
  • Patent number: 8497740
    Abstract: A rubidium oscillator or a cesium oscillator is used as a high stability oscillator, and an OCXO being a metastable oscillator which is inferior in a long-term frequency stability compared with the above oscillators but has a high short-term frequency stability is used as a backup. There is prepared a table in which an elapsed time since an occurrence of an abnormality in the high stability oscillator and weighting (use ratio) of use of the both oscillators is corresponded, and by using this table, after the high stability oscillator recovers, an oscillation frequency of the metastable oscillator is used by 100% initially, but thereafter the weighting (use ratio) of use of the metastable oscillator is made smaller and the use ratio of the high stability oscillator is made larger in stages.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: July 30, 2013
    Assignee: Nihon Dempa Kogyo Co., Ltd.
    Inventor: Naoki Onishi
  • Patent number: 8461934
    Abstract: An IC includes first and second pads. The first pad is configured to receive an external clock. Alternatively, the first and second pads are configured to be coupled to a crystal oscillator and receive a reference clock. Alternatively, the second pad is configured to be grounded. The IC includes an internal oscillator for generating an internal clock, and an oscillator detector coupled to the second pad. The oscillator detector includes a transistor having a gate coupled to the second pad configured to pull a source-drain region to a first state if the second pad receives the reference clock or allow the source-drain region to be pulled to a second state if the second pad is grounded. The IC includes a buffer for transferring the first state to the internal oscillator for keeping the internal oscillator enabled and transferring the second state to the internal oscillator for disabling the internal oscillator.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: June 11, 2013
    Assignee: Marvell International Ltd.
    Inventors: Ovidiu Carnu, Xiaoyue Wang, Shafiq M. Jamal
  • Patent number: 8462579
    Abstract: Control signal oscillation filtering circuits, delay locked loops, clock synchronization methods and devices and systems incorporating the control signal oscillation filtering circuits are described. An oscillation filtering circuit includes a first oscillation filter configured to filter oscillations and a majority filter configured to average filter an output of a phase detector and generate in response thereto control signals to an adjustable delay line.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: June 11, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Yantao Ma
  • Patent number: 8446224
    Abstract: A circuit interconnection structure for synchronizing a network of oscillators placed on a semiconductor substrate. One such structure comprises a first synchronizing circuit electrically coupled to a second synchronizing circuit through tunable delay circuits. Also disclosed are methods to tune oscillators placed in different regions of a circuit having multiple clock domains by estimating the relative slack of a first group of signals within the circuit with regard to the period of a first clock domain, and estimating the relative slack of the second group of signals within the circuit with regard to the period of second clock domain, wherein the estimating is performed at process and operational corners that cover the variability of the circuit at different speed conditions, then calculating tuning values for the oscillator delays for each region such that the oscillator delay slack matches the worst relative slack of the signals of the same region.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: May 21, 2013
    Assignee: eSilicon Corporation
    Inventors: Jordi Cortadella, Luciano Lavagno, Emre Tuncer
  • Patent number: 8410858
    Abstract: Electronic circuitry comprising operational circuits of active switching type requiring timing signals, and conductive means for distributing said timing signals to the operational circuits, wherein the timing signal distribution means includes a signal path that has different phases of a drive signal are supplied via active means at different positions about the signal path where that path exhibits endless electro-magnetic continuity without signal phase inversion or has interconnections with another signal path having different substantially unidirectional signal flow where there is no endless electromagnetic continuity between those signal paths and generally has non-linear associated circuit means where the signal path is of a transmission line nature.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: April 2, 2013
    Assignee: Analog Devices, Inc.
    Inventor: John Wood
  • Patent number: 8395454
    Abstract: A circuit for producing a synchronized output of multiple ring oscillators is disclosed. In one embodiment, the circuit includes a first ring oscillator configured to generate a first periodic signal and a second ring oscillator configured to generate a second periodic signal. The circuit may further include a selection unit coupled to receive the first periodic signal and the second periodic signal. The selection unit is configured to convey a first clock edge into each of the first and second ring oscillators responsive to a most recently received rising edge from one of the first and second periodic signals. The selection unit is further configured to convey a second clock edge into each of the first and second ring oscillators responsive to a most recently received falling edge from one of the first and second periodic signals, wherein the first and second clock edges are opposite in direction.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: March 12, 2013
    Assignee: Oracle International Corporation
    Inventor: Timothy Horel
  • Patent number: 8339209
    Abstract: An inductor architecture for resonant clock distribution networks is described. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture exhibits no inductor overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: December 25, 2012
    Assignee: Cyclos Semiconductor, Inc.
    Inventors: Marios C. Papaefthymiou, Alexander Ishii
  • Publication number: 20120313716
    Abstract: An oscillator synchronization system employs two oscillators, each of which includes an integrator which provides a ramping signal at its output, a comparator which receives the ramping signal and a reference signal at respective inputs and toggles an output when the ramping voltage crosses the reference signal, and a one-shot circuit that generates the integrator's reset signal when triggered. The system is preferably arranged such that the oscillators can be operated independently, in which case each oscillator's one-shot is triggered by its own comparator output, or synchronously, in which case each oscillator's one-shot is triggered by the other oscillator's comparator output—with the ramp signal of each oscillator operating to reset the integrator of the other oscillator. The oscillators are typically out-of-phase when synchronized, with the phase difference varying with the magnitude of the reference signals applied to the comparators.
    Type: Application
    Filed: June 10, 2011
    Publication date: December 13, 2012
    Inventor: JONATHAN MARK AUDY
  • Patent number: 8319567
    Abstract: An oscillator synchronization system employs two oscillators, each of which includes an integrator which provides a ramping signal at its output, a comparator which receives the ramping signal and a reference signal at respective inputs and toggles an output when the ramping voltage crosses the reference signal, and a one-shot circuit that generates the integrator's reset signal when triggered. The system is preferably arranged such that the oscillators can be operated independently, in which case each oscillator's one-shot is triggered by its own comparator output, or synchronously, in which case each oscillator's one-shot is triggered by the other oscillator's comparator output—with the ramp signal of each oscillator operating to reset the integrator of the other oscillator. The oscillators are typically out-of-phase when synchronized, with the phase difference varying with the magnitude of the reference signals applied to the comparators.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: November 27, 2012
    Assignee: Analog Devices, Inc.
    Inventor: Jonathan Mark Audy
  • Publication number: 20120286883
    Abstract: A circuit for producing a synchronized output of multiple ring oscillators is disclosed. In one embodiment, the circuit includes a first ring oscillator configured to generate a first periodic signal and a second ring oscillator configured to generate a second periodic signal. The circuit may further include a selection unit coupled to receive the first periodic signal and the second periodic signal. The selection unit is configured to convey a first clock edge into each of the first and second ring oscillators responsive to a most recently received rising edge from one of the first and second periodic signals. The selection unit is further configured to convey a second clock edge into each of the first and second ring oscillators responsive to a most recently received falling edge from one of the first and second periodic signals, wherein the first and second clock edges are opposite in direction.
    Type: Application
    Filed: May 13, 2011
    Publication date: November 15, 2012
    Inventor: Timothy Horel
  • Patent number: 8274338
    Abstract: A method is provided for generating local oscillator signals for a mixer. The method includes providing a reference frequency signal and generating a differential in-phase signal and a differential quadrature signal from the reference frequency signal. The method further includes re-clocking each of the differential in-phase and differential quadrature signals using the reference frequency signal. The re-clocked differential in-phase and differential quadrature signals are then provided as the local oscillator signals for the mixer.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: September 25, 2012
    Assignee: NXP B.V.
    Inventors: Frank Harald Erich Ho Chung Leong, Olivier Aymard
  • Patent number: 8258882
    Abstract: A clock signal distributing device includes a plurality of LC resonant oscillators, each resonating at a frequency conforming to values of a first inductor and a first capacitor to oscillate a signal, an injection locked LC resonant oscillator that resonates at a frequency conforming to values of a second inductor and a second capacitor to oscillate a signal which is synchronous with an input clock signal, and transmission lines that connect oscillation nodes of the plurality of LC resonant oscillators and the injection locked LC resonant oscillator with one another.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: September 4, 2012
    Assignee: Fujitsu Limited
    Inventors: Takayuki Shibasaki, Hirotaka Tamura
  • Patent number: 8258885
    Abstract: In one embodiment, a method includes generating, by a LCVCO, a first signal having a first phase based on a resonant frequency of a first LC tank; generating, by a second LCVCO, a second periodic signal having a second phase based on a resonant frequency of a second LC tank; determining a phase offset between the first LC tank and the second LC tank based on the first and second signals; generating a first output signal and a second output signal based on the determined phase offset; and adjusting the phase offset such that the phase offset is substantially equal to a predetermined phase offset. In one embodiment, the adjusting comprises modulating a first impedance of the first LC tank based on the first output signal, and/or modulating a second impedance of the second LC tank based on the second output signal.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: September 4, 2012
    Assignee: Fujitsu Limited
    Inventor: Nikola Nedovic
  • Patent number: 8248169
    Abstract: The semiconductor integrated circuit includes a first oscillator, a second oscillator (PLL), a third oscillator (ring oscillator), a selector that switches, in turn, based on a clock of the third oscillator, and outputs a clock of the first oscillator or a clock of the second oscillator, and a determination circuit that counts up or counts down the clock output from the selector, based on the clock of the third oscillator, determines the correspondence of the clock output from the selector and the clock of the third oscillator, based on a result of the counting up or the counting down, and determines whether either of the clock output from the selector or the clock of the third oscillator occur an abnormal oscillation.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: August 21, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Masanori Honda
  • Patent number: 8250399
    Abstract: Aspects of the disclosure provide a network device. The network device includes a first port coupled to a first device to communicate with the first device, and a clock wander compensation module. The first port recovers a first clock based on first signals received from the first device. The clock wander compensation module includes a global counter configured to count system clock cycles based on a system clock of the network device, and a first port counter configured to count first clock cycles based on the recovered first clock. Further, the first port transmits a first pause frame to the first device based on the global counter and the first port counter.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: August 21, 2012
    Assignees: Marvell International Ltd., Marvell Israel (M.I.S.L.) Ltd.
    Inventors: Tal Mizrahi, Carmi Arad, Martin White, Tsahi Daniel
  • Publication number: 20120161885
    Abstract: There is provided an aging diagnostic device including: a reference ring oscillator (101) that constitutes a ring oscillator using an odd-numbered plurality of logic gates constituted using a CMOS circuit; a test ring oscillator (102) that constitutes a ring oscillator using an odd-numbered plurality of logic gates having the same configuration as that of the logic gate; a load unit (104) that inputs a load signal to the test ring oscillator (102); a control unit (105) that simultaneously inputs a control signal instructing a start of oscillation of the reference ring oscillator (101) and the test ring oscillator (102) to the reference ring oscillator (101) and the test ring oscillator (102); and a comparison unit (103) that compares differences in the amount of movement of pulses within the reference ring oscillator (101) and the test ring oscillator (102), respectively, in the same time.
    Type: Application
    Filed: September 1, 2010
    Publication date: June 28, 2012
    Applicant: NEC CORPORATION
    Inventors: Eisuke Saneyoshi, Koichi Nose, Masayuki Mizuno
  • Patent number: 8207763
    Abstract: A semiconductor non-linear channelizer device comprises an array of N first order, bi-stable semiconductor circuit cells. The circuit cells are uni-directionally coupled from a first circuit cell to another circuit cell, where N is an integer greater than 1. A signal input trace is coupled to each of the circuit cells and a signal output trace is coupled from each of the circuit cells.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: June 26, 2012
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Visarath In, Patrick Anton Longhini, Yong (Andy) An Kho, Joseph D. Neff, Norman Liu
  • Patent number: 8174325
    Abstract: The present invention provides an array of tunable, injection-locking oscillators which are scalable to higher frequencies and measure the entire relevant frequency space simultaneously. The scalable, highly-parallelized, adaptive receiver architecture uses arrays of tunable, injection-locking nonlinear oscillator rings for broad spectrum RF analysis. Three separate and different microelectronic circuit configurations, each having a different type of readout, are described. The embodiments are designed to be incorporated as a subsystem in any type of powered system in which a fast image of the broader spectrum is valuable, when no information about the location of signals in the frequency space is predictable or forthcoming.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: May 8, 2012
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Daniel Leung, Joseph Neff, Norman Liu, Visarath In
  • Patent number: 8143954
    Abstract: A device can be coupled to an electrical load for supplying electrical power to the electrical load. The device contains an oscillator unit and an auxiliary oscillator unit. The oscillator unit is configured to generate an output signal of the device which can be supplied to the electrical load and which has a first frequency. The auxiliary oscillator unit is electrically coupled to the oscillator unit. The auxiliary oscillator unit is configured to excite the oscillator unit to oscillate at a second frequency greater than the first frequency. The auxiliary oscillator unit contains a timing element which is configured and arranged to terminate the excitation of the oscillator unit after the expiration of a pre-specified period of time after the start of the oscillator unit and the auxiliary oscillator unit.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: March 27, 2012
    Assignee: Continental Automotive GmbH
    Inventor: Stephan Bolz
  • Patent number: 8134886
    Abstract: Control signal oscillation filtering circuits, delay locked loops, clock synchronization methods and devices and systems incorporating the control signal oscillation filtering circuits are described. An oscillation filtering circuit includes a first oscillation filter configured to filter oscillations and a majority filter configured to average filter an output of a phase detector and generate in response thereto control signals to an adjustable delay line.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: March 13, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Yantao Ma
  • Patent number: 8134421
    Abstract: A voltage control oscillator includes: first and second field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; third and fourth field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; a first inductor connected between the drain of the first field effect transistor and the drain of the second field effect transistor; a second inductor connected between the drain of the third field effect transistor and the drain of the fourth field effect transistor; a third inductor magnetically coupled to the first inductor; a fourth inductor magnetically coupled to the second inductor; a first capacitor that capacitively couples one end of the third inductor and one end of the fourth inductor; and a second capacitor that capacitively couples the other end of the third inductor and the other end of the fourth inductor.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: March 13, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Hirashiki, Shinichiro Ishizuka, Nobuyuki Itoh
  • Patent number: 8125282
    Abstract: In a dual band capable voltage controlled oscillator VCO circuit comprising two voltage controlled oscillator units VCO1, VCO2, the voltage controlled oscillator units VCO1, VCO2 are synchronized and connected via at least two coupled transmission lines TL1, TL2, the transmission lines (TL1, TL2) are arranged to operate according to one of two modes to enable varying a combined inductance of the synchronized oscillator units VCO1, VCO2 and the oscillation frequency for the voltage controlled oscillator circuit VCO.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: February 28, 2012
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Mingquan Bao, Björn Albinsson