Abstract: The present disclosure relates to integrated circuits. One example integrated circuit includes a first resonant circuit, a second resonant circuit, and at least one connection circuit. The first resonant circuit includes a first inductor, and the second resonant circuit includes a second inductor. The first inductor includes a first port, and the second inductor includes a second port. The at least one connection circuit is connected between the first port and the second port. The at least one connection circuit provides an electrical connection between the first port and the second port.

Abstract: Apparatus and methods for rotary traveling wave oscillators (RTWOs) are disclosed. In certain embodiments, an RTWO system include an RTWO ring that carries a traveling wave, a plurality of selectable capacitors distributed around the RTWO ring and each operable in a selected state and an unselected state, and a decoder system that controls selection of the plurality of selectable capacitors based on a frequency tuning code. The frequency tuning code includes a fine tuning code and a coarse tuning code, and the decoder system is operable to maintain a constant number of capacitors that toggle state for each value of the fine tuning code.

Abstract: A first branch group circuit includes a first branch circuit receiving a first RF input signal and first control information; and a second branch circuit receiving the first input signal and second control information. Each of the first and second branch circuits includes a power amplifier. The second control information enables the second branch circuit to be switched on or off while the first branch circuit remains on. A second branch group circuit includes: a third branch circuit receiving a second RF input signal and third control information; and a fourth branch circuit receiving the second input signal and fourth control information. Each of the third and fourth branch circuits includes a power amplifier. The fourth control information enables the fourth branch circuit to be switched on or off while the third branch circuit remains on. A combiner combines output signals of the power amplifiers to produce an output signal.

Abstract: An oscillator including two sequentially connected pulse generation circuits is disclosed. Each pulse generation circuit includes a charge/discharge circuit and a switch circuit and outputs a first or second signal depending on an input signal. The switch circuit controls the charge/discharge circuit so that the latter is charged when the input signal is at a first level and discharged when the input signal is at a second level higher than the first level. When the input signal is at the first level, the first signal is at the first level and the second signal is at the second level. When the input signal is at the second level, the first signal is at the second level and the second signal is at the first level. Upon completion of discharge of the charge/discharge circuit, the first signal changes to the first level and the second signal changes to the second level.

Abstract: Adjustable integrated circuits and methods for designing the same are provided. In one embodiment, a method of designing an integrated circuit includes determining a plurality of design criteria of the integrated circuit; designing a plurality of circuit blocks of the integrated circuit in accordance with the plurality of design criteria, where one or more circuit blocks in the plurality of circuit blocks include one or more feedback paths; designing a circuit performance monitor, where the circuit performance monitor includes one or more replica feedback paths corresponding to the one or more feedback paths in the one or more circuit blocks, and where the circuit performance monitor is configured to monitor feedback path information of the one or more replica feedback paths; verifying the plurality of circuit blocks and the circuit performance monitor to meet the plurality of design criteria; and producing a verified description of the integrated circuit for manufacturing.

Abstract: A multi-level, multi-branch outphasing amplifier (20-1) includes a first branch group circuit (22-1) including a first branch circuit (11) receiving a first RF input signal (S1(t)) and first control information (S11_Ctrl=VDD) and a second branch circuit (12) receiving the first input signal and second control information (S12_Ctrl). Each of the first (11) and second (12) branch circuits includes a power amplifier. The second control information enables the second branch circuit to be switched on or off while the first branch circuit (12) remains on. A second branch group circuit (22-2) includes a third branch circuit (21) receiving a second RF input signal (S2(t)) and third control information (S21_Ctrl=VDD) and a fourth branch circuit (22) receiving the second input signal (S2(t)) and fourth control information (S22_Ctrl). Each of the third and fourth branch circuits includes a power amplifier.

Abstract: The present invention relates to a technique capable of implementing a frequency synthesizer circuit separated into a frequency synthesizer circuit part and an injection locked PLL circuit part and sequentially performing a frequency synthesizer lock operation and an injection lock operation to implement fast frequency and phase locking. The present invention comprises: a frequency synthesizer configured to perform a frequency and phase lock operation according to fractional number information and a first reference cock signal supplied from outside and thereby output a reset signal and a second reference clock signal; and an injection locked PLL configured to start a frequency lock operation after being reset by the reset signal inputted when the frequency synthesizer is frequency-locked, receive the second reference clock signal as a reference clock, multiply the second reference clock signal by an integer multiple of target frequency, and output an output clock signal.

Abstract: An aging detection circuit is provided. The aging detection circuit is configured on a chip and includes a testing circuit and an aging signal generation circuit. The testing circuit is electrically coupled to the aging signal generation circuit. The testing circuit generates an output signal. The aging signal generation circuit includes a signal generation circuit and a selection circuit. The signal generation circuit generates multiple input signals having different frequencies. The selection circuit selectively outputs one of the input signals as an aging signal to an input terminal of the testing circuit or feeds back the output signal generated by the testing circuit to the input terminal of the testing circuit.

Abstract: Communications data interface sampling systems configured effectively with fully-symmetric dual-loop traveling wave oscillators providing high frequency evenly spaced multiple phases to represent analog-in-nature continuous signals as digital stream of samples with best approximation to the original signal.

Abstract: A Pumped Distributed Wave Oscillator (PDWO) that provides a high purity accurate signal source with multiple oscillation phases. High-accuracy, high-frequency oscillation phases open paths to high performance phased-array transceiver design. Additional noise-canceling, noise-shaping circuit techniques result in enhanced sensitivity in radio design.

Abstract: A loading state determiner for determining a loading state of an electric power source including a source impedance includes a voltage drop determination circuit which is implemented to provide, based on a detection of an instantaneous current provided under load by the power source to a load, an electric quantity describing a voltage drop at a source impedance of the power source. Further, the loading state determiner includes an evaluation circuit which is implemented to obtain, based on electric quantity describing the voltage drop at the source impedance of the power source and an electric quantity describing a terminal voltage of the power source, a load state signal carrying information on an instantaneous relation between the terminal voltage of the power source and a no-load voltage of the power source.

Abstract: A ring-oscillator-based on-chip sensor (OCS) includes a substrate having a semiconductor surface upon which the OCS is formed. The OCS includes an odd number of digital logic stages formed in and on the semiconductor surface including a first stage and a last stage each including at least one NOR gate including a first gate stack and/or a NAND gate including a second gate stack. A feedback connection is from an output of the last stage to an input of the first stage. At least one discharge path including at least a first p-channel metal-oxide semiconductor (PMOS) device is coupled between the first gate stack and a ground pad, and/or at least one charge path including at least a first n-channel metal-oxide semiconductor (NMOS) device is coupled between the second gate stack a power supply pad.

Abstract: A circuit includes a coupling structure and a first inductive device. The coupling structure includes two or more conductive loops and a set of conductive paths electrically connecting the two or more conductive loops. The first inductive device is magnetically coupled with a first conductive loop of the two or more conductive loops.

Abstract: A circuit includes a first oscillator and a second oscillator. The first oscillator includes an inductive device, a capacitive device, and an active feedback device configured to output a first output signal having a predetermined frequency according to electrical characteristics of the inductive device of the first oscillator and electrical characteristics of the capacitive device of the first oscillator. The second oscillator includes an inductive device, a capacitive device, and an active feedback device configured to output a second output signal having the predetermined frequency according to electrical characteristics of the inductive device of the second oscillator and electrical characteristics of the capacitive device of the second oscillator. The inductive device of the first oscillator and the inductive device of the second oscillator are magnetically coupled.

Abstract: A phase-modification circuit is described. This phase-modification circuit reduces jitter by injecting a divided reference clock in a phase-locked loop from an auxiliary oscillator and by effectively gradually and completely transferring its phase to a master oscillator. The phase-correction strength in the phase-modification circuit is increased by successively coupling an edge in the divided reference clock over many cycles of a clock in the master oscillator. By increasing the correction strength, the phase error is effectively nulled out, thereby reducing the total absolute peak jitter. Moreover, because the correction is gradual and successive, the phase-modification circuit also significantly reduces the cycle-to-cycle jitter and half-cycle or edge jitter.

Abstract: A clock distributor includes a first oscillator and a second oscillator, to each of which a signal controlling an oscillation frequency is input and to one of which a clock is input; a wiring portion that connects the first oscillator and the second oscillator; a first conversion element that converts an output from the first oscillator into electric current, and outputs a result to a first connection portion connecting to the wiring portion; a second conversion element that converts voltage of the first connection portion into electric current, and outputs a result to the first oscillator; a third conversion element that converts an output from the second oscillator into electric current, and outputs a result to a second connection portion connecting to the wiring portion; and a fourth conversion element that converts voltage of the second connection portion into electric current, and outputs a result to the second oscillator.

Abstract: An oscillator system includes a first oscillator, a second oscillator, and a changeover component. The first oscillator is configured to generate a first signal at a selected frequency. The second oscillator is configured to generate a second signal at about the selected frequency. The changeover component is configured to generate a changeover output signal according to the first signal and the second signal.

Abstract: An integrated circuit includes a plurality of resonant clock domains of a resonant clock network. Each resonant clock domain has at least one clock driver that supplies a portion of clock signal to an associated resonant clock domain. The resonant clock network operates in a resonant mode with inductors connected to pairs of resonant clock domains at boundaries between the resonant clock domains. Each inductor forms an LC circuit with clock load capacitance in the pair of resonant clock domains to which the inductor is connected.

Abstract: A voltage controlled oscillation circuit oscillates at an oscillation frequency corresponding to a control voltage. Injection locked oscillation circuits oscillate at an oscillation frequency corresponding to an output signal from the voltage controlled oscillation circuit. A mixer circuit performs a frequency conversion based on output signals from the injection locked oscillation circuits. A synchronization determiner determines the synchronous status between the injection locked oscillation circuits in accordance with an output signal from the mixer circuit. The injection locked oscillation circuits synchronize with each other at a frequency that is an integral multiple of the oscillation frequency of the voltage controlled oscillation circuit.

Abstract: Coupled timing oscillators are described. The coupling may be electrical, mechanical, or electromechanical in some instances. In some cases, the timing oscillators include mechanical resonators. Any number of timing oscillators may be coupled. The coupled timing oscillators may be operated cooperatively to produce an oscillating signal with improved signal characteristics, such as phase noise and jitter.

Abstract: A transceiver includes a phase lock loop (PLL) and a clock data recovery circuit (CDR). The phase lock loop generates a first level control signal. The clock data recovery circuit, coupled to the phase lock loop, locks an incoming data signal to generate a data recovery clock according to a second level control signal. Wherein the clock data recovery circuit receives the first level control signal to further control a frequency range of the data recovery clock.

Abstract: A clock distributor includes unit circuit parts each including an oscillator, a first element configured to convert output voltage of the oscillator into a current, a second element having a voltage current conversion characteristic of an opposite phase to that of the first element, the second element being feedback connected to the first element and the oscillator, a third element configured to convert output voltage of the oscillator into a current, a fourth element having a voltage current conversion characteristic of an opposite phase to that of the third element, the fourth element being feedback connected to the third element and the oscillator; a wiring part to connect a connection part of the first and second elements of a unit circuit part to a connection part of the third and fourth elements of another unit circuit part; and a synchronization circuit connected to the oscillator of a unit circuit part.

Abstract: An apparatus comprises a ring oscillator comprising a plurality of delay cells connected in cascade, a main injection apparatus comprising a plurality of main buffers, wherein the main buffers receive a reference clock from their inputs and the outputs of the main buffers are coupled to respective inputs of the delay cells and a replica injection apparatus comprising a plurality of replica buffers, wherein the replica buffers receive the reference clock from their inputs and the replica buffers are configured such that the replica buffers are tri-stated and each output is connected to ground when the ring oscillator operates in an injection-locked mode and each output is connected to ground through a capacitor when the ring oscillator operates in a calibration mode.

Abstract: A stochastic beating time-to-digital converter (TDC) can include triggered ring oscillator (TRO) and a stochastic TDC (sTDC). The TRO, when triggered by a reference signal edge, can generate a periodic TRO signal with a TRO period that is a selected ratio of a voltage-controlled oscillator (VCO) period. The TRO period can be greater than or less than the VCO period by the specified ratio. The sTDC with an event triggered memory can include an sTDC component with a plurality of groups of latches. Each group of latches can be configured to sample and store a VCO state at an edge of a TRO signal. The sTDC component can trigger a capture of a select number of VCO states of the group of latches when one latch in the group of latches transitions to a different digital state referred to as a transition edge.

Abstract: A tunable Injection-Locked Oscillator (ILO) having a wide locking range is used in a Local Oscillator (LO) of a wideband wireless transceiver to generate differential signals. The ILO includes a resonator with an adjustable natural oscillating frequency. In one example, the ILO is part of a quadrature divider that can lock onto a Phase-Locked Loop (PLL) output signal in a wide frequency band while achieving lower power consumption and lower phase noise than a differential latch type divider. The ILO is tuned by disabling a Voltage-Controlled Oscillator (VCO) from driving the ILO, adjusting the natural oscillating frequency, making a measurement indicative of the natural oscillating frequency, and determining whether the measurement is within a predetermined range. If the measurement is below the predetermined range, capacitances of resonators within the ILO are decreased, whereas if the measurement is above the predetermined range, capacitances of the resonators are increased.

Abstract: There is provided an aging diagnostic device including: a reference ring oscillator (101) that constitutes a ring oscillator using an odd-numbered plurality of logic gates constituted using a CMOS circuit; a test ring oscillator (102) that constitutes a ring oscillator using an odd-numbered plurality of logic gates having the same configuration as that of the logic gate; a load unit (104) that inputs a load signal to the test ring oscillator (102); a control unit (105) that simultaneously inputs a control signal instructing a start of oscillation of the reference ring oscillator (101) and the test ring oscillator (102) to the reference ring oscillator (101) and the test ring oscillator (102); and a comparison unit (103) that compares differences in the amount of movement of pulses within the reference ring oscillator (101) and the test ring oscillator (102), respectively, in the same time.

Abstract: A circuit including a first oscillator configured to oscillate at a first frequency; a second oscillator configured to oscillate at a second frequency, the second frequency being different from and one of a harmonic or sub-harmonic of the first frequency; and a coupling between the first oscillator and the second oscillator configured to injection lock at least one of the first oscillator and second oscillator to the other of the first oscillator and second oscillator.

Abstract: The high-frequency digitally controlled oscillator includes fully digital cells capable of being ported to any CMOS fabrication process. The oscillator has a basic modular architecture comprising a digitally controlled digital ring oscillator (DRO) having a plurality of delay stages, a counter divider and a selection multiplexer. The DRO generates the basic (intrinsic) high frequency range and the counter provides the remaining ranges through division by multiples of two. The multiplexer provides a selection mechanism for the required range of frequencies. Load capacitances to the delay stages are added/removed to control delay via utilization of a unique capacitive cell driven synchronously by two ring oscillators such that the capacitance could be added or removed utilizing the Miller effect. Moreover, multiple capacitive load cells can be added to the same stage.

Abstract: An electronic high frequency induction heater driver, for a variable spray fuel injection system, uses a scalable array of zero-voltage switching oscillators that utilize full and half-bridge topology wherein the semiconductor switches are synchronous within each bridge for function, and each bridge is synchronized for function along the entire array. The induction heater driver, upon receipt of a turn-on signal, multiplies a supply voltage through a self-oscillating series resonance, wherein one component of each tank resonator circuit comprises an induction heater coil magnetically coupled to an appropriate loss component so that fuel inside a fuel component is heated to a desired temperature.

Abstract: An electronic high frequency induction heater driver, for a variable spray fuel injection system, uses a scalable array of zero-voltage switching oscillators that utilize full and half-bridge topology with inductors between semiconductor switches wherein the semiconductor switches are synchronous within each bridge for function, and each bridge is synchronized for function along the entire array. The induction heater driver, upon receipt of a turn-on signal, multiplies a supply voltage through a self-oscillating series resonance, wherein one component of each tank resonator circuit comprises an induction heater coil magnetically coupled to an appropriate loss component so that fuel inside a fuel component is heated to a desired temperature.

Abstract: An injection-locked oscillator circuit includes a master oscillator, a slave oscillator, and an injection lock control circuit. The slave oscillator is decoupled from the master oscillator (for example, due to an unlock condition). When the slave is free running, its oscillating frequency is adjusted (for example, as a function of a supply voltage). After an amount of time, the slave is to be relocked to the master (for example, due the unlock condition no longer being present). The slave oscillating frequency is made to be slightly lower than the master oscillating frequency. The slave is then only recoupled to the master upon detection of an opposite-phase condition between the master oscillator output signal and the slave oscillator output signal. By only recoupling the slave to the master during opposite-phase conditions, frequency overshoots in the slave oscillating frequency are avoided that may otherwise occur were the recoupling done during in-phase conditions.

Abstract: A semiconductor integrated circuit capable of reliably detecting oscillation stop of a vibrator-type oscillation circuit and reliably restarting the oscillation circuit when oscillation stop is detected is provided. The semiconductor integrated circuit includes one or more main oscillation circuits configured to generate a main clock signal by a vibrator, a ring oscillator configured to always operate independently of the main oscillation circuit, a main clock detection circuit configured to monitor the main clock signal on the basis of an output clock signal of the ring oscillator and to determine an operation state of the main oscillation circuit, and an switch circuit configured to switch a combination of elements making up the main oscillation circuit in response to a detection result of the main clock detection circuit.

Abstract: An oscillator including two groups of elementary junctions having giant magnetoresistance effect traversed by electric currents, the junctions of each of the two groups being in series and energized by respective main currents and the voltages across the terminals of the groups being added together to provide a voltage on an output of the oscillating circuit. The voltage across the terminals of one or more junctions of a first group is applied to a first input of a phase comparator and the voltage across the terminals of one or more junctions of the other group is applied to another input of the phase comparator, the phase comparator providing on two outputs secondary currents of the same amplitude and of opposite signs, which are dependent on the mean phase difference between the voltages applied to the inputs, the secondary currents each being added to a respective main current.

Abstract: An apparatus includes an adjustable oscillator circuit configured to generate an output signal having a frequency that varies responsive to a frequency control signal and a frequency reference generator circuit configured to produce a frequency reference signal. The apparatus further includes a calibration circuit configured to determine a relationship of the output signal to the frequency reference signal and to enable and disable the frequency reference generator circuit based on the determined relationship.

Abstract: A rubidium oscillator or a cesium oscillator is used as a high stability oscillator, and an OCXO being a metastable oscillator which is inferior in a long-term frequency stability compared with the above oscillators but has a high short-term frequency stability is used as a backup. There is prepared a table in which an elapsed time since an occurrence of an abnormality in the high stability oscillator and weighting (use ratio) of use of the both oscillators is corresponded, and by using this table, after the high stability oscillator recovers, an oscillation frequency of the metastable oscillator is used by 100% initially, but thereafter the weighting (use ratio) of use of the metastable oscillator is made smaller and the use ratio of the high stability oscillator is made larger in stages.

Abstract: Control signal oscillation filtering circuits, delay locked loops, clock synchronization methods and devices and systems incorporating the control signal oscillation filtering circuits are described. An oscillation filtering circuit includes a first oscillation filter configured to filter oscillations and a majority filter configured to average filter an output of a phase detector and generate in response thereto control signals to an adjustable delay line.

Abstract: An IC includes first and second pads. The first pad is configured to receive an external clock. Alternatively, the first and second pads are configured to be coupled to a crystal oscillator and receive a reference clock. Alternatively, the second pad is configured to be grounded. The IC includes an internal oscillator for generating an internal clock, and an oscillator detector coupled to the second pad. The oscillator detector includes a transistor having a gate coupled to the second pad configured to pull a source-drain region to a first state if the second pad receives the reference clock or allow the source-drain region to be pulled to a second state if the second pad is grounded. The IC includes a buffer for transferring the first state to the internal oscillator for keeping the internal oscillator enabled and transferring the second state to the internal oscillator for disabling the internal oscillator.

Abstract: A circuit interconnection structure for synchronizing a network of oscillators placed on a semiconductor substrate. One such structure comprises a first synchronizing circuit electrically coupled to a second synchronizing circuit through tunable delay circuits. Also disclosed are methods to tune oscillators placed in different regions of a circuit having multiple clock domains by estimating the relative slack of a first group of signals within the circuit with regard to the period of a first clock domain, and estimating the relative slack of the second group of signals within the circuit with regard to the period of second clock domain, wherein the estimating is performed at process and operational corners that cover the variability of the circuit at different speed conditions, then calculating tuning values for the oscillator delays for each region such that the oscillator delay slack matches the worst relative slack of the signals of the same region.

Abstract: Electronic circuitry comprising operational circuits of active switching type requiring timing signals, and conductive means for distributing said timing signals to the operational circuits, wherein the timing signal distribution means includes a signal path that has different phases of a drive signal are supplied via active means at different positions about the signal path where that path exhibits endless electro-magnetic continuity without signal phase inversion or has interconnections with another signal path having different substantially unidirectional signal flow where there is no endless electromagnetic continuity between those signal paths and generally has non-linear associated circuit means where the signal path is of a transmission line nature.

Abstract: A circuit for producing a synchronized output of multiple ring oscillators is disclosed. In one embodiment, the circuit includes a first ring oscillator configured to generate a first periodic signal and a second ring oscillator configured to generate a second periodic signal. The circuit may further include a selection unit coupled to receive the first periodic signal and the second periodic signal. The selection unit is configured to convey a first clock edge into each of the first and second ring oscillators responsive to a most recently received rising edge from one of the first and second periodic signals. The selection unit is further configured to convey a second clock edge into each of the first and second ring oscillators responsive to a most recently received falling edge from one of the first and second periodic signals, wherein the first and second clock edges are opposite in direction.

Abstract: An inductor architecture for resonant clock distribution networks is described. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture exhibits no inductor overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.

Abstract: An oscillator synchronization system employs two oscillators, each of which includes an integrator which provides a ramping signal at its output, a comparator which receives the ramping signal and a reference signal at respective inputs and toggles an output when the ramping voltage crosses the reference signal, and a one-shot circuit that generates the integrator's reset signal when triggered. The system is preferably arranged such that the oscillators can be operated independently, in which case each oscillator's one-shot is triggered by its own comparator output, or synchronously, in which case each oscillator's one-shot is triggered by the other oscillator's comparator output—with the ramp signal of each oscillator operating to reset the integrator of the other oscillator. The oscillators are typically out-of-phase when synchronized, with the phase difference varying with the magnitude of the reference signals applied to the comparators.

Abstract: An oscillator synchronization system employs two oscillators, each of which includes an integrator which provides a ramping signal at its output, a comparator which receives the ramping signal and a reference signal at respective inputs and toggles an output when the ramping voltage crosses the reference signal, and a one-shot circuit that generates the integrator's reset signal when triggered. The system is preferably arranged such that the oscillators can be operated independently, in which case each oscillator's one-shot is triggered by its own comparator output, or synchronously, in which case each oscillator's one-shot is triggered by the other oscillator's comparator output—with the ramp signal of each oscillator operating to reset the integrator of the other oscillator. The oscillators are typically out-of-phase when synchronized, with the phase difference varying with the magnitude of the reference signals applied to the comparators.

Abstract: A circuit for producing a synchronized output of multiple ring oscillators is disclosed. In one embodiment, the circuit includes a first ring oscillator configured to generate a first periodic signal and a second ring oscillator configured to generate a second periodic signal. The circuit may further include a selection unit coupled to receive the first periodic signal and the second periodic signal. The selection unit is configured to convey a first clock edge into each of the first and second ring oscillators responsive to a most recently received rising edge from one of the first and second periodic signals. The selection unit is further configured to convey a second clock edge into each of the first and second ring oscillators responsive to a most recently received falling edge from one of the first and second periodic signals, wherein the first and second clock edges are opposite in direction.

Abstract: A method is provided for generating local oscillator signals for a mixer. The method includes providing a reference frequency signal and generating a differential in-phase signal and a differential quadrature signal from the reference frequency signal. The method further includes re-clocking each of the differential in-phase and differential quadrature signals using the reference frequency signal. The re-clocked differential in-phase and differential quadrature signals are then provided as the local oscillator signals for the mixer.

Abstract: In one embodiment, a method includes generating, by a LCVCO, a first signal having a first phase based on a resonant frequency of a first LC tank; generating, by a second LCVCO, a second periodic signal having a second phase based on a resonant frequency of a second LC tank; determining a phase offset between the first LC tank and the second LC tank based on the first and second signals; generating a first output signal and a second output signal based on the determined phase offset; and adjusting the phase offset such that the phase offset is substantially equal to a predetermined phase offset. In one embodiment, the adjusting comprises modulating a first impedance of the first LC tank based on the first output signal, and/or modulating a second impedance of the second LC tank based on the second output signal.

Abstract: A clock signal distributing device includes a plurality of LC resonant oscillators, each resonating at a frequency conforming to values of a first inductor and a first capacitor to oscillate a signal, an injection locked LC resonant oscillator that resonates at a frequency conforming to values of a second inductor and a second capacitor to oscillate a signal which is synchronous with an input clock signal, and transmission lines that connect oscillation nodes of the plurality of LC resonant oscillators and the injection locked LC resonant oscillator with one another.

Abstract: Aspects of the disclosure provide a network device. The network device includes a first port coupled to a first device to communicate with the first device, and a clock wander compensation module. The first port recovers a first clock based on first signals received from the first device. The clock wander compensation module includes a global counter configured to count system clock cycles based on a system clock of the network device, and a first port counter configured to count first clock cycles based on the recovered first clock. Further, the first port transmits a first pause frame to the first device based on the global counter and the first port counter.

Abstract: The semiconductor integrated circuit includes a first oscillator, a second oscillator (PLL), a third oscillator (ring oscillator), a selector that switches, in turn, based on a clock of the third oscillator, and outputs a clock of the first oscillator or a clock of the second oscillator, and a determination circuit that counts up or counts down the clock output from the selector, based on the clock of the third oscillator, determines the correspondence of the clock output from the selector and the clock of the third oscillator, based on a result of the counting up or the counting down, and determines whether either of the clock output from the selector or the clock of the third oscillator occur an abnormal oscillation.

Abstract: The present invention discloses a radio frequency receiver and a receiving method, where the method includes: performing band splitting on a radio frequency signal of multiple carriers to obtain at least one band signal, and outputting the signal; separately performing filtering and amplification processing on the at least one band signal to obtain at least one processed signal; generating multiple oscillation signals; and selectively receiving a processed signal, of the at least one processed signal, that includes a target carrier; receiving an oscillation signal corresponding to the target carrier; selectively selecting a frequency division ratio from multiple frequency division ratios; using the frequency division ratio to perform frequency division on the received oscillation signal to obtain a local oscillator signal; using the local oscillator signal to perform frequency mixing on the received processed signal that includes the target carrier to obtain a mixed signal.