Abstract: There is provided an aging diagnostic device including: a reference ring oscillator (101) that constitutes a ring oscillator using an odd-numbered plurality of logic gates constituted using a CMOS circuit; a test ring oscillator (102) that constitutes a ring oscillator using an odd-numbered plurality of logic gates having the same configuration as that of the logic gate; a load unit (104) that inputs a load signal to the test ring oscillator (102); a control unit (105) that simultaneously inputs a control signal instructing a start of oscillation of the reference ring oscillator (101) and the test ring oscillator (102) to the reference ring oscillator (101) and the test ring oscillator (102); and a comparison unit (103) that compares differences in the amount of movement of pulses within the reference ring oscillator (101) and the test ring oscillator (102), respectively, in the same time.

Abstract: A semiconductor non-linear channelizer device comprises an array of N first order, bi-stable semiconductor circuit cells. The circuit cells are uni-directionally coupled from a first circuit cell to another circuit cell, where N is an integer greater than 1. A signal input trace is coupled to each of the circuit cells and a signal output trace is coupled from each of the circuit cells.

Abstract: The present invention provides an array of tunable, injection-locking oscillators which are scalable to higher frequencies and measure the entire relevant frequency space simultaneously. The scalable, highly-parallelized, adaptive receiver architecture uses arrays of tunable, injection-locking nonlinear oscillator rings for broad spectrum RF analysis. Three separate and different microelectronic circuit configurations, each having a different type of readout, are described. The embodiments are designed to be incorporated as a subsystem in any type of powered system in which a fast image of the broader spectrum is valuable, when no information about the location of signals in the frequency space is predictable or forthcoming.

Abstract: A device can be coupled to an electrical load for supplying electrical power to the electrical load. The device contains an oscillator unit and an auxiliary oscillator unit. The oscillator unit is configured to generate an output signal of the device which can be supplied to the electrical load and which has a first frequency. The auxiliary oscillator unit is electrically coupled to the oscillator unit. The auxiliary oscillator unit is configured to excite the oscillator unit to oscillate at a second frequency greater than the first frequency. The auxiliary oscillator unit contains a timing element which is configured and arranged to terminate the excitation of the oscillator unit after the expiration of a pre-specified period of time after the start of the oscillator unit and the auxiliary oscillator unit.

Abstract: A voltage control oscillator includes: first and second field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; third and fourth field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; a first inductor connected between the drain of the first field effect transistor and the drain of the second field effect transistor; a second inductor connected between the drain of the third field effect transistor and the drain of the fourth field effect transistor; a third inductor magnetically coupled to the first inductor; a fourth inductor magnetically coupled to the second inductor; a first capacitor that capacitively couples one end of the third inductor and one end of the fourth inductor; and a second capacitor that capacitively couples the other end of the third inductor and the other end of the fourth inductor.

Abstract: Control signal oscillation filtering circuits, delay locked loops, clock synchronization methods and devices and systems incorporating the control signal oscillation filtering circuits are described. An oscillation filtering circuit includes a first oscillation filter configured to filter oscillations and a majority filter configured to average filter an output of a phase detector and generate in response thereto control signals to an adjustable delay line.

Abstract: In a dual band capable voltage controlled oscillator VCO circuit comprising two voltage controlled oscillator units VCO1, VCO2, the voltage controlled oscillator units VCO1, VCO2 are synchronized and connected via at least two coupled transmission lines TL1, TL2, the transmission lines (TL1, TL2) are arranged to operate according to one of two modes to enable varying a combined inductance of the synchronized oscillator units VCO1, VCO2 and the oscillation frequency for the voltage controlled oscillator circuit VCO.

Abstract: Local oscillator circuitry for an antenna array is disclosed. The circuitry includes an array of rotary traveling wave oscillators which are arranged in a pattern over an area and coupled so as to make them coherent. This provides for a set of phase synchronous local oscillators distributed over a large area. The array also includes a plurality of phase shifters each of which is connected to one of the rotary oscillators to provide a phase shifted local oscillator for the array. The phase shifter optionally includes a cycle counter that is configured to count cycles of the rotary oscillator to which it is connected and control circuitry that is then operative to provide a shifted rotary oscillator output based on the count from the cycle counter. A system and method for operating a true-time delay phased array antenna system. The system includes a plurality of antenna element circuits for driving or receiving an rf signal from the elements of the array.

Abstract: An oscillation circuit, a driving circuit thereof, and a driving method thereof are provided. The driving circuit generates a second enable signal according to an output signal of an oscillator and a first enable signal. The second enable signal is transmitted to the oscillator. When a number of waves of the output signal within a predetermined period is smaller than a predetermined value, the driving circuit adjusts a voltage level of the second enable signal. A voltage level of the first enable signal is equal to an enable voltage level. Through variations in voltage levels of the second enable signal, the oscillator is triggered to oscillate.

Abstract: The device has a component providing an outlet signal whose oscillation frequency depends on a physical unit to be measured, and a reference oscillator. A phase comparison component compares the component and the oscillator for control on the component or for mutual control. A synchronization unit permits alternatively blocking and oscillation of the component. A determination unit determines a derivative signal from evolution of the output signal of the component. The device also includes an electrostatic type keyboard having an electrode assembly.

Abstract: A synchronized clock system, for use with an electronic system having several system nodes requiring a synchronized clock signal. The clock system may be formed in either discrete form or in integrated form, or in any combination, and includes a first synch bus and a second synch bus, isolated from the first synch bus, and at least one pair and preferably several pairs of SXO modules connected to the busses in alternating fashion. Each of the system nodes is connected at a different one of any number of arbitrarily selected connection points anywhere along the first bus. The points along the busses at which the SXO modules are connected are spaced roughly equidistantly apart. The system nodes are connected to the bus by means of signal conditioning circuits, which may include correction circuits, an amplifier, a frequency multiplier, a logic translator and a fan buffer.

Abstract: An apparatus comprises a structure, an array of oscillator units, a plurality of waveguides in the structure, and a synchronizing cavity located within the structure. The array of oscillator units has a plurality of rows and a plurality of columns associated with the structure. Oscillator units in a row within the array of oscillator units are directly coupled to each other. The plurality of waveguides is configured to couple the array of oscillator units to the synchronizing cavity. The synchronizing cavity is configured to cause the array of oscillator units to operate at substantially a common frequency.

Abstract: This invention makes it possible to reduce a power consumption of an electronic circuit (microcomputer, for example) while preventing malfunctioning of an oscillator by appropriately setting a power supply impedance of a low frequency oscillator corresponding to an operation mode. A high frequency oscillator, a medium frequency oscillator and a low frequency oscillator are provided as sources of system clocks. In addition, there is provided a quartz oscillator to generate a clock for a timepiece. When the high frequency oscillator is in operation, a power supply impedance of the quartz oscillator is reduced to improve a noise tolerance. In a waiting period during which the high frequency oscillator, the medium frequency oscillator and the low frequency oscillator are halted, on the other hand, the power supply impedance of the quartz oscillator is increased to suppress the power consumption.

Abstract: A method is provided for switching between two oscillator signals within an alignment element. In accordance with the method, one of the two oscillator signals one is selected as a first master signal in order to provide an output stepping signal at an output of the alignment element. The method comprises introducing a virtual stepping signal when a switch between the two oscillator signals occurs or when a failure in the first master signal is detected. The method further comprises sending the virtual stepping signal to the output of the alignment element in the event of a switch until an alignment with a new master signal is completed.

Abstract: A multi-phase ultra-wideband signal generator uses differential pulse oscillators. The multi-phase ultra-wideband signal generator using differential pulse oscillators includes N pulse oscillators for generating pulse signals based on a supply of power, and further comprises N inverting amplification units for outputting inverted amplified signals of output signals of the N pulse oscillators when a number of pulse oscillators is at least two, wherein, when the number of pulse oscillators is an even or odd number, the pulse oscillators are arrayed such that they have a connection form in which output terminals OUT(+) and OUT(?) of a relevant pulse oscillator are connected to output terminals OUT(+) and OUT(?) of a next pulse oscillator through a relevant inverting amplification unit, and the connection form is consecutively applied to the pulse oscillators.

Abstract: An apparatus comprises a structure, an array of oscillator units, a plurality of waveguides in the structure, and a synchronizing cavity located within the structure. The array of oscillator units has a plurality of rows and a plurality of columns associated with the structure. Oscillator units in a row within the array of oscillator units are directly coupled to each other. The plurality of waveguides is configured to couple the array of oscillator units to the synchronizing cavity. The synchronizing cavity is configured to cause the array of oscillator units to operate at substantially a common frequency.

Abstract: Embodiments of the present invention include a low phase noise oscillator circuit using a current-reuse technique to reduce power consumption and improve phase noise, where the oscillator circuit comprises a first VCO coupled to a second VCO, and the outputs of the first and second VCOs are coupled with passive elements, such as capacitors. The overall power consumption of both the first and second VCOs is about the same as a single VCO. Furthermore, the phase noise is lowered by around 3 dB. Thus, the phase noise performance is improved without increasing the power consumption of the oscillator circuit.

Abstract: An injection locking clock generator can vary the free running frequency of an injection locking oscillator to broaden an operating frequency range of an oscillation signal injected to itself, thereby performing an injection locking with respect to all frequencies of an operating frequency range. The clock generator includes a main oscillator configured to generate oscillation signals of a frequency corresponding to a control voltage, and an injection locking oscillator configured to generate division signals synchronized with the oscillation signals by dividing the oscillation signals, wherein a free running frequency of the injection locking oscillator is set according to the frequency of the oscillation signals.

Abstract: Multiple microwave oscillators can be phase locked such that the power output of multiple oscillators can be coherently combined to achieve a single output which has the total sum power of the multiple oscillators. Multiple oscillators assembled in a power combining array are phase locked using a locking signal provided at each oscillator via strategic placement of a partial obstruction between combined multiple oscillators and a load. This locking signal includes a minimum threshold level and preselected phase. A method for phase locking multiple microwave oscillators includes steps of combining power output of multiple microwave oscillators to achieve a single output to a load and inserting a partial obstruction between said at least two multiple oscillators and said load. The partial obstruction configured to provide a combined microwave oscillator signal including a minimum threshold and preselected phase.

Abstract: A device includes a plurality of channel-capture circuits. Each circuit may include an array of N non-linear oscillators, wherein N?3, circularly connected to each other in series such that unidirectional signal flow occurs between the oscillators. Each circuit may be configured to capture a respective channel signal from a wideband signal containing a plurality of channel signals and convert its captured channel signal to a lower frequency. Each oscillator may include an oscillator input configured to receive an output signal from another oscillator, an oscillator output configured to provide an output for an input of another oscillator, a frequency capture input configured to receive at least a portion of the wideband signal, at least two amplifiers, and a control capacitor coupled to the output of the amplifiers. An analog-to-digital converter may be coupled to the output of each channel-capture circuit.

Abstract: Systems and methods for distributing a clock signal are disclosed. In some embodiments, systems for distributing a clock signal include a plurality of resonant oscillators, each comprising an inductor; and a differential clock grid that distributes the clock signal. The differential clock grid is coupled to the plurality of resonant oscillators and the clock signal, and the inductances of the inductors are configured such that a resonant frequency of the plurality of resonant oscillators is substantially equal to the frequency of the clock signal.

Abstract: A clock signal distributing device includes a plurality of LC resonant oscillators, each resonating at a frequency conforming to values of a first inductor and a first capacitor to oscillate a signal, an injection locked LC resonant oscillator that resonates at a frequency conforming to values of a second inductor and a second capacitor to oscillate a signal which is synchronous with an input clock signal, and transmission lines that connect oscillation nodes of the plurality of LC resonant oscillators and the injection locked LC resonant oscillator with one another.

Abstract: LC resonant voltage control oscillators are adopted as voltage control oscillators for the purpose of providing a clock generating and distributing apparatus that can generate and distribute a clock signal of high precision even in a high-frequency region of several giga hertz or higher, and of providing a distributive VCO-type clock generating and distributing apparatus in which voltage control oscillators oscillate in the same phase, and which can generate a clock signal of a desired frequency and distributes a high-frequency clock signal to each part within a chip more stably even in a high-frequency region reaching 20 GHz. Furthermore, an inductor component of a wire connecting the oscillation nodes of the oscillators is made relatively small, or the LC resonant oscillators are oscillated in synchronization by using injection locking, whereby the LC resonant voltage control oscillators stably oscillate in the same phase.

Abstract: Ring oscillator circuitry is provided. The ring oscillator circuitry may include a loop of inverters. A control gate may be interposed in the loop to control operation of the loop. The control gate may be activated using a ring oscillator trigger signal. During application of the trigger signal, the trigger signal may become degraded due to circuit parasitics. Trigger signal conditioning circuitry may be used to remove noise from the degraded trigger signal. A version of the trigger signal that has been conditioned by the trigger signal conditioning circuitry may be applied to a control input of the control gate. The trigger signal conditioning circuitry may include a low pass filter, a hysteresis circuit, and a two-stage buffer. The two-stage buffer may be formed from transistors with the same characteristics as the transistors in the inverters of the ring oscillator loop.

Abstract: Frequency synthesizer circuitry employs a delay line. A reference clock signal propagates through successive stages of the delay line, and the currents drawn by output buffers of all of the stages are added at a common node. The common node current is converted to a voltage, which is AC-coupled to an output buffer ring oscillator of the frequency synthesizer. The output buffer ring oscillator includes a plurality of inverters connected in a series. A feedback connection including a resistor is provided from an output node of the last inverter to an input node of the first inverter.

Abstract: A crystal oscillator-based module, which includes a crystal resonator receiving a conditioned signal from a first bus and passing a resonator signal to a sustaining stage amplifier. A synchronization range expansion circuit is connected between a gain control network and the resonator. A tri-state buffer has a main input connected to receive the resonator signal through a buffer. The output of the tri-state buffer is connected to a second bus, through a matching network if necessary. A synchronous clock system can be formed by connecting these modules alternately to the two busses. The tri-state buffer also has a control input, which may be connected to a delay circuit between Vcc and ground, so as to allow hot swapping and for other benefits.

Abstract: Methods and systems to provide digitally controlled crystal oscillators are disclosed. One example method includes determining a state of an oscillator system and selecting a first output of a digitally controlled crystal oscillator or a second output of a second oscillator based on the determination. In an example implementation, the second oscillator is a ring oscillator.

Abstract: A crystal oscillator-based module, which includes a crystal resonator receiving a conditioned signal from a first bus and passing a resonator signal to a sustaining stage amplifier. A synchronization range expansion circuit is connected between a gain control network and the resonator. A tri-state buffer has a main input connected to receive the resonator signal through a buffer. The output of the tri-state buffer is connected to a second bus, through a matching network if necessary. A synchronous clock system can be formed by connecting these modules alternately to the two busses. The tri-state buffer also has a control input, which may be connected to a delay circuit between Vcc and ground, so as to allow hot swapping and for other benefits.

Abstract: The device resonant comprises a plurality of synchronized oscillators. Each oscillator comprises a resonator which comprises detection means providing detection signals representative of oscillation of the resonator to a feedback loop connected to an excitation input of the resonator. The detection signals control the conductivity of the feedback loop of the oscillator. The excitation inputs of all the resonators are connected to a common point which constitutes the output of the resonant device. A capacitive load is connected between said common point and a reference voltage.

Abstract: A Trigger-Mode Distributed Wave Oscillator that provides accurate multiple phases of an oscillation and a method of use of the same. An auxiliary oscillator triggers an oscillation on independent conductor loops or rings forming a differential transmission medium for the oscillation wave. Once the oscillation wave is triggered, the auxiliary oscillator can be powered down to turn it off, and the wave can sustain itself indefinitely through active amplifying devices which can compensate for losses in the conductors.

Abstract: An oscillator structure has a sync signal processor with an input interface for an external clock based sync signal and an output interface for a duty cycle indication signal depending on a signal property of the sync signal and an oscillator with an input interface for the duty cycle indication signal and the sync signal and an output interface for an oscillation signal synchronized with the external clock and having a duty cycle adjusted according to the duty cycle indication signal.

Abstract: The present invention relates to a control method for the operation modes of an oscillator and the apparatus thereof, for which the method and the apparatus can be applied to the electronic circuits with multi-operation modes of the oscillator so as to correctly choose the desirable oscillator operation mode. Furthermore, an oscillator checking circuit sets up the oscillation mode automatically and judges if the oscillator operates properly. Hence, there is no need for the user to set up the oscillator operation mode manually.

Abstract: An injection-locked frequency divider includes a ring oscillator, a signal injection circuit, a first adjustable load circuit and a second adjustable load circuit. The ring oscillator generates an oscillation signal according to a differential signal outputted by the signal injection circuit. According to an adjustable voltage, the first and second adjustable load circuits can respectively change equivalent impedances of the first adjustable load circuit and the second adjustable load circuit so that a free-running frequency of the oscillation signal of the ring oscillator is adjusted and an injection-locked frequency range of the injection-locked frequency divider is expanded.

Abstract: A system for generating a multiple phase clock is provided. The system includes a ring oscillator structure for generating multiple phases. The structure includes two or more unit oscillators, each unit oscillator implemented by a ring oscillator having M stages. The structure also includes a horizontal loop coupling the two or more unit oscillators to generate multiple phases. The number of phases generated is equal to the product of the number of unit oscillators and M. Another structure generates multiple phases using a multi-dimensional oscillator including ring oscillators constructed as vertical and horizontal loops with shared elements between the oscillators. A memory system includes a ring oscillator structure with vertical and horizontal loops, the ring oscillator structure receiving an input clock and outputting a multiple phase clock to one or more of a memory controller, memory devices and a memory interface device.

Abstract: An L-C resonant circuit with an adjustable resonance frequency, having a capacitor and a first inductor electrically coupled together and a second inductor magnetically coupled to the first inductor. Additionally, there is a control circuit to sense a signal representing a first current flowing through the first inductor and to force through the second inductor a second current that is a replica of the first current for setting the adjustable resonance frequency of the L-C resonant circuit.

Abstract: One aspect relates to an oscillator, and various oscillator embodiments comprise an amplifier and line driver with an input and an output and a transmission line with a predetermined transmission signal time delay. The output is adapted to produce an inverted signal with respect to a signal received at the input. The transmission line has a first end connected to the output and a second end connected to the input. Other aspects and embodiments are provided herein.

Abstract: A carrier generator for generating a carrier at a frequency of interest in a wireless communications system comprises an oscillator exhibiting a first impedance, the oscillator comprising an energy storage tank configured to generate a periodic signal, the energy storage tank including at least one inductor and at least one capacitor, and an amplifier coupled with the energy storage tank, the amplifier being configured to amplify an amplitude of the periodic signal, an antenna exhibiting a second impedance smaller than the first impedance, and a network coupled between the oscillator and the antenna, the network including at least one inductor or at least one capacitor and being configured to provide a third impedance such that a resultant impedance of the second impedance and the third impedance as viewed from the oscillator toward the antenna is large enough to facilitate the oscillator to generate the carrier at the frequency of interest.

Abstract: Timing signal generation and distribution are combined in operation of a signal path exhibiting endless electromagnetic continuity affording signal phase inversion and having associated regenerative active means. Two-or more-phases of substantially square-wave bipolar signals arise directly in traveling wave transmission-line embodiments compatible with semiconductor fabrication including CMOS. Coordination by attainable frequency synchronism with phase coherence for several such oscillating signal paths has intra-IC inter-IC and printed circuit board impact.

Abstract: A Trigger-Mode Distributed Wave Oscillator that provides accurate multiple phases of an oscillation and a method of use of the same. An auxiliary oscillator triggers an oscillation on independent conductor loops or rings forming a differential transmission medium for the oscillation wave. Once the oscillation wave is triggered, the auxiliary oscillator can be powered down to turn it off, and the wave can sustain itself indefinitely through active amplifying devices which can compensate for losses in the conductors.

Abstract: Control signal oscillation filtering circuits, delay-locked loops, clock synchronization methods and devices and system incorporating control signal oscillation filtering circuits is described. An oscillation filtering circuit includes a first oscillation filter configured to filter oscillations and a majority filter configured to average filter an output of a phase detector and generate in response thereto control signals to an adjustable delay line.

Abstract: A method for assisting the oscillating starting process of an electromechanical oscillator (10) has the following steps: detection of oscillator oscillations (1b, 1c) which occur in the output signal (1a) from the electromechanical oscillator (10); generation of an excitation pulse (3b) on the basis of a detected oscillator oscillation (1c); and feeding (3a) of the excitation pulse (3b) to the electromechanical oscillator (10).

Abstract: An oscillator is described. The oscillator includes segments of two-conductor transmission line being connected together by an odd number of connection means to form a closed loop. A plurality of current switches is connected to the conductors of the segments and a high impedance element, such as an inductor or transmission line, is connected to a conductor of at least one segment. The high impedance element sources current into the closed loop and the current switches sink current from one or the other of the conductors of the loop depending on the state of the switch. The switches cause a wave to be established and maintained on the loop and the wave changes the state of the switches as it oscillates. One embodiment of the switches employs npn transistors whose emitters are connected to a current source and another uses NMOS transistors.

Abstract: An improved receiver architecture and method for a wireless transceiver (e.g. for a headphone) is provided whereby the receiver, advantageously, enables the use of only one synthesizer circuit for both the RF-to-IF and IF-to-base band conversion processes which, in turn, provides for lower power consumption. The receiver includes an injection locked local receiver oscillator (Rx LO) which is used for the first mixing stage (i.e. the RF-to-IF conversion). The Rx LO 105 is thereby able to use a high-level harmonic of a relatively low reference frequency signal produced by that synthesizer (e.g. a fractional-N phase locked loop circuit (PLL)). The receiver further includes a tunable Q-enhanced IF filter 110 and complex sub-sampling and mixing down-conversion circuitry for the second conversion stage (i.e. IF-to-baseband conversion). The sampling frequency used for the second conversion stage is a harmonic of the reference frequency derived from the synthesizer (PLL).

Abstract: An oscillator coupling system includes a plurality of oscillating members and a plurality of delay members connecting at least two of the oscillating members. Between the delay members is a specific phase or time delay relationship such that characteristics of phase or frequency noise suppression correlation of the two oscillating members are coupled to each other by the delay members, thereby reducing noise autocorrelation while the oscillator coupling system is in operation, enhancing phase or frequency noise suppression, using no bulky elements such as solid state circulators, isolators and resonators, reducing signal distortion, and increasing system stability.

Abstract: An automatic frequency correction phase-locked loop (PLL) circuit includes an analog control circuit and a digital control circuit. The digital control circuit includes a High-side comparator and a Low-side comparator which receive an analog control voltage, a state monitor circuit, and a counter and decoder circuit. At least one of the High-side comparator and the Low-side comparator includes a threshold switching circuit which selectively provides a first threshold voltage and a second threshold voltage, the first and second threshold voltages having different magnitudes. When the analog control voltage remains stable between the High-side threshold voltage and the Low-side threshold voltage and the threshold switching circuit is providing the first threshold voltage, the state monitor circuit switches the threshold switching circuit from the first threshold voltage to the second threshold voltage, thereby expanding the interval between the High-side threshold voltage and the Low-side threshold voltage.

Abstract: CMOS LC tank circuits and flux linkage between inductors can be used to distribute and propagate clock signals over the surface of a VLSI chip or processor. The tank circuit offers an adiabatic behavior that recycles the energy between the reactive elements and minimizes losses in a conventional sense. Flux linkage can be used to orchestrate a number of seemingly individual and distributed CMOS LC tank circuits to behave as one unit. In one example, the distribution of a 45° separated multi-phase balanced oscillations over the surface of die 1.6 cm×1.6 cm at 10 GHz is expected to dissipate under 10 W and offers a potential to significantly reduce the road map predictions of 100 W. Simulations of several CMOS tank circuits indicate that the power dissipation can be reduced an order of magnitude when compared to conventional techniques. A passive flux linkage, mechanical, and finite state machine technique of frequency adjustment of an oscillator are described.

Abstract: CMOS LC tank circuits and flux linkage between inductors can be used to distribute and propagate clock signals over the surface of a VLSI chip or ?processor. The tank circuit offers an adiabatic behavior that recycles the energy between the reactive elements and minimizes losses in a conventional sense. Flux linkage can be used to orchestrate a number of seemingly individual and distributed CMOS LC tank circuits to behave as one unit. Several frequency-adjusting techniques are presented which can be used in an distributed clock network environment which includes an array of oscillators. A passive flux linkage, mechanical, and finite state machine technique of frequency adjustment of oscillators are described.

Abstract: An oscillator for synchronizing and controlling a multi-phase, interleaved power supply system that has a plurality of power sources. The oscillator includes a first oscillator, having a pulse generator and a timing capacitor, and a second oscillator, having a pulse generator and timing capacitor, that are electrically coupled to one or more first power supplies and one or more second power supplies, respectively. The pulse generator of the first oscillator is electrically coupled to the second timing capacitor and the pulse generator of the second oscillator is electrically coupled to the first timing capacitor. Each of the pulse generators is structured and arranged to provide a synchronizing pulse to the other oscillator's timing capacitor when the voltage on its own timing capacitor is midway between a pre-determined maximum voltage threshold and a pre-determined minimum voltage threshold.

Abstract: The present invention relates to radar imaging and to phased array antennas. The invention also relates to transmitter/receiver modules, push-push oscillators and Injection locked push-push oscillators for phased array antennas. The invention reduces the production cost and improves the performance of conventional phased array antennas.

Abstract: The present invention discloses a low power consumption frequency divider circuit. It mainly comprises a signal source; a signal injection circuit; and an oscillator circuit. The low-power consumption frequency divider circuit according to the present invention mainly uses the configuration of current reused circuit to form the common current path for reducing the power loss in the disclosed frequency divider circuit.