Abstract: A power supply phase doubling system includes a pulse width modulation (PWM) controller and first and second phase doubling chips. The PWM controller outputs a PWM signal. The first phase doubling chip is operated at a power supply voltage and has a first PWM output pin to generate a first control signal and a second control signal according to the PWM signal, and generates a first output signal according to the first control signal. The second phase doubling chip is operated at the power supply voltage, has a second PWM output pin, and is configured to generate a second output signal according to the second control signal. The first and second phase doubling chips are respectively switched between a master mode and a slave mode according to a voltage level of the first PWM output pin and a voltage level of the second PWM output pin.

Abstract: A frequency tripler circuit includes an amplifier to receive a balanced input signal at an input frequency and outputs a balanced signal at a second harmonic of the input frequency. The frequency tripler circuit includes a passive double balanced mixer coupled to an output of the amplifier to receive the balanced signal at the second harmonic and the balanced input signal to generate an output balanced signal having a frequency triple the input frequency.

Abstract: A circuit portion comprises a load circuit portion and a bias circuit portion. The load circuit portion comprises a load transistor. The bias circuit portion comprises a replica transistor matched to the load transistor and connected to the load transistor at a node such that when a current flows through the replica transistor, a current proportional to the current through the replica transistor flows through the load transistor. The bias circuit portion also comprises a current input for receiving an input current, a supply voltage input for receiving a supply voltage, and a feedback loop arranged to: adjust a voltage at the node connecting the replica transistor and the load transistor such that the replica transistor conducts a current proportional to the input current, and counteract variations in the voltage at the node connecting the replica transistor and the load transistor arising from changes in the supply voltage.

Abstract: An isolated switch-mode power supply includes at least one input, at least one output, and a power circuit coupled between the at least one input and the at least one output for converting an input voltage or current to an output voltage or current. The power circuit includes a transformer having one or more primary windings, one or more secondary windings, an electrical insulator, and a core magnetically coupling the one or more primary windings and the one or more secondary windings. Upper portions of the primary and secondary windings are covered with the electrical insulator. Other example switchmode power supplies, transformers, magnetic chokes and methods are also disclosed.

Abstract: A power control unit is provided to control the efficiency of a charge pump converter having a first input terminal and a second input terminal, a primary attenuator and a secondary attenuator between a first input terminal and the second input terminal, a first output terminal, a second output terminal, a secondary attenuator controlling terminal and a primary attenuator controlling terminal to be plugged to the power control unit. The primary attenuator controlling terminal and the secondary attenuator controlling terminal are to attenuate or amplify a signal of the first input terminal and the second input terminal.

Abstract: Provided is a gate controller having a primary signal input which is AC coupled to the gate through a capacitor, one or more bias inputs each connected to the gate through a resistor such as to control the DC voltage bias of the gate and therefore the conductivity of the switching element. The bias inputs can be properly connected to internal nodes of the charge pump, or charge pump stages, such that the gate controller is self-biased, without using bias-reference external to the charge pump. The gate controller can be made programmable by using potentiometers in place of the bias resistors. The programmable gate controller stages can be connected to form a programmable gate controlled charge pump.

Abstract: The present invention is directed to electrical circuits. More specifically, an embodiment of the present invention provides a variable impedance module with a first capacitor coupled to a first input terminal and the second capacitor coupled to a second input terminal. A diode bridge is connected between the input capacitors. The anodes of the top diodes are connected to a supply through a resistor, and the cathodes of the lower diodes are connected to a high-impedance current source. A third capacitor is connected between these two nodes.

Abstract: A phase-locked loop (PLL) includes a phase-frequency detector that compares a reference signal to a feedback signal. The difference in phase between the reference signal and the feedback signal is encoded as digital pulses on one or more outputs of the phase-frequency detector. The digital output pulses from the phase-frequency detector are duplicated and delayed multiple times in a non-overlapping manner before being input to the loop filter or voltage controlled oscillator (VCO) of the PLL.

Abstract: Embodiments of this application disclose an RC oscillator that amplifies a difference between a first voltage and a second voltage by using a first amplifier and a second amplifier. The first amplifier may include a first amplification circuit and a second amplification circuit. The first amplification circuit and the second amplification circuit may share a same voltage-current conversion circuit. The RC oscillator disclosed in the embodiments of this application not only avoids noise introduced by the first amplifier, but also reduces internal noise of the RC oscillator and a jitter of a clock signal.

Abstract: A first three state driver injects a first clock signal into a crystal through an input node during a startup phase of a crystal oscillator and a second three state driver injects a second signal into the crystal through an output node during the startup phase. The first and second signals are anti-phase signals. The crystal oscillator circuit includes a first amplifier that is used during starting up and steady-state operation and includes a second amplifier. The injection through the input and output nodes is disabled after a fixed time. After injection ends, the second amplifier is turned on if voltage on the output node has reached a desired voltage and left off otherwise. If the second amplifier is turned on, the second amplifier is turned off when the voltage on the output node reaches the desired voltage.

Abstract: A frequency synthesizer on an integrated circuit provides a local oscillator (LO) signal for RF operations and also functions as an injection clock signal source during crystal oscillator startup. The integrated circuit goes into a sleep mode in which the crystal oscillator is off and responsive to a wakeup event the crystal oscillator starts up again using the injection clock signal sourced from the frequency synthesizer. Parameters that cause the injection clock signal to match the crystal oscillator frequency are stored. The frequency synthesizer includes a phase-locked loop having an LC oscillator. A digital to analog converter controls the LC oscillator during injection. During an initial power up of the integrated circuit, a PLL in the frequency synthesizer locks to the crystal oscillator frequency to determine the parameters to store for injection.

Abstract: Embodiments of the invention are directed to a current sensor that includes a current controlled oscillator circuit configured to receive an input current and to provide an output signal having an output frequency which is dependent on the input current. The current sensor further includes a feedforward circuit configured to adapt a reference voltage of the current controlled oscillator in dependence on an instantaneous current value of the input current.

Abstract: A clock data recovery circuit includes a phase-locked loop circuit generating a multi-phase clock signal based on input data, the phase-locked loop circuit including a multi-rate phase detector being operable at an initial rate among a plurality of rates in an initial period; a lock detector generating a lock-enable signal by detecting a lock state of the phase-locked loop circuit; a dead zone calibration circuit determining an operational rate corresponding to a data rate of the input data among the plurality of rates in response to the lock-enable signal; and a digital block controlling the multi-rate phase detector to operate at the operational rate, and generating a calibration-enable signal. The dead zone calibration circuit determines whether the multi-phase clock signal is locked within a dead zone in response to the calibration-enable signal, and changes a phase of the multi-phase clock signal based on the multi-phase clock signal.

Abstract: A method and circuit for linearizing a frequency response of an oscillator controlled by a plurality of capacitor banks are disclosed. In the disclosed method, for each capacitor bank of at least two capacitor banks of the oscillator, a respective sensitivity characteristic of the capacitor bank is determined. Further, a set of reference output frequency control words (FCWs) for an associated set of frequencies of the oscillator are determined. When an input FCW is received and an output FCW is responsively provided based on (i) an interpolation between two reference output FCWs of the set of reference output FCWs and (ii) the respective sensitivity characteristics of the at least two capacitor banks of the oscillator. The output FCW is then applied to the at least two capacitor banks of the oscillator.

Abstract: Certain aspects of the present disclosure generally relate to a low-power relaxation oscillator. Certain aspects provide a circuit for generating an oscillating signal. The circuit generally includes a comparator, a first current source coupled to a reference potential node, a first resistive element coupled between the first current source and a voltage rail, a node between the first current source and the first resistive element being selectively coupled to a first input terminal of the comparator, a second current source coupled between a second input terminal of the comparator and the voltage rail, and a first capacitive element selectively coupled between the second input terminal of the comparator and the reference potential node.

Abstract: An FLL (frequency locked loop) oscillator/clock generator includes a free-running oscillator (such as a ring oscillator), and generates an FLL_clk with an FLL-controlled frequency fOSC. The FLL control loop includes a switched capacitor resistor divider that converts fOSC to a resistance, generating an FLL feedback voltage Vfosc used to generate a loop control signal OSC_cntrl input to the oscillator. In response, the oscillator frequency locks FLL_clk to fosc. In an example implementation, the FLL oscillator/clock operates with spread spectrum clocking (SSC) that provides triangular SSC modulation based on a truncated RC transition voltage generated as a negative feedback to an RC relaxation oscillator, with truncation based on switched tripping threshold voltages generated a positive feedback to the RC relaxation oscillator.

Abstract: An apparatus for generating an oscillating output signal includes an inductive-capacitive (LC) circuit and a current tuning circuit. The LC circuit includes a primary inductor and a varactor coupled to the primary inductor. A capacitance of the varactor is responsive to a voltage at a control input of the varactor. The current tuning circuit includes a secondary inductor and a current driving circuit coupled to the secondary inductor. The current driving circuit is responsive to a current at a control input of the current driving circuit. An effective inductance of the primary inductor is adjustable via magnetic coupling to the secondary inductor, and a frequency of the oscillating output signal is responsive to the effective inductance of the primary inductor and to the capacitance of the varactor.

Abstract: A detection circuit is provided. A detection signal corresponding to an equivalent capacitance value of a micro-electro-mechanical system is generated by an oscillator, and the equivalent capacitance value of the micro-electro-mechanical system varies with a location of the micro-electro-mechanical system.

Abstract: Aspects disclosed herein relate to predicting one or more signal characteristics to improve efficiency for a PA. A wireless communications device may be include a power amplifier and a processor that is associated with a signal prediction module. In an aspect, the processor may be a modem, a RF chip, etc. In one example, the wireless communications device may be configured to buffer one or more values associated with an input signal. The signal prediction module may be configured to predict a system response to at least a portion of the one or more buffered values, and generate a switcher control signal based on the system response. The signal prediction module may also generate a predicted supply voltage from the values associated with the input signal.

Abstract: A phase-locked loop circuit using a multi-curve voltage-controlled oscillator (VCO) having a set of operating curves, each operating curve corresponding to a different frequency range over a control voltage range. The phase-locked loop circuit includes a phase and frequency detector driving a charge pump and a digital control circuit configured to perform a closed loop curve search operation to select one of the operating curves in the multi-curve VCO and to perform a curve tracking operation using the selected operating curve, the selected operating curve being used by the VCO to generate an output signal with an output frequency being equal or close to a target frequency of the phase-locked loop. In one embodiment, the digital control circuit increases the charge pump current above a nominal current value during the closed loop curve search operation and set the charge pump current to the nominal current during the curve tracking operation.

Abstract: A voltage controlled oscillator (VCO) includes a sensing circuit, where the sensing circuit is configured to generate a plurality of compensation control signals. The VCO further includes a voltage-to-current converter comprising a plurality of current sources which are configured to generate a current signal in response to the plurality of compensation control signals. Additionally, the VCO includes a plurality of switching circuits, each of the plurality of switching circuits being configured to selectively enable or disable a corresponding one of the plurality of current sources in response to a corresponding one of the plurality of compensation control signals. Furthermore, the VCO includes a current controlled oscillator configured to generate an oscillating signal in response to the current signal.

Abstract: An injection locked frequency divider includes a ring oscillator, an input terminal, an output terminal and a control voltage terminal. The ring oscillator has a three-stage cascade connection of a first amplification circuit including an N-channel MOS type transistor and P-channel MOS type transistors, a second amplification circuit configured in the same manner as the first amplification circuit and a third amplification circuit configured likewise. A high frequency signal is input to a gate terminal of each P-channel MOS type transistor. A predetermined DC control voltage is supplied to a gate terminal of each P-channel MOS type transistor.

Abstract: It is an object of the present invention to provide a phase locked loop in which a voltage signal input to a voltage controlled oscillator after a return from a stand-by state becomes constant in a short time and power consumption is reduced. A transistor including a semiconductor layer formed using an oxide semiconductor material is provided between an input terminal of a voltage controlled oscillator and a capacitor of a loop filter. The transistor is turned on in a normal operation state and turned off in a stand-by state.

Abstract: An ADPLL includes a digital controlled oscillator, a first counter counting a number of clocks from the digital controlled oscillator, a second counter to count a multiplication number representing a number of the clocks in a reference clock, a TDC detecting a delayed amount of a phase of the clocks against a phase of the reference clock, an adder adding the delayed amount to a difference between the multiplication number and the number of clocks, a slew rate setting part setting a slew rate of the clocks, an ADC receiving the clocks to which the slew rate is set, a switching part switching between an output of the adder and an output of the ADC, and a controller controlling the slew rate by shifting a phase of the clocks to set a slew rate while the ADLL is locked by utilizing the TDC.

Abstract: The inventive concept relates to a supply regulated voltage controlled oscillator having a function of an active loop filter by sharing one operational amplifier without additional use of active elements in a supply regulated voltage controlled oscillator using an operational amplifier as a supply regulator, and a phase locked loop using the same.

Abstract: A novel and useful millimeter-wave digitally controlled oscillator (DCO) that achieve a tuning range greater than 10% and fine frequency resolution less than 1 MHz. Switched metal capacitors are distributed across a passive resonator for tuning the oscillation frequency. To obtain sub-MHz frequency resolution, tuning step attenuation techniques are used that exploit an inductor and a transformer. A 60-GHz fine-resolution inductor-based DCO (L-DCO) and a 60 GHz transformer-coupled DCO (T-DCO), both fabricated in 90 nm CMOS, are disclosed. The phase noise of both DCOs is lower than ?90.5 dBc/Hz at 1 MHz offset across 56 to 62 GHz frequency range. The T-DCO achieves a fine frequency tuning step of 2.5 MHz, whereas the L-DCO tuning step is over one order of magnitude finer at 160 kHz.

Abstract: An oscillator arrangement comprises a current controlled oscillator, a frequency to voltage converter, and an operational amplifier. The current controlled oscillator is adapted to generate a clock signal based on a control voltage signal, wherein the generated clock signal is supplied to the frequency to voltage converter. The frequency to voltage converter is adapted to generate an output voltage signal based on the generated clock signal and based on a supply voltage signal.

Abstract: The disclosed embodiments provide a resonant oscillator circuit. The resonant oscillator circuit includes a clipping mechanism configured to clip an output voltage of a signal pulse generated by the resonant oscillator circuit to a predefined constant level. The resonant oscillator circuit also includes a feedback path configured to return energy from the clipping mechanism to an input of the resonant oscillator circuit.

Abstract: Oscillators are described that have a highly stable output frequency versus the variation of supply voltage and different operating conditions such as temperature. The concepts are broadly applicable to various types of oscillators. The highly stable output is achieved with the use of self biasing loops. The circuits associated with providing constant harmonic output current can be used with the concept of a phi-null oscillator to further stabilize the output frequency.

Abstract: In one embodiment, a voltage-controlled oscillator (VCO) is provided that includes: a plurality of differential inverters coupled to form a loop, each differential inverter having a differential pair of transistors configured to steer a tail current from a current source, the current source sourcing the tail current responsive to a bias voltage, wherein each transistor in the differential pair couples to a power source through a corresponding switching-capacitor circuit; and a bias circuit configured to generate the bias voltage such that a transconductance for each transistor in the differential pairs is proportional to a factor that is a function of a ratio of transistor widths within the bias circuit.

Abstract: An oscillator circuit includes an amplifier including at least two terminals for receiving a crystal and an automatic amplitude control loop coupled to the amplifier including biasing circuitry switched between a first operational mode and a second operational mode. The first operational mode occurs during an initial time period and the second operational mode occurs after the initial time period is expired. The biasing circuitry includes first and second PMOS transistor circuits, each transistor circuit including an unswitched PMOS transistor and a switched PMOS transistor. Alternatively, the biasing circuitry can include first and second NMOS transistor circuits, each transistor circuit including an unswitched NMOS transistor and a switched NMOS transistor. The biasing circuitry is under control of an internally generated control signal.

Abstract: A circuit includes a first path including a first transistor and a first current source. The first transistor is responsive to a tuning voltage. The circuit also includes a tuning voltage range extension circuit responsive to the tuning voltage. The tuning voltage range extension circuit is configured to selectively change current supplied by the first path as the tuning voltage exceeds a capacity threshold of the first transistor.

Abstract: An adjustable-frequency oscillator, is formed by two looped systems, functioning at the same frequency but the signals are phase shifted by 90°. Each looped system includes a phase shift device, an active element providing the gain and a resonator having a fixed phase-frequency characteristic. As the phase shift in each loop is imperatively a whole multiple of 2?, the phase shift added in each loop by the phase shift device entails that each resonator introduces a complementary phase shift to comply with the oscillation criterion. This complementary phase shift is produced at a frequency defined by the resonator, this then defining the frequency of oscillation. The frequency is adjusted by two phase shift stages, which carry out the analogue multiplication of the signals coming from the two looped systems by control voltages and the summing of these products.

Abstract: A thermally-compensated oscillator has a current reference with an output current which relates to an ambient temperature with a first relationship, a ring oscillator having an operating frequency which relates to the ambient temperature with a second relationship, and which receives the output current of the current reference and outputs an oscillator signal, and a level shifter which receives the oscillator signal from the ring oscillator and outputs a corresponding voltage-regulated clock signal.

Abstract: An oscillator may include a crystal resonator, an inverter coupled in parallel with the crystal resonator, a first switched capacitor coupled to a first terminal of the crystal resonator, a second switched capacitor coupled to a second terminal of the crystal resonator, a control module configured to output a periodic dithering signal, the periodic dithering signal having a first pulse width based on a desired frequency of oscillation for the oscillator, and a delay module configured to communicate a first periodic enable signal to enable the first switched capacitor and a second periodic enable signal to enable the second switched capacitor. At least one of the first periodic enable signal and the second periodic enable signal may have a second pulse width greater than the first pulse width. The second periodic enable signal may be phase delayed relative to the first periodic enable signal by a non-zero delay.

Abstract: A resonance part of a voltage controlled oscillator (VCO) includes variable capacitance elements where an electrostatic capacitance changes in order to adjust a resonance frequency and an inductance element, and a transistor of grounded emitter type amplifies a frequency signal inputted from the resonance part to a base terminal. A feedback part includes capacitance elements for feedback, and feedbacks a frequency signal outputted from an emitter terminal of the transistor to the transistor via the base terminal. Besides, base bleeder resistances for adjusting a bias voltage to be applied to the base terminal and the transistor are formed in a common integrated circuit, and an emitter resistance is provided outside the integrated circuit as a resistance element being a different body in order to adjust an operating point of the transistor.

Abstract: The subject innovation relates to systems and/or methodologies for generating a low jitter large frequency tuning LC-based phase-locked loop circuit for multi-speed clocking applications. In addition to a plurality of noise reduction features, the phase-locked loop includes programmable charge pump and loop filter that enable a wide loop bandwidth, a programmable VCO that enables a wide VCO frequency range and a per lane clock divider that further enables a wide PLL frequency range. Furthermore, an auto-calibration circuit ensures that the VCO included in the PLL receives the optimum current for noise reduction across the VCO frequency range.

Abstract: A voltage-controlled oscillator includes a voltage regulator, and a delay unit. The voltage regulator independently receives a first oscillation control signal and a second oscillation control signal to provide a regulated voltage signal which is represented by a regular ratio of combination of the first and second oscillation control signals, and the regulated voltage signal is feedback to the voltage regulator. The delay unit generates an output signal having a frequency varying in response to the regulated voltage signal.

Abstract: In a crystal-oscillator circuit having a quartz crystal unit, further stabilization of output frequency change at a time of startup of the power supply is achieved. A crystal-oscillator circuit having a quartz crystal unit includes a first variable-capacitance element, which forms an oscillation loop with the quartz crystal unit, and a temperature compensation circuit which provides a first control signal for the first variable-capacitance element to compensate for a temperature characteristic of the quartz crystal unit. In addition, the crystal-oscillator circuit includes a second variable-capacitance element group, and a time constant circuit which provides a time constant signal, which changes with a predetermined time constant, for the second variable-capacitance element group as a second control signal.

Abstract: A phase locked loop circuit includes an oscillator part configured to generate a reference signal by amplifying a signal generated by an oscillator, and a phase locked loop part configured to include a filter that outputs a control signal to a clock transmitting circuit that generates a clock signal in accordance with a phase difference between the reference signal and a feedback signal, wherein a drive capability of the oscillator part is controlled in accordance with the control signal.

Abstract: A voltage-controlled oscillator operates at high frequency without high gain by dividing the frequency range into a plurality of subranges, which preferably are substantially equal in size. Within any subrange, the full extent of variation in the control signal changes the frequency only by the extent of the subrange. The gain is thus substantially equal to the gain one would expect for the full frequency range, divided by the number of subranges. The subrange may be selected manually, or by an initial calibration process. In one embodiment, the oscillator includes a voltage-to-current converter and a current-controlled oscillator, with a current mirror arrangement. In that embodiment, selection of the subrange may be controlled by turning on the correct number of current legs.

Abstract: This disclosure relates to a Phase-Locked Loop (PLL) device and a method for providing a stable free-running voltage signal to a voltage controlled oscillator.

Abstract: In a voltage-controlled oscillator capable of broadening a variable frequency range while suppressing increase of conversion gain, a converter (12) converts an input voltage to a first physical quantity, a variable converter (13) supplies a second physical quantity that accords with the status of each switch of a switch group (13a). another variable converter (14), when the input voltage is contained within a prescribed voltage range, supplies a third physical quantity that accords with the input voltage and the status of each switch of another switch group (14a), and a variable-frequency oscillator (15) supplies a signal of a frequency that accords with the first physical quantity, the second physical quantity, and the third physical quantity.

Abstract: Provided is a low voltage frequency synthesizer using a boosting method for a power supply voltage of a charge pump. The low voltage frequency synthesizer includes a phase/frequency detector (PFD) that receives and compares a reference frequency and a feedback frequency to output a comparison signal, a charge pump that receives the comparison signal to output a current corresponding to the comparison signal, a low-pass filter (LPF) that generates a voltage corresponding to the output current of the charge pump, a voltage controlled oscillator (VCO) that receives the voltage of the LPF, amplifies the voltage to generate a boosting voltage, and outputs a frequency corresponding to the received voltage, and a DC converter that receives the boosting voltage of the VCO, converts the boosting voltage into a DC voltage, and applies the DC voltage as a power supply voltage of the charge pump.

Abstract: A variance correction method includes generating a reference current depending on a resistance within a lowpass filter and outputting the reference current to a voltage controlled oscillator, and correcting characteristics of the lowpass filter and a gain of the voltage controlled oscillator based on an output clock of the voltage controlled oscillator.

Abstract: In a circuit having a runaway detector coupled to a phase-locked loop (PLL), the PLL may include a loop filter to receive a control voltage within the PLL and provide a filtered control voltage and a voltage-controlled oscillator to receive the filtered control voltage and provide an output clock signal. The runaway detector may provide a control signal for adjusting the filtered control voltage in response to a predetermined PLL condition. The runaway detector may include a comparator to receive a first and second input voltages, where the second input voltage is based on the output clock signal. When the predetermined PLL condition exists, the runaway detector may be active to adjust the filtered control voltage, thereby enabling the PLL to return to a lock condition.

Abstract: A frequency phase locked loop (FPLL) includes a first feedback loop coupled to a second feedback loop. The first feedback loop is configured to correct a phase offset of an output signal of the FPLL. The second feedback loop is configured to correct a frequency offset of the output signal of the FPLL.

Abstract: A mixed-mode PLL is disclosed. The mixed-mode PLL comprises an analog phase correction path and a digital frequency correction path. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit.

Abstract: A phase locked loop with a current leakage adjustment function is provided. The phase locked loop includes a phase locked loop unit having a compensation voltage node, a digitalized leakage-detection circuit generating a plurality of digital control signals based upon the phase error between a reference clock signal and a feedback signal, and a compensation circuit generating a compensation current based upon the plurality of digital control signals. When there exist current leakages of the MOS capacitors, the current leakage adjustment circuits provided by the present invention may prevent the conventional phase locked loop from un-locking due to jittering.

Abstract: A voltage controlled oscillator-phase lock loop (VCO-PLL) system includes a voltage controlled oscillator (VCO) system implementing four-channel architecture, such that two bands support two channels; a phase-locked-loop (PLL) system; and a mixer system. The VCO system further includes a control circuit; a first cross-coupled oscillator system adapted to receive a source voltage; a second cross-coupled oscillator system adapted to receive the source voltage; and a plurality of isolation buffer systems adapted to protect the first and second cross-coupled oscillator systems.