Abstract: A charge pump has two charge pump nodes. The first charge pump node has a first current source (CS) with a source terminal connected to a positive supply voltage and an output terminal connected to the first charge pump node with a P channel metal oxide silicon transistor (PFET) controlled by a first control signal. The first charge pump node is also connected to a second CS with a source terminal connected to the ground supply voltage and an output terminal connected to the second CS with an NFET controlled by a second control signal. The second charge pump node has a third CS with a source terminal connected to the positive supply voltage and an output terminal connected to the second charge pump node with a PFET controlled by a third control signal. The second charge pump node is also connected to a fourth CS with a source terminal connected to the ground supply voltage and an output terminal connected to the second CS with an NFET controlled by a fourth control signal.

Abstract: An efficient current feedback buffer is revealed. The buffer is useful in power supplies for a number of analog and digital devices, including CMOS voltage controlled ring oscillators, frequency synthesizers, delay locked loops, phase accumulators, and phase locked loops. The power supply and buffer maintains a low impedance output to the load, regulates the voltage output of the supply, and rejects power line noise.

Abstract: A phase-locked loop (PLL) includes a voltage controlled oscillator (VCO) and a pair of charge pump circuits (CP) and provides a stable oscillation clock signal. A phase comparator compares a reference clock signal with an oscillation clock signal generated by the VCO and generates two comparison signals. The comparison signals are input to the first CP, which generates a first CP output signal. The first CP output signal is filtered with a first low pass filter (LPF) and the filtered signal (control voltage) is provided to the VCO, which produces the oscillation clock. The second CP receives two clock signals and generates a second CP output signal. The second CP output signal is filtered with a second LPF and the filtered signal is converted to a digital signal with an A/D converter. The digital signal is applied to a bias circuit, which then produces first and second control voltages.

Abstract: A local oscillator calibrator comprises a main charge pump that drives a voltage controlled oscillator (VCO) through a loop filter. A second, replica charge pump can also drive the VCO, but is setup to output only its most positive or most negative analog output control voltage. Since the construction and characteristics of the replica charge pump duplicate the main charge pump, the main charge pump's minimum and maximum analog control outputs can be cloned out to the VCO on demand. A VCO calibration procedure therefore includes switching the VCO to each of its ranges set by a bank of fixed capacitors, and using the replica charge pump to drive the VCO to its minimum and maximum frequency for each range setting. The min-max frequency data is stored in a lookup table, and operational requests to switch to a new channel frequency can be supported with a priori information about which fixed-capacitor range selection will be best.

Abstract: A tuning circuit includes an oscillator that receives an oscillating input signal and a control signal, and generates an oscillating output signal. The control signal is obtained from a frequency control circuit that compares the phases of the oscillating output signal and a reference signal. The control signal controls the transconductance of a transconductance element in the oscillator, thereby controlling the oscillator output frequency. The oscillating input signal is obtained from an amplitude control circuit that detects an amplitude limit of the oscillator output. The oscillator output amplitude is responsive to the oscillating input signal. Frequency control and amplitude control in this tuning circuit are mutually independent, so their respective control loops remain stable under all frequency and amplitude combinations.

Abstract: System and method for providing low noise signal having a broad tuning range (1 GHz to 10 GHz, or larger), with associated jitter no more than about 10 percent of the selected period of a target output signal. In a first stage, a ring-based VCO phase locked loop system provides a broad tuning range with some associated noise, and a second stage in a first state is relatively transparent, with no substantial differential attenuation based on frequency. After phase lock is achieved, the second stage is switched to a second state with low associated noise and high differential attenuation based on input signal frequency.

Abstract: Apparatus for generating an oscillating signal in a desired phase relationship with an input signal, including a mixer arranged to receive a pair of reference signals oscillating at a common frequency and having a phase offset between them, and to mix the reference signals in variable proportions according to the value of input weighting signals to generate an output signal. A comparator is to compare the phase of the output signal with that of the input signal to determine whether the signals are in the desired phase relationship and, if not, to output one or more control signals indicative of the required adjustment in the phase of the output signal to achieve the desired phase relationship. An adjustable ring oscillator including a plurality of stages is connected in a ring and arranged to propagate oscillations around the ring.

Abstract: A voltage controlled oscillator of a phase locked loop circuit having digitally controlled gain compensation. The digital control circuitry provides binary logic input to the voltage controlled oscillator for a digitally controlled variable resistance circuit, a digitally controlled variable current transconductor circuit, or differential transistor pairs having mirrored circuitry for adjusting the V-I gain.

Abstract: Object of the present invention is to provide a semiconductor integrated circuit and a voltage control oscillator capable of performing stable oscillating operation and generating an oscillating signal with little jitter. The present invention has a VCO cell, a replica cell constituted in the same way as the VCO cell, an operational amplifier, and a current generator bias circuit. A NMOS transistor is connected between a node in the VCO cell and a ground terminal. The operational amplifier controls the voltages of a node in the replica cell and the node in the VCO so that they are equal to the reference voltage. Because of this, the PMOS transistor composing of a current generator always operates at pentode region, thereby stabilizing the oscillating operation. Furthermore, according to the present embodiment, a CC jitter at low frequency side can be reduced more efficiently than that of the conventional circuit.

Abstract: A regulator circuit for providing a regulated voltage, comprises a driver for generating a drive signal, and a charge pump having a first voltage input coupled to a first voltage source, being responsive to the drive signal, to generate a pump voltage from the first voltage source. An amplifier having a reference input is coupled to a reference voltage, a sense input is coupled to a sense signal representative of the pump voltage, and an output is operable in response to a difference between the reference voltage and the sense signal, to control the driver. A switch is coupled from the amplifier output to an output of the charge pump such that the pump voltage is controllably boosted by the amplifier output through the switch.

Abstract: A phase-locked loop (PLL) having a wide range of oscillator output frequencies and a wide range of loop divider values is realizable in integrated form because the total capacitance of its loop filter is small. The PLL includes a first phase detector, a second phase detector, a programmable tapped-delay-line oscillator, a divide-by-M loop divider, and a programmable on-chip loop filter. The programmable filter is programmed to realize one of many loop filters. In a first step, oscillator output is fed back via the loop divider to the first phase detector. Oscillator frequency is decremented by changing tap selection inside the oscillator until the first phase detector determines that the frequency of the signal fed back via the loop divider (divide-by-M) is smaller than the frequency of an input signal. The tap control at which this frequency lock condition occurred, along with value M, is then used to determine which of the many loop filters will be used in a phase lock step.

Abstract: A high speed data communication system includes a receiver to recover data and clock signals from communicated data. The receiver circuit has a dual phase lock loop (PLL) circuit. A fine loop of the PLL includes a phase detector providing a differential analog voltage output. Transconductance circuitry converts the differential analog voltage output to a low current analog output. The transconductance circuitry has a variable gain which is controlled by an automatic gain adjust circuit. A coarse loop of the PLL allows for fast frequency acquisition of an internal oscillator.

Abstract: A low phase noise CMOS voltage controlled oscillator (VCO) circuit. The VCO circuit includes a bias circuit and a VCO cell coupled to the bias circuit. The VCO cell includes a VCO output for transmitting a VCO output signal. A frequency to voltage converter is coupled to receive the VCO output signal. The frequency to voltage converter converts a frequency of the VCO output signal into a corresponding voltage output. The voltage output is coupled to control the bias circuit. The VCO cell includes a current source coupled to the bias circuit such that the voltage output from the voltage a current converter provides negative feedback to the VCO cell via the current source. The negative feedback, in turn, reduces the phase noise on the VCO output signal.

Abstract: A phase locked loop (PLL) is use in a radio communication system such as a frequency mixer, a carrier frequency and the like. The phase locked loop (PLL) includes a phase/frequency detector for comparing a phase/frequency of a reference signal and a feedback signal. The phase/frequency detector includes: a NAND gate logic circuit for NANDing a first signal and a second signal to output a NANDed signal; a first latch unit for latching the NANDed signal and outputting the first signal in response to a reference frequency; and a second latch unit for latching the NANDed signal and outputting the second signal in response to a feedback frequency. The phase locked loop (PLL) further includes a filter controller for changing a bandwidth of a low pass filter in response to an output signal of the phase/frequency detector.

Abstract: In a frequency synthesizer device in which a frequency-division ratio control circuit 6 and other circuits are integrated on the same semiconductor substrate, a power supply 8 for supplying a power to the frequency-division ratio control circuit 6 is provided separately from a power supply 7 for supplying a power to other circuits. A power supply voltage supplied from the power supply 8 to the frequency-division ratio control circuit 6 is set lower than a power supply voltage supplied to other circuits. The noise generated by the frequency-division ratio control circuit 6 can be reduced by setting the power supply voltage lower, and also C/N degradation can be reduced. Since the noises can be suppressed even if the frequency is increased, a lock-up time can be reduced and the lower power consumption can be attained.

Abstract: A phase locked loop (PLL) is used in a radio communication system such as a frequency mixer, a carrier frequency and the like. The phase locked loop (PLL) includes a phase/frequency detector for comparing a phase/frequency of a reference signal and a feedback signal. The phase/frequency detector includes: a NAND gate logic circuit for NANDing a first signal and a second signal to output a NANDed signal; a first latch unit for latching the NANDed signal and outputting the first signal in response to a reference frequency; and a second latch unit for latching the NANDed signal and outputting the second signal in response to a feedback frequency. The phase locked loop (PLL) further includes a filter controller for changing a bandwidth of a low pass filter in response to an output signal of the phase/frequency detector.

Abstract: A self-biased phase-locked loop circuit includes a phase detector, first and second charge pumps, first and second loop filters, and a voltage-controlled oscillator (VCO). The phase detector is configured to measure a phase offset between two input signals, and to generate pulses corresponding to the phase offset. The first and second charge pumps are configured to provide charge corresponding to the pulses. The first and second loop filters are coupled to outputs of the first and second charge pumps, respectively. The filters operate to provide a control signal responsive to the charge. The VCO is configured to adjust its output frequency in response to the control signal. The second loop filter capacitor considerably improves the output clock jitter.

Abstract: A generator (50) able to be fitted to a clockwork system including a crystal (51a) used as a time base, includes a first oscillator (51) able to supply a first frequency (f1), a second oscillator (56) able to supply a second frequency (f2), a divider (60) able to supply a third frequency (f3) from the second frequency, a comparator (52) able to compare the third and first frequencies, and a control loop including a filter (54) connected to the comparator and able to control the second oscillator. The generator is characterised in that it includes a component (58) able to provide an indicator (LCK) containing the state of the loop, and in that the filter (54) can receive the indicator (LCK) and, in response, have a narrow (or respectively wide) band, when the loop is (or respectively is not) locked.

Abstract: A high precision charge pump used in a phase-lock-loop incorporating a phase/frequency detector is designed and constructed to substantially eliminate the effects of DC offset and glitch errors on the charge pump output current. The high precision charge pump is constructed of parallel current paths each having a central node which is, in turn, connected to a feedback element. The feedback element defines a feedback current which is applied to the charge pump so as to maintain the two central nodes at an equi-potential level and to maintain the value of the pump-down current exactly equal to the value of the pump-up current output by the device.

Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock by using a shift register.

Abstract: A digital phase locked loop includes a digital phase detector which provides a magnitude control signal to adjust the step size of up and down adjustments in the phase/frequency of a digitally controlled oscillator, resulting in shorter lock-in or acquisition time and smaller jitter as compared to conventional digital phase locked loop devices. In the disclosed embodiments, the digital phase detector includes multiple bit shift registers in both the up and down directions to count or measure a number of up or down minimum width pulses and provide a pulse magnitude control based on the value of the shift registers to the digitally controlled oscillator. The digitally controlled oscillator includes a charge pump and voltage controlled oscillator. In one embodiment, the charge pump provides programmable control over its output current pulses to a capacitor which controls the output frequency of the voltage controlled oscillator.

Abstract: A charge pump circuit for use with a phase locked loop is described. The circuit has an input port for receiving a signal indicative of a misalignment between two clock signals. It also has an output port at which a drive signal is provided. The drive signal is provided when the comparison result is indicative of misalignment of the signals. When the signals are aligned, a high impedance is provided at the output port and the charge pump circuit or a portion thereof enter a sleep mode to reduce power consumption of the charge pump when providing a high impedance at the output port.

Abstract: A PLL is implemented as a full differential circuit to improve the jitter performance and the operating voltage range. A process-compensated common-mode feedback is designed in the differential charge pump which together with loop filter of MOSFET capacitors maximizes the dynamic voltage range. A high-frequency divider capable of divide-mode change-on-flight is developed with eight divide mode programmability. A PLL start-up control circuit makes the PLL start and work under difficult conditions.

Abstract: An integrated circuit has a phase-locked loop (PLL) frequency synthesizer circuit which has a charge pump circuit for providing an output control voltage to adjust an oscillator frequency in response to fast and slow signals provided by a phase detector. The charge pump circuit has first and second current sources, and a switching network for selectively coupling, in response to said fast signal, the first current source to one of an internal node and an output node coupled to an output capacitor and having an output voltage, and, in response to said slow signal, the second current source to one of the internal node and the output node.

Abstract: The present invention includes a charge pump that has an advantageous use in a phase-lock loop. The charge pump includes a current mirror, at least two switches and a loop. The current mirror pumps up loop filters according to input signals. The loop senses the common mode of loop filter nodes and compares them to a reference voltage. If the common mode is not at a desired level, then the loop provides leakage paths that are turned on to bring the nodes to that desired level. The use of the current mirror substantially reduces current mismatch. Furthermore, the loop is active for a relatively short time, thus minimizing the introduction of any errors. The present invention reduces static phase error by reducing current mismatch.

Abstract: PLL power up detector includes a capacitor coupled to a charging circuit. The capacitor is charged to a level responsive to the pulse width of the UP and DOWN signals produced by the PFD circuit included in the PLL circuit. When the PLL is near or at the locked state, the UP and DOWN signals will exhibit short high-going pulses or remain at ground level, allowing charger circuit increase the voltage on the capacitor. The Schmitt trigger circuit senses the voltage level on the capacitor and outputs a signal indicating the PLL is near or at the locked state. The Schmitt trigger output signal is coupled to a counter circuit to further validate the lock state of the PLL. The Schmitt trigger output signal must remain at the locked state for n-consecutive reference clock cycles before the PLL power-up signal, is asserted. When the power-up signal is asserted, the charging circuit is disabled and PLL power up detector will not consume quiescent current.

Abstract: A phase-locked loop (PLL) includes a voltage controlled oscillator (VCO) and a pair of charge pump circuits (CP) and provides a stable oscillation clock signal. A phase comparator compares a reference clock signal with an oscillation clock signal generated by the VCO and generates two comparison signals. The comparison signals are input to the first CP, which generates a first CP output signal. The first CP output signal is filtered with a first low pass filter (LPF) and the filtered signal (control voltage) is provided to the VCO, which produces the oscillation clock. The second CP receives two clock signals and generates a second CP output signal. The second CP output signal is filtered with a second LPF and the filtered signal is converted to a digital signal with an A/D converter. The digital signal is applied to a bias circuit, which then produces first and second control voltages.

Abstract: A phase-locked loop includes a phase/frequency detector, a charge pump, a loop filter, an oscillator and a feedback circuit coupled between the oscillator and the phase/frequency detector. The loop filter includes a first temperature-variable well resistor and has a gain directly related to resistance of the first resistor. An oscillator coupled to the loop filter includes a voltage-to-current converter that generates a reference current based on the loop filter voltage, and a current-controlled oscillator that generates the output clock based on the value of the reference current. The voltage-to-current converter includes a first transistor that receives the loop filter voltage at a gate and a second temperature-variable well resistor coupled to the source of the first transistor. The oscillator gain is indirectly related to the resistance of the second resistor. The second well resistor and first well resistor have substantially equal resistances and substantially equal temperature coefficients.

Abstract: A high precision charge pump used in a phase-lock-loop incorporating a phase/frequency detector is designed and constructed to substantially eliminate the effects of DC offset and glitch errors on the charge pump output current. The high precision charge pump is constructed of parallel current paths each having a central node which is, in turn, connected to a feedback element. The feedback element defines a feedback current which is applied to the charge pump so as to maintain the two central nodes at an equi-potential level and to maintain the value of the pump-down current exactly equal to the value of the pump-up current output by the device.

Abstract: A system and method for a differential charge pump with reduced charge-coupling effects for use in integrated circuits such as a phase-lock loop are disclosed. The charge pump includes a first branch, a second branch, and a charge device. The first branch includes a first current source and sink coupled to a power supply and ground, respectively, a first current steering device coupled between the first current source and sink, and a first buffer coupled to the first current steering device between a first charge node and a first damp node. The second branch includes a second current source and sink coupled to a power supply and ground, respectively, a second current steering device coupled between the second current source and sink, and a second buffer coupled to the second current steering device between a second charge node and a second damp node.

Abstract: A phase lock loop includes a charge pump, a voltage controlled oscillator (VCO), and a phase frequency detector. The phase frequency detector has a dynamic logic structure. The phase frequency detector generates up and down signals for directing the charge pump to provide a voltage signal to the VCO to vary the frequency of the VCO clock. The difference between the up and down signals is indicative of the phase difference between the reference clock signal and the VCO clock. The phase frequency detector includes up and down signal generators for generating the up and down signals, respectively. The up signal generator includes a first p field effect transistor (FET) having a gate for receiving a set signal, a second p FET having a source coupled to the drain of the first p FET and having a gate for receiving a reference clock signal. A first n FET has a source coupled to the drain of the second p FET and has a gate for receiving the set signal.

Abstract: A phase locked loop (PLL) oscillating circuit includes a first oscillating circuit, a lock detector and a reference oscillating circuit. The first oscillating circuit generates an oscillation signal with a first frequency, and controls the first frequency based on a reference signal. The lock detector detects phase lock between the oscillation signal and the reference signal to a lock detection signal. The reference oscillating circuit includes a crystal oscillation element, and generates the reference signal. An oscillation state of the reference oscillating circuit is controlled based on the lock detection signal.

Abstract: The synthesis of high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock by using a shift register.

Abstract: A programmable dividing circuit comprises a first plurality N of similar transistor stages connected in a divide-by-N sequence, wherein N is an odd integer, the transistor stages being configured so that when an output of the last stage is supplied to a first stage in the sequence, the dividing circuit operates as a divide-by-N circuit in which an output signal is generated which has one cycle for every N cycles of a clock signal applied to the transistor stages.

Abstract: The present invention is directed to apparatus and methods for reducing transient signals in phase locked loop (PLL) circuits of central processing units. One aspect of the present invention is directed to a method and apparatus that disables a charge pump circuit in a phase locked loop circuit when a frequency change in the output signal of the PLL circuit is implemented to limit transient signals generated by the PLL. Another aspect of the present invention is directed to a method and apparatus for coordinating a change in divider values for frequency dividers in a PLL of a CPU to limit transient signals from the PLL.

Abstract: A correction circuit for controlling a correction required circuit includes an oscillator circuit, and a logic circuit which counts an oscillation frequency of the oscillator circuit and thus produces a control signal which causes the oscillator circuit to oscillate at a constant frequency. The control signal changes element values of elements of the oscillator circuit and the correction required circuit so that characteristics of the oscillator circuit and the correction required circuit can be controlled.

Abstract: A phase locked loop circuit includes a reset signal generating circuit for generating a reference clock signal and a reset signal from an input clock signal. A phase locked loop section generates an output clock signal based on the reference clock signal such that a phase of the output clock signal is locked in that of the reference clock signal. Also, the phase locked loop section is reset in response to the reset signal such that the phase of the output clock signal is locked in an initial value.

Abstract: A current source circuit for providing a stable current into a filter element of a phase-lock-loop circuit of a clock generator. The current source circuit comprises a first resistor coupled to a voltage supply. The emitter of a first transistor is coupled to the first resistor; the collector is coupled to a capacitor which is part of the filter elements of the phase-lock-loop. Current flows from the voltage supply through the first resistor and first transistor into the capacitor. Leakage current flowing out of the capacitor due to the inherent Rcb impedance associated with the first transistor is directed to a path provided by a second transistor. The second transistor has an emitter coupled to the base of the first transistor and a collector coupled to the capacitor. The second transistor is biased such that the Rcb leakage current is directed back into the capacitor.

Abstract: A microprocessor includes an on-chip low phase noise CMOS LC capacitance oscillator. The LC oscillator is relatively insensitive to power supply fluctuations. In addition, the LC oscillator is operable over a range of frequencies sufficient to support both normal full power operation, and reduced power operation of the microprocessor. The LC oscillator minimizes clock jitter problems and so permits extension of the microprocessor operating frequency to even higher levels than heretofore were possible. An output signal from a phase-frequency detector is a frequency control signal on a frequency control input line of a level converter and filter circuit of the LC oscillator. The output signal from level converter and filter circuit is a filtered frequency control signal on a control voltage input line to a continuously modifiable gigahertz frequency voltage controlled oscillator (VCO) circuit.

Abstract: A PLL (phase lock loop) circuit improves pull-in and noise performances by changing a loop gain based on the loop states. The PLL circuit includes a voltage controlled oscillator (VCO) for generating an oscillation signal whose oscillation frequency is controlled by a control voltage provided thereto, a phase comparator for detecting a phase difference between the oscillation signal from the VCO and a reference signal wherein a detection gain of the phase difference is regulated by a bias voltage provided thereto, a low pass filter for receiving an output signal of the phase comparator for removing high frequency components therefrom to produce the control voltage supplied to the VCO, a phase lock loop formed by the VCO, phase comparator and low pass filter, and a phase lock detection circuit for detecting whether the phase lock loop has reached a phase lock state and changing the bias voltage to decrease the detection gain of the phase comparator when the phase lock loop has reached the lock state.

Abstract: A phase locked loop in a LSI comprises a phase comparator, a low-pass filter, a voltage controlled oscillator and a frequency divider, and receives an input clock signal to output an internal clock signal obtained by multiplication of the input clock signal. The output of the low-pass filter is supplied through a voltage follower from an external pin toward outside the integrated circuit. The output voltage of the low-pass filter is evaluated during a test mode for evaluating the function of the phase locked loop without affecting the characteristics of the phase locked loop.

Abstract: An integrated circuit (100) includes an analog phase-locked loop circuit (10) and other circuitry (102). The integrated circuit (100) has a plurality of external connection pins (104, 106), which are coupled to the other circuitry. The analog phase-locked loop circuit (10) is free of connections to the external connection pins. The analog phase-locked loop circuit (10) includes a phase detector circuit (16) which compares the phase of a reference signal (28) to the output (12) of the phase-locked loop circuit, a charge pump circuit (18) responsive to the phase detector for varying the charge on a capacitor (36) of a loop filter circuit (20), a regulator circuit (22) which receives two separate control voltages (38, 44) from the loop filter circuit, and a voltage controlled oscillator circuit (24) which receives from the regulator circuit two separate control voltages (VIN, VREG) and a regulated supply voltage (VREG).

Abstract: A low-gain, low-jitter VCO circuit implemented in CMOS provides center frequency adjustment to overcome process variations. Further, noise immunity is improved by using a separate feedback loop to provide the nominal current biasing for the oscillator chain. This feedback loop coarsely sets the center frequency. The actual control of the oscillation frequency is achieved by a second current source, whose output is added to the nominal bias current to provide a total bias to the oscillator. This second current source "fine tunes" the oscillator frequency responsive to a control signal. Because two separate current sources are used, the circuit can realize a high oscillation frequency with a low VCO gain. Another feature provides for adjusting the center frequency in response to a digital input word provided via external pins, or from internal logic or memory. The center frequency thus can be calibrated by measurement at the time of manufacture, or changes later by the end user or by other circuitry.

Abstract: An integrated circuit (100) includes an analog phase-locked loop circuit (10) and other circuitry (102). The analog phase-locked loop circuit includes a phase detector circuit (16) which compares the phase of a reference signal (28) to the output (12) of the phase-locked loop circuit, a charge pump circuit (18) responsive to the phase detector for varying the charge on a capacitor (36) of a loop filter circuit (20), a regulator circuit (22) which receives two separate control voltages (38, 44) from the loop filter circuit, and a voltage controlled oscillator circuit (24) which receives from the regulator circuit two separate control voltages (VIN, VREG), one of which also serves as a regulated supply voltage. The regulator circuit includes n-channel devices which are connected in series between a supply voltage and each control voltage output.

Abstract: A lock detector (16) includes a set circuit (64), a reset circuit (120), and a latch circuit (80). The latch circuit (80) provides an output signal (82) in response to the temporal relationship of the first input signal (12) and the second input signal (14). The set circuit (64) initiates the transition of the latch circuit (80) to the locked state, while the reset circuit (120) initiates the transition of the latch circuit (80) to the not-locked state.

Abstract: A voltage controlled current source provides controlled current to a current controlled oscillator in a high frequency phase-locked loop clock generator. The voltage controlled current source receives a first control signal and a set of second control signals indicative of a phase difference between the output signal of the clock signal generator and a reference frequency. It uses those control signals to adjust the current-controlled oscillator. A level shifter coupled to the current-controlled oscillator amplifies the oscillator signals to full rail and adjusts the duty cycle at its output to 50% to produce the clock signal generator output signal.

Abstract: A phase-locked loop (PLL) circuit includes a low-pass filter, a voltage controlled oscillator that produces a PLL signal having a frequency that differs according to a control voltage supplied by the low-pass filter, a phase detector which receives the PLL signal and a reference signal and detects a phase difference between them to produce an error signal, and a charge pump that, in response to the error signal, supplies a charge to the low-pass filter or extracts a charge from the low-pass filter. The charge pump includes a variable resistance element the resistance of which varies when the error signal is applied, thereby nonlinearly adjusting the charge supplied to or extracted from the low-pass filter with respect to the duration of the error signal from the phase detector.

Abstract: A system and method for regulating the voltage at an input node of a varying current demand circuit is provided. The input node may be a power supply node and the varying current demand circuit may be a controllable oscillator. In addition, a frequency synthesizer may be formed from a phase locked loop which includes the controllable oscillator and a voltage control circuit. The voltage control circuit may receive an input control signal that varies as the current demand of the controllable oscillator varies. In response to the input control signal, the voltage control circuit may provide a more stable voltage supply to the controllable oscillator even as the current demands of the oscillator vary widely. The input control signal may be generated by generating a signal from the loop path of the phase locked loop. The frequency synthesizer may be utilized in a data storage system data detection circuit, such as for example, a data detection circuit used for recovering data from an optical disk.

Abstract: An improved phase locked loop (PLL) circuit is provided for use in microprocessor clock generation. A ring oscillator provides an output frequency signal. A voltage to current converter converts differential control voltages to a variable reference current applied to the ring oscillator. A range control reference current generator applies a range control reference current to the ring oscillator. A range control operatively controls the range control reference current generator to sequentially change the range control reference current applied to the ring oscillator. A lock detector coupled to the range control compares the output frequency signal and a reference frequency signal and responsive to the compares signals applies a locked signal to the range control. Responsive to an applied locked signal, the range control stops changing ranges. The phase locked loop (PLL) circuit automatically sweeps through multiple frequency subranges responsive to the range control.

Abstract: A phase-locked loop design is provide that can operate at a plurality of dissimilar supply voltages. By adjusting the frequency range of a PLL based on the power supply voltage, the same PLL design can operate at different supply voltages.