Abstract: A current source suitable for use as a loop filter in a phase-locked loop having two aspects of automatic gain control one for prohibiting the voltage controlled oscillator from stopping as the input voltage approaches the limits of the oscillator and another to compensate for current limiting drain to source voltage drops.

Abstract: A low leakage, metal oxide semiconductor field effect transistor (MOSFET) charge pump circuit includes P- and N-MOSFET current mirrors, P- and N-MOSFET current switches and an output node. The P-MOSFET current mirror sources an output current which is switched by the P-MOSFET current switch in accordance with a pump-up control signal to provide a pump-up current. The width of the channel of the P-MOSFET current switch is substantially less than the sum of the widths of the channels of the P-MOSFETs of the P-MOSFET current mirror. The N-MOSFET current switch, in accordance with a pump-down control signal, switches a pump-down current which is sunk by the N-MOSFET current mirror. The width of the channel of the N-MOSFET current switch is substantially less than the sum of the widths of the channels of the N-MOSFETs of the N-MOSFET current mirror.

Abstract: A bias voltage generator for a voltage controlled oscillator is described. In one aspect of the invention, the bias voltage generator includes a biasing circuit to generate a minimum clock output at zero operating voltage, and includes a common mode rejection circuit for the BIASN and BIASP control voltages for the differential delay stages and a IDD test current shut-down circuit. A differential delay stage is described that includes a current source controlled by the BIASN and BIASP control voltages from the bias voltage generator, a resistance linearization circuit for current controlling transistors of a BIASN circuit, and a process variation circuit for compensating for temperature and process variations. The improved characteristics of the resulting VCO permits high frequency operation with a relatively low gain, relatively constant gain throughout operating voltage range, improved noise rejection capabilities, increased speed of delay stage, and reduced output signal swing.

Abstract: A compact PLL circuit (100) and method of operation are provided which include a phase/frequency detector circuit (102), a control voltage generating circuit (110), and a VCO circuit (108) including at least one delay buffer circuit (118). A transmission gate (M3, M4) is arranged in series with each delay element (M5, M6) in the VCO circuit (108). A plurality of "power down" transistors (M3, M8-M9, M13-M16) are arranged strategically in the control circuit (110), and a "power down" transistor (M7) is arranged strategically in at least one delay buffer circuit (118). A filter arrangement (R1, R2, C) is included in the control circuit (110). Consequently, a relatively compact PLL circuit design is provided in which output jitter is minimized, the overall stability of the PLL is maximized, and only leakage current is drawn from the PLL circuit (100) during a "power down" mode of operation.

Abstract: A voltage controlled oscillator (VCO) 16 generates a periodic clock signal without the use any resistors. Therefore, the described VCO may be advantageously incorporated into devices fabricated with semiconductor processes without special resistor-base design constraints.

Abstract: A phase-locked loop design is provided that can operate at a plurality of dissimilar supply voltages. By adjusting the frequency range of a PLL based on the power supply voltage, the same PLL design can operate at different supply voltages.

Abstract: The voltage-controlled oscillator (VCO) of the present invention is designed with reduced sensitivity to power supply voltage variations. The VCO includes multiple inverter stages with dc supply inputs tied to a filtered control dc signal, and a disabling circuit for disabling oscillation. The disabling circuit includes a disabling gate connected to the input to said inverter stages and an enabling gate connecting to the output of the inverter stages for enabling transmission of output from the VCO.

Abstract: A PLL circuit comprising a phase comparator unit which forms a differentiation signal based upon both edges of an external signal, outputs an early pulse only during a period in which the differentiation signal is overlapped on a period from the leading edge to the trailing edge of a reference signal, and outputs a late pulse only during a period in which the differentiation signal is overlapped on a period from the trailing edge to the leading edge thereof, a charge pump unit which calculates and compares the amounts of integration of the early pulse and the late pulse, lowers the output voltage when the amount of the late pulse is larger than the amount of the early pulse and raises the output voltage when it is smaller, and a VCO which outputs a corrected reference signal of which the frequency decreases or increases accompanying the increase or decrease in the output voltage of the charge pump unit, wherein the VCO is controlled by the output voltage of the charge pump unit and by the early pulse and the

Abstract: A fully differential voltage controlled oscillator having a large common mode rejection ratio is disclosed with a first and a second phase detector disposed between the output of a differential comparator and the input of a differential triangle wave generator to insure 180 degree out of phase operation.

Abstract: A phase locked loop (10) has a first (24) and a second (28) feedback path by which a generated clock signal may be phase and frequency matched to an input reference clock signal. The two feedback paths are delay matched so either one may be used to maintain "PLL lock." However, the first path consumes significantly less power than the second path. Control circuitry (22) selects which path is fed back through a multiplexer (126) and disables the second path when the path is not needed.

Abstract: A fully-symmetric high-speed CMOS frequency synthesizer which exhibits minimum dead-zone effects is disclosed. A fully-symmetric phase-frequency detector and a fully differential charge-pump filter combined with a voltage-controlled oscillator are key elements of the invention described.

Abstract: A phase lock loop comprises a phase detector (11), a frequency adjuster (13, 15) for adjusting and cancelling phase differences detected by said phase detector (11) and responsive thereto, and a filter (12) coupled between said phase comparator (11) and said frequency adjuster (13, 15). The phase lock loop has a first and a second operating mode (FIG. 5). Operation in said first operating mode is used to establish an initial lock acquisition to a desired output signal f.sub.out and uses a relatively wide bandwidth within the filter (12). At a transition from said first operating mode to said second operating mode, initial lock acquisition is lost, whereafter said second operating mode is used to re-establish final lock acquisition to the desired output frequency f.sub.out. A gain adjuster (15) commences the controlled adjustment of the gain of said phase comparator (11) at a transition between said first and said second operating modes.

Abstract: An oscillator system and method in which a time period (inverse of frequency) of a multi-stage ring oscillator (ROSC) is adjusted by a bias current which controls the charging and discharging times of respective capacitors (e.g., interelectrode capacities) within each stage. The time periods of the unadjusted oscillator are counted along with the time periods of a reference clock over a same period of time and a count difference between the two counts is determined. The count difference is applied by a logic circuit in accordance with an algorithm relating count differences to incremental bias current levels to adjust the frequency of the oscillator. The logic circuit generates digital gate signals corresponding to the count difference and these signals automatically select the bias current level needed to bring the oscillator frequency into close agreement with the reference clock frequency.

Abstract: A charge-pump circuit for controlling a voltage controlled oscillator by converting a phase difference between two input signals, which never become low at the same time, into a voltage. The charge-pump circuit includes first and second feeder circuits, made of bipolar transistors, outputting current in accordance with the input signals; a capacitor circuit having first, second, and third capacitors, and the first and the second or the first and the third capacitors are charged by the output current from the first or the second feeder circuit; and a differential amplifying circuit amplifying the voltage between the ends of the first capacitor to a predetermined voltage for output. The differential amplifying circuit operates to draw the same leakage current from the second and the third capacitors when the first capacitor is not being charged.

Abstract: A phase synchronization circuit including a phase-locked-loop synchronizes a phase of a clock signal with a phase of a reference clock signal having a frequency desired by a user. The gates of an NMOS transistor and a PMOS transistors are connected in common to a resistor. The drain and the source of the NMOS transistor are both connected to a ground potential while the drain and the source of the PMOS transistor are both connected to a power source voltage. By changing a number of NMOS and PMOS transistors formed during a metallization process, the capacitance in a loop filter is easily changed.

Abstract: A phase-locked loop circuit includes a voltage controlled oscillator. A phase comparator compares the phase of the output signal of the voltage control led oscillator with a reference signal. A loop filter to which the output signal of the comparator is applied provides a control signal to the voltage controlled oscillator. The voltage controlled oscillator is formed by interconnecting a plurality of oscillator components according to a desired wiring pattern. Each wiring pattern determines the basic oscillation frequency of the voltage controlled oscillator. A loop filter is formed by interconnecting a plurality of loop filter components according to another wiring pattern. Each wiring pattern determining the time constant of the loop filter. The oscillator components, the wiring pattern interconnectors, the comparator, the loop filter components and its wiring pattern interconnectors are disposed on a single substrate.

Abstract: In a phase synchronization circuit for generating a clock signal from an input signal, having a VCO, a phase comparator for comparing the phase of the input signal with that of an output signal of the VCO, and a loop filter for receiving an output signal of the phase comparator and providing a control voltage for the VCO, the loop filter includes first and second voltage-current converters for receiving the output signal of the phase comparator; a capacitor to be charged and discharged according to an output current of the first voltage-current converter; and a resistor for converting the output signal of the second voltage-current converter into the control voltage for the VCO.

Abstract: Programmable phase locked loop circuit and method of programming same. The cross-over frequency of the phase locked loop circuit can be changed solely by programming the gain constants of the phase-locked loop, while preserving the phase margin at each programmed operating frequency.

Abstract: A charge pump circuit for a phase-locked loop circuit which provides substantially constant charge and discharge currents characterized by minimal overshoots and undershoots. The charge pump circuit includes a level shifter circuit which attenuates voltage swings in Up and Down signals from the phase detector and provides control signals. The charge pump circuit also includes a feedback circuit coupled to the level shifter which compares the output voltage of the charge pump to predetermined first and second reference voltages and increases and decreases the charge and discharge currents to minimize overshoot and undershoot noise as determined by the control signals.

Abstract: A phase locked loop PLL circuitry for use in a radio pager. A power source applies a voltage to a charge pump circuit. A power supply control circuit controls the application of the voltage.

Abstract: A device for converting binary logic pulses into an output current and the output current being switchable between a positive and negative polarity. The device provides a charge pump circuit which is suitable for the phase-detector stage in a phase-locked loop (PLL) circuit. The charge pump circuit comprises an input stage for the "UP" binary logic pulses and a second stage for the "DOWN" binary logic pulses. The input stages comprise emitted-coupled transistor pairs. The circuit includes current sources and current sinks for generating the output current in the input stages in response to the binary logic pulses. The circuit features a pair of switch diodes coupled between the outputs of the input stages. The diodes form a commutator which controls the direction of the output current and the leakage current during the idle states. The circuit also includes a clamping circuit to limit the voltage swing across the switching diodes.

Abstract: A current sourcing and sinking circuit for driving a charge pump for a voltage-controlled oscillator includes two similar subcircuits, each of which is capable of simultaneously sourcing and sinking output currents. Both subcircuits have identical, corresponding CMOSFET components with two open drain outputs, one of which is a current sourcing output port and the other of which is a current sinking output port. In one subcircuit the current sourcing output port is used while the current sinking output port is terminated drain-to-source with a short circuit. In the other subcircuit the current sinking output port is used while the current sourcing output port is terminated drain-to-source with a short circuit. The similarity of the two subcircuits provides a balanced current sourcing and sinking circuit topology, resulting in substantially equal source and sink current amplitudes and current sourcing and sinking activation timing.

Abstract: A phase-lock loop circuit including a voltage-controlled oscillator for generating a clock signal. The voltage-controlled oscillator includes a plurality of multiplexers coupled in series. The signal generated by the last multiplexer in the series is used as a clock signal. Each of the multiplexers in the series has a select input. Either a first signal or a second signal propagates through the series of multiplexers, depending on a select signal applied to the select inputs of the multiplexers. The second signal is the first signal with a predetermined delay. A 3-input multiplexer is connected to the first and last multiplexers in the series to the form a ring oscillator. The first or second signals output by the last multiplexer in the series is sent to an input of the 3-input multiplexer, and a test signal is sent to a third input of the 3-input multiplexer. The 3-input multiplexer also receives the select signal and a test mode signal.

Abstract: A voltage controlled oscillator (VCO) including a negative feedback circuit operates in response to a negative feedback signal generated during active transistor region operation of transistors in transconductance amplifying stages coupled thereto. As a result, harmonic distortion and problems of noise and unstable frequency oscillation are obviated or significantly reduced. The VCO includes first and second variable transconductance (gm) amplifying stages whose non-inverting (+) and inverting (-) terminals are respectively grounded and a first condenser connected between an output terminal of the first transconductance (gm) amplifying stage and a non-inverting (+) terminal of the second transconductance (gm) amplifying stage. A negative-resistive circuit is used to provide a negative feedback.

Abstract: A phase lock loop (PLL) is configured as a frequency synthesizer with a first programmable frequency divider placed in the input signal path and a second programmable frequency divider located between the output of an current controlled oscillator (ICO) and the second input of a phase detector. A charge pump receives control pulses from the phase detector to generate first and second currents to control the ICO. The control currents are low-pass filtered and summed before application to the ICO. To improve loop stability, the summation current to the ICO is duplicated and used to control the bias on the charge pump. With proper biasing, first and second control currents become dependent on the second programmable divider ratio and maintain the unity gain bandwidth of the loop constant at a value much less than the digital sampling rate.

Abstract: An autoranging phase-lock-loop circuit compares an oscillator signal output from a range programmable voltage controlled oscillator, which generates the oscillator frequency within one of a plurality of operating ranges, to a reference signal and commands the voltage controlled oscillator to step to a next operating range if the voltage controlled oscillator cannot lock onto the reference signal within a prescribed time.

Abstract: The frequency control and phase control of a voltage-controlled oscillator (50) of a phase-locked loop (100) comprise two current paths. The frequency control system comprises a filter (75) that converts pulse output current (i.sub.1) of a charge pump (70) generated by phase error signals (X.sub.1, X.sub.2) to a DC voltage, and a resistor (R.sub.1 or R.sub.2) that converts that voltage to DC current (i.sub.3), and the phase control system comprises a charge pump (80) that generates a pulse output current (i.sub.2) using the phase error signals (X.sub.1, X.sub.2). The frequency and phase of the oscillator output (V.sub.OUT) of the voltage-controlled oscillator (50) is controlled by a composite current i.sub.4, which is the sum of the DC current (i.sub.3) and the output current i.sub.2. Since it is possible to make the natural angular frequency proportional to the data transfer rate while the damping factor remains unchanged, by changing the value of the currents (i.sub.3, i.sub.

Abstract: A circuit (10) for providing recovery of a phase locked loop circuit when lock has been lost has been provided. The circuit includes a lock indicator circuit (24) for detecting when the phase locked loop circuit has lost lock on an input reference signal. When such loss has occurred, an override circuit (28) is rendered operative to decrease the voltage appearing at the input of a VCO within the phase locked loop thereby slowing down the frequency of the VCO and allowing the phase locked loop circuit to recover lock. Further, a logic circuit (30) detects when the voltage appearing at the input of the VCO has fallen below a predetermined threshold voltage and renders the override circuit non-operative.

Abstract: In a frequency synthesizer, a first pulse removing circuit (31) is connected between a reference signal generator (21) and a phase-frequency comparator (24). A second pulse removing circuit (32) is connected between a variable frequency divider (23) and the phase-frequency comparator. Responsive to first removing data indicative of a first pulse number, the first pulse removing circuit removes pulses from the reference signal that are equal in number to the first pulse number for a first predetermined cycle to produce a first pulse removed signal. Responsive to second removing data indicative of a second pulse number, the second pulse removing circuit removes pulses from the divided signal that are equal in number to the second pulse number for a second predetermined cycle to produce a second pulse removed signal. Responsive to a current command, a current controlling circuit may control current supplied from/to a charge pump circuit (25).

Abstract: A digital-to-analog converter--preamplifier apparatus serving as an interface between a source of digital audio signal data and an amplifier is disclosed. A digital stage receives multiple digital audio signal inputs, a selected one of which is analyzed by a digital audio interface receiver, processed by a digital signal processing device and a delta-sigma modulator prior to passing to the analog stage for conversion from the digital domain into left and right channel analog audio output signals. Volume control is performed on the audio signal in both the digital domain and the analog domain in order to optimize performance and minimize noise. The present invention automatically adjust for input word lengths of greater than 18-bits.

Abstract: In a frequency synthesizer, a first pulse removing circuit (31) is connected between a reference signal generator (21) and a phase-frequency comparator (24). A second pulse removing circuit (32) is connected between a variable frequency divider (23) and the phase-frequency comparator. Responsive to first removing data indicative of a first pulse number, the first pulse removing circuit removes pulses from the reference signal that are equal in number to the first pulse number for a first predetermined cycle to produce a first pulse removed signal. Responsive to second removing data indicative of a second pulse number, the second pulse removing circuit removes pulses from the divided signal that are equal in number to the second pulse number for a second predetermined cycle to produce a second pulse removed signal. Responsive to a current command, a current controlling circuit may control current supplied from/to a charge pump circuit (25).

Abstract: A variable bandwidth phase-locked loop clock generator circuit is disclosed. The PLL circuit includes a phase comparator which presents pump-up and pump-down signals, indicating the polarity of the desired frequency change. The phase comparator also generates multiple level control outputs to control the rate of the frequency change. A current source includes a reference leg having a plurality of resistors which are shorted out according to the control outputs, from which a bias signal is generated. The level of the bias signal controls current sources in the output leg of the current source to control the rate of change of the voltage applied to the voltage controlled oscillator. In addition, the bias signal also controls the slew rate of an active low-pass filter according to the desired response characteristic; the output of the filter is applied to the voltage controlled oscillator for generating the output clock signal.

Abstract: An electronic circuit (100) includes a load stage circuit (116) having at least one FET (118 and 120). The load stage circuit (116) includes an adjustment terminal responsive to an adjustment voltage for controlling the load resistance of the FET (118 and 120). The electronic circuit (100) also includes a bias current generator (124) for generating a bias current. A current steering circuit (122) controls the amount of bias current supplied to the load stage circuit (116). The electronic circuit (100) also includes a plurality of output terminals (112 and 114) for providing an output which is responsive to voltages applied at input terminals (104, 106 and 108) of the current steering circuit (122). Circuit (100) alllows for the adjustment of the bias current to the circuit in order to achieve optimum power dissipation over changing operating conditions.

Abstract: A radio frequency amplifier comprises a differential amplifier having a pair of differential first and second transistors and a first and a second load resistor; an emitter grounded amplifier having a third transistor and a third load resistor; and a reference voltage generator having a constant-current source formed by a fourth transistor and a fourth load resistor. The emitter grounded amplifier receives a high frequency input signal and outputs a single signal output. One input node of the differential amplifier receives the output from the emitter grounded amplifier and the other input node receives a reference voltage from the reference voltage generator. The third and fourth transistors form a current-mirror circuit.

Abstract: A high speed voltage controlled oscillator (VCO) providing for low sensitivity to the noise on the integrated circuit's (IC) power supply. The VCO circuit creates a supply voltage for a ring oscillator independent of the IC's power supply thereby controlling the frequency of operation independent of variations on the IC's power supply. A high speed CMOS level shifting circuit provides for converting outputs of the VCO with low logic level and varying frequencies to a signal with a full CMOS logic level and low duty cycle distortion.

Abstract: A multiple frequency scan oscillator control system includes a phase locked loop operative upon a scan oscillator to provide phase and frequency synchronization thereof to a periodic reference signal. A static phase error correction is operative to provide adjustment of the free-running or static frequency of the scan oscillator. An error amplifier includes a pair of intercoupled differential amplifier configurations one having a constant current source and the other having a frequency dependent current source which responds to a frequency dependent bias current to alter amplifier gain. A threshold detection circuit includes a differential amplifier pair coupled to a pair of switching circuits for establishing a threshold action in response to system error voltage to indicate large magnitude error voltages and signal the need for free-running frequency adjustment of the oscillator.

Abstract: A phase-locked loop having automatic internal phase offset calibration includes a voltage-controlled oscillator circuit for generating a recovered data signal in response to an error signal. A phase detector determines the phase difference between the recovered data signal and a reference data signal. The phase-locked loop further includes a charge pump circuit, coupled to the phase detector, for generating an error signal in response to the detected phase difference. The charge pump circuit includes first and second pump generators for respectively providing first and second sets of pump signals, with the pump generators being interconnected to facilitate generation of the error signal. The phase-locked loop is designed to alternate between operation in phase correction and phase calibration cycles. In each phase correction cycle an error signal is synthesized as described above on the basis of the most recent phase comparison.

Abstract: The object of the description is a phase-locked loop circuit in the form of an integrated circuit (IC) including in sequential connection a digital phase comparator, to the input of which is supplied a reference frequency (fref); a loop filter; and a voltage-controlled oscillator, from which a feedback branch is fed to the second input of the phase comparator. The voltage (.phi.V; .phi.R) of the pulses obtained from the digital phase comparator is disposed so as to be adjusted by limiting means so as to modify the bandwidth and rate of the loop. The adjustment of the voltage of the pulses can be carried out, e.g., by limiting the supply voltage of the phase comparator or by means of an exterior diode or transistor limiter (Q2, Q3). The circuit is usable e.g. in radiotelephone applications, in which loop rate is increased during channel switching.

Abstract: A phase locked loop IC comprising a voltage controlled oscillator which generates a clock signal in accordance with a control voltage, a first ECL input buffer which is an input buffer for a signal to be synchronized, a phase-lock capture circuit for producing a current determinative of the control voltage in accordance with the phase difference and the frequency difference between the signal to be synchronized and the clock signal, and a phase-lock follow-up circuit for producing a current determinative of the control voltage in accordance with the phase difference between the clock signal and the signal to be synchronized; wherein the supply voltage system of the first ECL input buffer is so disposed as to be isolated from any of the supply voltage systems of the voltage-controlled oscillator, the phase-lock capture circuit and the phase lock follow-up circuit, while the ground system of the first ECL input buffer is so disposed as to be insolated from any of the ground systems of the voltage-controlled osc

Abstract: A clock generator (30) dynamically generates a system clock in response to a high or a low frequency oscillator. An amplified oscillator input is provided to a first input of a multiplexor (62), a divider (56), and a comparator circuit (58, 60). Divider (56) divides an oscillator input frequency to provide a divided input to a second input of multiplexor (62). Comparator circuit (58,60) compares the input frequency with a reference frequency to determine whether the input frequency is high or low. If the input frequency is low, multiplexor (62) is enabled to provide the oscillator input as the system clock. If the input frequency is high, multiplexor (62) provides the divided input as the system clock. Additionally, comparator circuit (58,60) provides a control signal to enable an amplifier (50) to amplify the oscillator input using a high or low gain factor in accordance with the input frequency.

Abstract: An improved phase lock loop frequency synthesizer capable of handling both analog and digital transmission. The synthesizer includes a reference signal source, a phase detector coupled to the reference signal source, a phase lock loop filter coupled to the phase detector, and a voltage controlled oscillator coupled to the phase lock loop filter for providing an output and a feedback signal to the phase detector. The phase lock loop filter comprising a charge pump coupled to the phase detector for providing a phase lock signal to a charge pump output node, said phase lock signal being variable in response to a bandwidth control signal; and a filter coupled to the charge pump for filtering the phase lock signal at a given bandwidth, said bandwidth being variable in response to the bandwidth control signal.

Abstract: The frequency of a local oscillator is maintained within a small frequency window around any one of a number of reference frequencies so that it can lock onto the frequency of an incoming color burst (CHRM). The oscillator (10) may be a current-controlled oscillator. Its control input is switched via a fet (32) to a capacitor (20) charged to a voltage level which will, when connected to the oscillator control input, result in the correct oscillator frequency (Fo). The connection to this capacitor (20) is made when the charge on either one of two control capacitors (22,24) exceeds a threshold value. The threshold values are exceeded when the local oscillator frequency (Fo) is respectively greater than or less than the reference frequency (Fr) by a predetermined frequency difference.

Abstract: A phase locked loop system having a non-linear voltage controlled oscillator (VCO) is provided with a variable gain charge pump. The charge pump supplies a pump current to an integrating network which transforms the pump current into a frequency-modulating input voltage. The frequency-modulating input voltage is applied to an input of the VCO. The frequency-modulating input voltage is also coupled to a gain control input of the variable gain charge pump so that the magnitude of the pump current will be a function of the absolute value of the frequency-modulating voltage.A substantially constant loop gain may be obtained in the phase locked loop system by arranging the gain function of the variable gain charge pump in counterposed relation to the slope of a VCO transfer function defining the nonlinear relation between the frequency-modulating input voltage of the VCO and the output frequency of the VCO.

Abstract: A one-shot whose period is a fraction or multiple of the VCO period in a clock recovery circuit. In a clock recovery circuit using PLL, the one-shot is coupled to the PLL in order to enable/disable the phase detector for cases when the data stream does not consist of uniformly spaced pulses. Without a one-shot, the phase detector in the PLL generates a large error signal whenever a clock pulse occurs without a data pulse. During the times when the phase detector is enabled, a phase comparison is made between the next data edge and the next clock edge. When this comparison is completed, the phase detector is disabled again. In order for the PLL to average out the effects of noise and jitter, the phase detector is enabled one half clock period before the data edge. By doing this, the data edge can shift up to one half clock period.

Abstract: Separate charge pumps (58, 60 and 74, 76) drive integral and proportional control paths for a voltage-controlled oscillator (52) in a phase-locked loop (50). A control circuit (74) varies the loop gain of the phase-locked loop by varying the current supplied by the integral-path charge pump (58,60) through a range that is the square of the range through which the current supplied by the proportional-path charge pump (74, 76) is varied. As a consequence, the damping factor of the loop response changes very little as the loop gain is varied through a large range.

Abstract: By using an EIP source lock counter, a frequency of a Gunn oscillator is stabilized. This increases the frequency stability of a circuit. An oscillation output of the Gunn Oscillator is supplied to the EIP source lock counter, and a phase lock signal indicative of a phase shift of the oscillation frequency from the EIP source lock counter relative to a preset reference frequency is supplied to a driver circuit. The driver circuit includes level shift circuit which level-shifts the phase lock signal thereof. A phase compensation circuit in the driver circuit boosts a gain as well as advances a phase at a high frequency region. The current amplifier circuit amplifies a current amplitude of the output of the level shift circuit, and the amplified output therefrom controls an oscillation frequency of the Gunn oscillator using negative feedback.

Abstract: An integratable phase locked loop (IPLL) comprising sampled data filter means adapted to receive a first reference signal, the filter means sampling the first reference signal (Ref In) to provide a second reference signal (Control Volts Out), and voltage or current controlled oscillator (VCO) means adapted to receive said second reference signal, the second signal serving to regulate the frequency of oscillation of the oscillator, the oscillator providing as an output a digital signal which is fed back to the filter means to provide a clock signal (CLK) for said sampling.

Abstract: A method for a phase-locked loop, which circuit includes, in a preferred embodiment, a resistor to unbalance phase detector outputs to an operational amplifier to cause the voltage output of the operational amplifier to sweep and thus cause the frequency output of a voltage controlled oscillator to sweep. Simple circuitry detects correct lock and terminates sweeping; or, if lock is not achieved, causes the output of the operational amplifier to remain at a low level until the operational amplifier is reset and then permits resweep. Very little auxiliary circuitry is required.

Abstract: A PLL circuit suitable for fabrication into an integrated circuit includes: a first phase comparator for determining a phase difference between an input signal and a first feedback signal to produce a first phase difference signal in rsponse to the phase difference; a first loop filter for removing a high frequency constituent from the first phase difference signal; a first variable frequency oscillator which oscillates at a frequency which varies in response to an output of the first loop filter to produce the first feedback signal; a second phase comparator for determining a phase difference between a reference signal and a second feedback signal to produce a second phase difference signal in response to the phase difference; a second loop filter for removing a high frequency constituent from the second phase difference signal; a second variable frequency oscillator having substantially the same characteristics as those of the first variable frequency, oscillator which oscillates at a frequency which varies

Abstract: A digital phase detector comprises a first input for receiving an output of a voltage controlled oscillator and a second input for receiving a reference signal. When a phase of the first input is in advance of that of the second input or when a frequency of the first input is higher than that of the second input, the phase detector operates to output a first control signal for decrease of an oscillation frequency of the voltage controlled oscillator. When the phase of the first input is delayed from that of the second input or when the frequency of the first input is lower than that of the second input, the phase detector operates to output a second control signal for increase of the oscillation frequency of the voltage controlled oscillator. In addition, the phase detector is configured to output neither the first control signal nor the second control signal when both of the first input and the second input are at a low level.