Abstract: A PWM signal generating circuit, printer, and PWM signal generating method are described. The PWM signal generating circuit includes: a single counter configured to count values expressed in N bits; and at least one arithmetic device configured to generate a PWM signal, each of the at least one arithmetic device including a pulse width data storage unit for storing N-bit pulse width data representing a pulse width of the PWM signal to be generated, and an adder for calculating a carry value from a most significant bit obtained when adding the count value and the pulse width data. A signal having a level corresponding to the carry value is output at every change in the count value so that the PWM signal having the pulse width of the pulse width data is generated.

Abstract: A method for providing cross point information includes: providing an input signal having amplitude and phase information; interpolating between a first point of the input signal and a second point of the input signal to provide cross point information between the first point and the second point; and providing a pulse-width modulated signal based on the input signal and the cross point information.

Abstract: The present invention provides a digitally controlled, current starved, pulse width modulator (PWM). In the PWM of the present invention, the amount of current from the voltage source to the ring oscillator is controlled by the proposed header circuit. By changing the header current, the pulse width of the switching signal generated at the output of the ring oscillator is dynamically controlled, where the duty cycle can vary between 50% and 90%. A duty cycle to voltage converter is used to ensure the accuracy of the system under process, voltage, and temperature (PVT) variations. The proposed pulse width modulator is appropriate for dynamic voltage scaling systems due to the small on-chip area and high accuracy under process, voltage, and temperature variations.

Abstract: In various embodiments, systems and methods for generating high-precision pulse-width modulation include a delay-locked loop comprising multiple delay units having time-variable delays, control logic for selecting a subset S of the multiple delay units to thereby generate a time-invariant shift amount having a precision finer than that of a system clock and circuitry for applying the shift amount to rising and falling edges of a pulse-width modulation waveform to thereby generate a high-precision pulse-width modulation waveform.

Abstract: A modulation method is provided. The modulation method includes the steps of receiving multiple sinusoidal signals, obtaining the maximum value of the sinusoidal signals, obtaining the median value of the sinusoidal signals, and obtaining the minimum value of the sinusoidal signals within a period to generate a difference between the maximum value and the minimum value, generating a difference according to an upper limit and a lower limit of a predetermined comparison value, and comparing the two differences to generate an optimized modulation signal.

Abstract: A modulation apparatus for a class D switching amplifier is capable of reducing power consumption of an Electro-Migration Interface (EMI) of an output end and a gate driver end in a zero input signal. The modulation apparatus for a class D switching amplifier includes a control unit for detecting and outputting a control signal which is a common signal component of a first modulation signal modulated by using a first input signal and a second modulation signal modulated by using a second input signal; and is characterized by feedback of a first output signal, a second output signal and a common output signal outputted by using the first modulation signal, the second modulation signal and the control signal through an input of the modulation apparatus.

Abstract: In an embodiment, a method of producing a multi-level RF signal includes producing plurality of pulse-width modulated signals based on an input signal. The method further includes driving a corresponding plurality of parallel amplifiers with the plurality of pulse-width modulated signals by setting a parallel amplifier to have a first output impedance when a corresponding pulse-width modulated signal is in an active state and setting the parallel amplifier to have a second output impedance when the corresponding pulse-width is in an inactive state. The method also includes phase shifting the outputs of the plurality of parallel amplifiers, wherein phase shifting transforms the second output impedance into a third impedance that is higher than the second output impedance, and combining the phase shifted outputs.

Abstract: In a gyro sensor, a TDC detects a magnitude of vibration of a vibrator. A drive circuit (excluding the TDC) determines a duty ratio of a PWM drive signal in accordance with the magnitude of vibration so that the magnitude of vibration becomes a predetermined magnitude and outputs the PWM drive signal having the determined duty ratio. The drive circuit (excluding the TDC) includes a control circuit and a DCO. The control circuit measures time corresponding to the control value by using a gate delay time, generates the PWM drive signal having a pulse width corresponding to the control value and outputs the PWM drive signal.

Abstract: A device for mixing multiple (N) pulse density modulated (PDM) bit streams of a bit rate, the device comprises an input logic, an error accumulation circuit, an error correction circuit and an adder of more than N bits; wherein the device is arranged to output an output PDM bit stream that represents a mixture of the multiple input PDM bit streams; wherein the output PDM bit stream comprises a plurality of output PDM bits, wherein a certain output PDM bit of a plurality of output PDM bits that form the output PDM bit stream is generated during a certain clock cycle; wherein the input logic is arranged to select, during each fraction of the certain clock cycle, a current bit of a selected PDM bit stream, wherein different PDM bit streams are selected during different fragments of the certain clock cycle; wherein the error accumulation circuit is arranged to store intermediate values during a first fraction till a penultimate fraction of the certain clock signal and to store a last value during a last fraction

Abstract: Methods and apparatus for translating duty cycle information in duty-cycle-modulated signals to higher frequencies or higher data rates. An exemplary duty cycle translator includes a duty cycle evaluator, a high-speed digital counter, and a comparator. The duty cycle evaluator generates a first digital number representing a duty cycle of a low-frequency input duty-cycle-modulated (DCM) signal. The comparator compares the first digital number to a second digital number generated by the high-speed digital counter, and generates, based on the comparison, an output DCM signal having a higher frequency or data rate than the frequency or data rate of the low-frequency input DCM signal but a duty cycle that is substantially the same as the duty cycle of the low-frequency input DCM signal.

Abstract: An example PWM includes a driver and a two-way oscillator. The oscillator includes, a first frequency adjust current source, a second frequency adjust current source, a capacitor, a switching reference and a comparator. The capacitor integrates a frequency adjust current by charging with the first frequency adjust current source. The capacitor subsequently integrates a second frequency adjust current by discharging with the second frequency adjust current source. The switching reference outputs a first reference voltage and a second reference voltage responsive to an oscillator signal. The comparator compares the output of the switching reference with a voltage on the capacitor. The first and second frequency adjust current sources vary the first and second frequency adjust currents to vary the frequency of the PWM signal to spread energy of switching harmonics over a frequency band and to reduce EMI.

Abstract: A digital pulse width modulation controller includes a pulse width modulation controller, a selection unit having at least one selector, a comparison unit having at least one comparator, and a signal conversion unit having at least one digital-to-analog converter. The digital-to-analog converter generates a reference current and/or voltage. The comparator receives the reference current and/or voltage, and performs a comparison operation to generate a comparison signal based on a feedback signal. The selector selects one selection signal to input into the pulse width modulation controller, which receives other parameters set by a user or the system at the same time so as to control characteristics of the digital pulse width modulation signals, thereby improving the electric properties of a loading circuit.

Abstract: A PWM circuit that can have two refresh rates, including: a first PWM signal generator and a second PWM signal generator; wherein the first PWM signal generator and the second PWM signal generator respectively control refresh rates in two dimensions of an output data generated from a target apparatus. A PWM signal generation method that can have two refresh rates, including: generating a first PWM signal; generating a second PWM signal; and controlling refresh rates in different dimensions of an output data generated from a target apparatus respectively by using the first PWM signal and the second PWM signal.

Abstract: A device for detecting a PWM wave, comprising: a PWM wave generating module, configured to generate the PWM wave; a detecting module coupled to the PWM wave generating module, configured to receive the PWM wave and to determine an electric level of the PWM wave; a timer coupled to the detecting module, configured to start a counting when the detecting module receives the PWM wave, and to interrupt the counting when the counting reaches a predetermined value, the detecting module determining whether the electric level of the PWM wave is a high electric level or a low electric level when the counting is interrupted; and a calculating module coupled to the detecting module, configured to calculate a duty ratio of the PWM wave based on a number of high electric level and a number of low electric level of the PWM wave determined within one period of the PWM wave.

Abstract: In an embodiment, a method of generating a pulse-width modulated signal from an input signal includes calculating a finite number of basis functions of a first pulse-width modulated signal based on the input signal, and forming an electronic output based on the calculated finite number of basis functions.

Abstract: A pulse width modulation device includes a switching transistor for defining modulation phases, a capacitor, and switches arranged to: a) in a first phase, charge the capacitor to a voltage corresponding to the on/off threshold of the switching transistor, and b) in a second phase, connect the capacitor between a terminal for applying a setpoint voltage and the gate of the switching transistor. A constant current source is connected to apply a current in the capacitor tending to bring the gate of the switching transistor toward the on/off threshold.

Abstract: The frequency characteristic of a voltage-feedback class-D amplifier circuit for driving an output load is improved. A triangular-wave correction circuit which compensates a gradient of a triangular wave is provided to a triangular-wave signal generator which supplies a triangular wave signal used as a PWM carrier to a comparison circuit for performing PWM modulation of an input signal. In an area where a duty of a command value for an output circuit drive becomes about 50%, a slew rate (gradient) of the triangular wave is decreased.

Abstract: Embodiments are directed to modulating a pulse width modulation (PWM) signal, by initializing at least one phase index to an initial value, establishing a set of values in a lookup table that correspond to data points for PWM comparator values that correspond to a given number of samples of a single periodic waveform during a predetermined sampling rate that establishes a table resolution, repeatedly executing the following operations at the predetermined sampling rate: determining a value of a command signal frequency, setting a value to a jump factor equal to the quotient of the value of the command signal frequency divided by the table resolution, progressing the value of the phase index by the value of the jump factor, selecting a value of a commutation vector from the lookup table that corresponds to the phase index, and loading the value of the commutation vector into a corresponding PWM comparator.

Abstract: An electrical resonance network comprising a first capacitor and a first inductor whose resonance frequency can be tuned by means of a second capacitor and/or a second inductor. The resulting effective capacitor- or inductor value of a network period is controlled by a variable coupling respectively decoupling interval by means of at least one coupling switch. The coupling respectively decoupling interval is synchronized by a sign change of a current and/or voltage in the network.

Abstract: An asymmetric modulation scheme may be used to drive two output nodes coupled to a load. The asymmetric modulation scheme may be one-sided such that the switching rate of a first output node is lower than the switching rate of a second output node. The first output node may be switched only to change a direction of current between the first output node and the second output node, while the second output node is switched to convey the information of an input signal. The asymmetric modulation scheme may be used to drive a speaker to reduce noise at the first output node to improve accuracy of current monitoring through the speaker by a current monitor coupled at the first output node.

Abstract: A switching mode power converter includes a DSC with a digital PWM module configured for complementary operation mode during normal operation. The control algorithm of the DSC is configured such that during an initialization stage immediately following power up of the device relevant digital PWM modules used for interleaving operation are reconfigured to temporarily operate in an independent operation mode with the duty cycle associated with each channel set at zero. The reconfigured digital PWM modules remain set in the independent operation mode for a predefined period of time. Once the predefined time period is reached, the reconfigured digital PWM modules are again reconfigured back to the original complementary operation mode configuration and the control algorithm resumes normal operation of the DSC and digital PWM modules.

Abstract: A system and method for generating a digital pulse width modulation (PWM) control signal for a power transfer device that includes providing a digital PWM signal having a stochastic characteristic and control information, storing one or more of the digital PWM signals and retrieving the signal from the storage device to determine the output of a power transfer device. The stored digital PWM signals exhibit selected frequency domain characteristics after being configured and preselected to minimize undesirable characteristics such as harmonic signatures, audible noise, component vibration, and frequency-domain energy peaks.

Abstract: An embodiment of pulse width modulated (PWM) signal generator includes a module or modules to calculate an amount of change in a period length and duty ratio of an output signal during a transition period between a first signal waveform and a second signal waveform using a first period parameter, a second period parameter, and a parameter indicating a predetermined number of steps in the transition period. The period parameter and duty parameter of the output signal during the steps of the transition period are based on the calculated amounts of change.

Abstract: An integrated circuit includes a delay lock loop (DLL) circuit that generates incremental delay line signals and a delay line output signal based on a received clock signal. A pulse-width modulation (PWM) control module generates a PWM control signal. A variable capacitance circuit is controlled based on the delay line output signal, the PWM control signal, and one of the incremental delay line signals.

Abstract: A pulse generation circuit (12) includes a PWM waveform outputting part (20) which outputs a PWM waveform having a duty ratio in which one linear PWM pulse is defined with a first number of bits, an input connector (22) which receives as an input a control signal indicating a duty ratio defined with a second number of bits larger than the first number of bits, and a setting part (24) which sets a PWM waveform to be output from the PWM waveform outputting part (20) based on the control signal input to the input connector (22) with one cycle being made up of a set comprised of a plurality of consecutive linear PWM pulses according to the second number of bits.

Abstract: A method of performing space vector modulation for PWM control for creating AC waveforms includes generating and sampling a reference signal to generate reference samples and performing a reference vector approximation to synthesize a reference vector associated with at least one of the reference samples. The reference vector approximation employs active vectors, one or more zero vectors, and one or more pseudo zero vectors in the formation thereof. Another method of performing space vector modulation (SVM) includes generating a reference signal and sampling the reference signal at a sampling frequency to generate a plurality of reference samples. The method also includes performing a reference vector approximation to synthesize a reference vector associated with at least one of the reference samples, wherein the reference vector approximation has a first portion that employs two adjacent active vectors and a remaining portion that employs two non-adjacent active vectors in the formation thereof.

Abstract: A digital pulse width modulation controller includes a pulse width modulation controller, a selection unit having at least one selector, a comparison unit having at least one comparator, and a signal conversion unit having at least one digital-to-analog converter. The digital-to-analog converter generates a reference current and/or voltage. The comparator receives the reference current and/or voltage, and performs a comparison operation to generate a comparison signal based on a feedback signal. The selector selects one selection signal to input into the pulse width modulation controller, which receives other parameters set by a user or the system at the same time so as to control characteristics of the digital pulse width modulation signals, thereby improving the electric properties of a loading circuit.

Abstract: A self-oscillating driver circuit includes a driver stage, a feedforward path which is coupled to an input of the driver stage, and a feedback path which couples an output of the driver stage to an input of the feedforward path. The feedforward path includes a feedforward filter which is designed as an active filter. In order to prevent an oscillatory state of the driver circuit at an unwanted frequency, it is proposed that an internal state variable of the feedforward filter be monitored and that the feedforward filter be reset if the value of the monitored internal state variable is outside a predefined range.

Abstract: A motherboard includes a central processing unit (CPU), a drive, and a voltage-state display system to display a voltage mode of the CPU. The voltage-state display system includes a power management chip, a first transistor, a second transistor, a first light emitting diode (LED), and a second LED. A first phase output terminal of the power management chip is connected to the first LED through the first transistor. A second phase output terminal of the power management chip is connected to the second LED through the second transistor. The LEDs indicate the voltage mode of the CPU.

Abstract: A variable frequency modulator including a compensation network, first and second pulse control networks and a linearity controller. The compensation network is configured to provide a compensation signal indicative of an output load condition. The first pulse control network is configured to initiate pulses on a pulse control signal and to adjust operating frequency based on changes of the compensation signal. The second pulse control network is configured to terminate the pulses on the pulse control signal based on a predetermined timing parameter. The linearity controller is configured to adjust timing of terminating the pulses based on a predetermined steady state operating frequency and an actual operating frequency to maintain modulator gain at a constant level.

Abstract: A system and method for a radio controlled clock receiver adapted to extract timing and time information from a phase modulated signal. The official time signal is broadcast from a central location using a modified modulation scheme, which adds phase modulation over the legacy amplitude modulation, such as the legacy WWVB pulse width modulated (PWM)/amplitude shift keying (ASK) modulation, thereby allowing for improved performance. The information modulated onto the phase contains a known synchronization sequence having good autocorrelation properties, error-correcting coding for the time information and notifications of daylight-saving-time (DST) transitions that are provided months in advance. The modulation scheme is based on a form of phase modulation, such as binary-phase-shift-keying (BPSK) or phase reversal keying (PRK).

Abstract: A pulse-width modulator (PWM) includes a plurality of comparators for comparing an input signal with a plurality of reference signals and for providing a plurality of corresponding comparison signals. The pulse-width modulator also includes a combinational logic for receiving the plurality of comparison signals and for generating a plurality of binary pulse-width modulation signals on the basis of the plurality of comparison signals. At most only a currently selected binary pulse-width modulation signal of the binary pulse-width modulation signals is at a first signal level at a time. The currently selected binary pulse-width modulation signal is associated to a specific reference signal of the plurality of reference signals which is currently closest to the input signal among the plurality of reference signals in terms of a given amplitude relation between the plurality of reference signals and the input signal.

Abstract: An amplifying circuit is provided and includes a signal processor, an edge detector, and a calibration controller. The signal processor transforms amplitude information of a first and second input signals into time domain to provide first and second output signals respectively. The edge detector detects a polarity of a voltage offset from a timing relationship of the first and second output signals. The calibration controller compensates the voltage offset according to a change of the detected polarity.

Abstract: A modulation method is provided. The modulation method includes steps of: receiving multiple sinusoidal signals; obtaining a maximum value, a median value and a minimum value of the sinusoidal signals within a period to generate a first difference between the maximum value and the minimum value; generating a second difference according to an upper limit and a lower limit of a predetermined comparison value; and comparing the first difference with the second difference to generate an optimized modulation signal.

Abstract: An apparatus and method for controlling a device using pulse signals. In the apparatus and method, a two-stage control is used to generate pulse signals, which can be a PWM signal, a pulse signal including a PWM signal with a sleeping time, or a PDM signal. The two-stage control includes a second stage control, which generates pulse signals according to parameter values generated periodically by a first stage according to a target value and feedback sensing values. The two-stage control can be used in decreasing perturbation in a closed-loop control and accurate open-loop control.

Abstract: A beat frequency cancellation circuit, for an amplifier, includes a coupling device connected between two signal processing paths of the amplifier for compensating for beat frequency effects of output signals between the signal processing paths.

Abstract: In a device, a pulse modulation switching logic is provided to generate switching signals of a pulse modulator so as to generate a pulse modulated signal with a first pulse modulation control parameter and a second pulse modulation control parameter. The first pulse modulation control parameter is controlled on the basis of a first control signal, and the second pulse modulation control parameter is controlled on the basis of a second control signal. A first control loop is provided to generate the first control signal from an output signal derived from the pulse modulated signal. A second control loop is provided to generate the second control signal on the basis of the output signal. The first and second control signals are applied to concurrently control the first and second pulse modulation control parameters.

Abstract: In an embodiment, a method of generating a pulse-width modulated signal from an input signal includes calculating a finite number of basis functions of a first pulse-width modulated signal based on the input signal, and forming an electronic output based on the calculated finite number of basis functions.

Abstract: A slope compensation module provides slope compensation of a switched-mode power supply using current mode control. The slope control unit comprises a capacitor coupled between an input and an output of the slope control unit, a switch for discharging the capacitor and a constant current source for charging the capacitor. Slope compensation parameters may be changed during operation with a programmable constant current source. The slope compensation module may also function as an analog sawtooth waveform frequency generator, and as an analog pulse width modulation (PWM) generator. Charging the capacitor generates a linearly decreasing (negative slope) ramp voltage for modulating a feedback error voltage into a slope compensated feedback error voltage. Capacitor charging may be controlled from a pulse width modulation signal. Opening of the switch may be programmably delayed, and a minimum closed time thereof may also be programmed during operation of the slope compensation module.

Abstract: A method adjusts a pulse width of a signal. The method provides a fixed voltage input trigger pulse (34), of a certain pulse width, to a pulse width generator circuit (10) and provides an output pulse (52) from the pulse width generator circuit such that a pulse width of the output pulse is longer than the certain pulse width, without changing a voltage or frequency of the input trigger pulse. The method is used to drive an injector of a diesel reductant delivery system to inject fluid into an exhaust flow path.

Abstract: A delta-sigma modulator and a transmitter apparatus including the same are disclosed. The delta-sigma modulator includes a first integrator, a second integrator, a first comparator configured to compare an output signal of the second integrator and a reference signal, and output a first comparison signal, a second comparator configured to compare the output signal of the second integrator and the reference signal, and output a second comparison signal, a first DAC configured to output the first signal corresponding to the first comparison signal and the second comparison signal, a second DAC configured to output the second signal corresponding to the first comparison signal and the second comparison signal, a delayer configured to generate a delayed signal that delays the first comparison signal and the second comparison signal by a predetermined time, and an output DAC configured to generate an output signal having a multi-level corresponding to the delayed signal.

Abstract: A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

Abstract: The PWM control circuit is provided. The PWM control circuit includes: a PWM control signal generator that generates a PWM period signal defining a period of a PWM signal and a PWM resolution signal specifying a resolution in one period of the PWM period signal; and a PWM unit that generates the PWM signal based on the PWM period signal and the PWM resolution signal, wherein the PWM control signal generator changes a frequency of the PWM resolution signal while keeping a frequency of the PWM period signal unchanged.

Abstract: A pulse width modulator for modulating a rectangular carrier signal in accordance with an input signal includes a modulating unit that receives the input signal and provides a digital output word. The output word has a pre-defined number of digits comprising a first contiguous set of binary ones (“1”) and a second contiguous set of binary zeroes (“0”) and in which the fraction of the binary ones (“1”) represents the digital input signal. The modulator also includes a random number generator that generates a pseudo-random sequence, and a flipping unit configured to flip, or not, the output word provided by the modulating unit in accordance with the pseudo-random sequence thus providing a randomly modified digital pulse width modulated output signal.

Abstract: The invention provides a multi-phase digital pulse width modulator (MP-DPWM) to implement a distribution scheme which applies the duty cycle in the fastest possible manner with restriction on the number of switching actions per phase and cycle, and additionally takes the number of available phases into account. It modulates switching signals according to a duty cycle input command, their previous switching states, and the current switching cycle. The controller is adapted to additionally take the residue of the previous subcycle into account. In the control scheme: each phase is allowed switch up to twice per cycle; only the next phase in the cycle is additionally turned on, at the start of a subcycle, and if a phase is still on at the end of a subcycle it can be kept on for longer, if required.

Abstract: A low-cost ultra-versatile pulse width modulation (PWM)-timer controller system is disclosed for use in the electric power management industry. Using different voltage/current buffer devices, the present system is capable of performing a variety of control applications, including for example as a pulse width modulation controller, power factor correction circuit, silicon controlled rectifier or thyristor, zero-voltage drive circuit, AC/DC boost converter, battery charger, motor RPM controller, timer or clock, light intensity controller, temperature range controller, pressure controller, sensing/monitoring/warning system, or analog logic circuit.

Abstract: A control circuit adjusts the duty cycle of a PWM control signal. An analog processing component within the control circuit receives an analog feedback input signal and compares it to an analog reference signal to generate a pre-processed signal. A sigma-delta modulator within the analog processing component generates a quantized signal based on the pre-processed signal. A digital processing component stores a value. The controller then adjusts the duty cycle of the PWM signal to correspond to the value. A clock keeps the system synchronized.

Abstract: An amplifier circuit includes a modulation signal generating circuit, a driving stage circuit and an output stage circuit. The modulation signal generating circuit generates a pair of modulation signals according to a pair of differential input signals and a plurality of clock signals. The driving stage circuit generates a pair of driving signals according to the pair of modulation signals. The output stage circuit generates a pair of amplified output signals according to the pair of driving signals.

Abstract: An controller for use in a power supply includes a variable oscillator and a digital-to-analog converter (DAC). The variable oscillator generates a switching signal having an on-time and a switching period to control a first switch to regulate an output of the power supply. The DAC provides the variable oscillator with a first analog signal and a second analog signal, where the on-time of the switching signal is responsive to the first analog signal and where the switching period is responsive to the second analog signal. The DAC includes a current source and a second switch that is configured to couple the current source to provide current to the first analog signal in response to a binary digit received by the DAC, and to couple the current source to provide current to the second analog signal in response to a complement of the binary digit.

Abstract: First information is received at a first pulse width modulation (PWM) module responsive to a chip select signal being asserted at a chip select input of a communication bus of the first PWM module during a first time. The first information is latched at a control register of the first PWM module in response to a first logic transition of the chip select signal. A first PWM signal is provided at a first output of the first PWM module beginning a predetermined amount of time after the first logic transition of the chip select signal, the first PWM signal generated by the first PWM module based upon the first information.