Abstract: Multiple pulse width modulation (PWM) generators each have a separate phase offset counter creating a phase shift. The phase shifting process is separated from the duty cycle generation process, thereby easing the task of preserving the duty cycle and phase relationships among the various PWM channels following an asynchronous external synchronization event. A master time base generates a PWM cycle start signal that resets the phase offset counters in each of the PWM generator circuits. The phase offset counter continues counting until it matches the respective phase offset value. Then, the associated duty cycle counter is reset and restarted. The duty cycle continues until its count matches the specified value at which time the duty cycle counter stops until reset by the terminal count from the phase offset counter. The output of the duty cycle comparators provide the output PWM signals as a repetitive series of single cycle PWM signals.

Abstract: A method is provided. An input signal is received, and a noise-shaped signal is generated from the input signal. The noise-shaped signal is formed from a plurality of noise-shaping levels. A pulse stream is generated from the noise-shaped signal over a plurality of periods, where each period has a plurality of frames. The pulse stream also includes a plurality of pulse sets, where each pulse set is associated with at least one of the noise-shaping levels, and, for each pulse set having a total pulse width for its period that is less than its period and greater than zero, each pulse set includes at least one pulse in each frame for its period.

Abstract: A pulse-width modulator (PWM) includes a plurality of comparators for comparing an input signal with a plurality of reference signals and for providing a plurality of corresponding comparison signals. The pulse-width modulator also includes a combinational logic for receiving the plurality of comparison signals and for generating a plurality of binary pulse-width modulation signals on the basis of the plurality of comparison signals. At most only a currently selected binary pulse-width modulation signal of the binary pulse-width modulation signals is at a first signal level at a time. The currently selected binary pulse-width modulation signal is associated to a specific reference signal of the plurality of reference signals which is currently closest to the input signal among the plurality of reference signals in terms of a given amplitude relation between the plurality of reference signals and the input signal.

Abstract: New methods for generating through-zero pulse-width modulation are disclosed. In one approach, a periodic reference signal varies over time over at least one portion of the period. A pulse-width control signal varies linearly with time over at least one portion of the reference signal. The reference signal is compared with the pulse-width control value to produce a first pulse waveform. The value of a function of the control value is subtracted from the first pulse waveform to produce through-zero pulse-width modulation. In another approach, the difference in value between two ramp or sawtooth periodic waveforms is computed to produce a pulse waveform with a time-varying DC offset that varies linearly in time. The time-varying offset-term is retained with the pulse waveform, producing through-zero pulse-width modulation.

Abstract: A pulse width modulation (PWM) system can include at least a first pulse width modulation circuit that generates a first pulse width modulated signal in synchronism with a first clock signal; a source circuit that provides a second pulse width modulated signal that is phase shifted with respect to the first pulse width modulated signal; and output logic that logically combines the first and second pulse width modulated signals to generate a pulse width modulated output signal.

Abstract: The present invention discloses a pulse width modulation driving IC. The pulse width modulation driving IC includes a first pin, for receiving a first signal, a second pin, for receiving a second signal, a comparing unit, for comparing the first signal with a reference voltage, to generate a comparison result indicating a operating mode of the pulse width modulation driving IC, and an output unit, for outputting a pulse width modulation output signal according to the first signal, the second signal and the comparison result.

Abstract: A fan speed control circuit includes a first fan, a second fan, a first temperature sensor, a second temperature sensor, a PWM regulator, and a driving module. The first temperature sensor senses a temperature of the first component to generate a first temperature signal. The second temperature sensor senses a temperature of a second component to generate a second temperature signal. The PWM regulator is connected to the first temperature sensor and the second temperature sensor. The PWM regulator generates a first PWM signal according to the first temperature signal and generates a second PWM signal according to the second temperature signal. The driving module is connected to the PWM regulator. The driving module generates a first driving voltage provided to the first fan according to the first PWM signal. The driving module also generates a second driving voltage provided to the second fan according to the second PWM signal.

Abstract: A PWM signal for driving power transistors of a half-bridge of a converter is generated with the aid of a digital circuit, in which an internal reference value is compared to the counter content of a counting ramp. In this context, a logic state of the PWM signal depends upon whether the internal reference value is greater than the counter content of the counting ramp. After each comparison between the internal reference value and the counter content, an n-bit long data word dependent on the result of this comparison is output serially as PWM signal, n being greater than or equal to 2. The resolution of the PWM signal is thereby improved by the factor n in comparison to conventional systems, without markedly increasing the circuit expenditure.

Abstract: Analog-to-digital pulse width modulation circuitry includes thermometer code generator circuitry, clock generator circuitry, delay selection circuitry, and an output stage. The thermometer code generator circuitry is adapted to generate a digital thermometer code based upon a received analog input voltage. The clock generator circuitry is adapted to generate a reference clock and a plurality of delayed clock signals. The delay selection circuitry is connected between the thermometer code generator circuitry and the clock generator circuitry, and is adapted to select one of the delayed clock signals to present to the output stage based upon the generated thermometer code. The selected delayed clock signal is delayed by an amount of time that is proportional to the generated thermometer code. The reference clock signal and the selected delayed clock signal are delivered to the output stage where they are used to generate a pulse width modulated output signal.

Abstract: A pulse width modulator based on a pair of rotary traveling wave oscillators. The first oscillator operates freely or as part of a phase-locked loop. The second oscillator operates at the same frequency as the first oscillator, but with a controllable phase offset from the first oscillator. The phase offset is set by an input voltage. A block takes the outputs of the first and second oscillators and combines them so that the output is a pulse whose width is the overlap of the oscillation signals from the first and second oscillators. The output pulse width is thus a function of the input voltage. When the pulse width modulator receives the input voltage from the output of a switching power supply, it can use the modulated pulse width to control the switching transistor of the power supply to maintain the output at a regulated voltage.

Abstract: A pulse width modulator based on a pair of rotary traveling wave oscillators. The first oscillator operates freely or as part of a phase-locked loop. The second oscillator operates at the same frequency as the first oscillator, but with a controllable phase offset from the first oscillator. The phase offset is set by an input voltage. A block takes the outputs of the first and second oscillators and combines them so that the output is a pulse whose width is the overlap of the oscillation signals from the first and second oscillators. The ouput pulse width is thus a function of the input voltage. When the pulse width modulator receives the input voltage from the output of a switching power supply, it can use the modulated pulse width to control the switching transistor of the power supply to maintain the output at a regulated voltage.

Abstract: An apparatus and method for amplifying a Transmit (Tx) signal according to an Envelope Tacking (ET) scheme in a wireless communication system are provided. A transmitting end apparatus includes an envelope gain controller for controlling a gain of a digital baseband Tx signal in accordance with power control, a detector for detecting an envelope signal from the digital baseband Tx signal whose gain is controlled, and for shaping on the envelope signal, a first Digital to Analog Converter (DAC) for converting the shaped envelope signal into an analog signal, and an envelope modulator for generating a drain bias of a power amplifier that amplifies a Radio Frequency (RF) Tx signal by using the analog envelope signal. Accordingly, a digital-based ET scheme is implemented, and by using a plurality of shaping tables, efficiency of the ET scheme can be maximized in a transmitting end that uses power control.

Abstract: A baseband signal generator (102a) provides a polar signal (A, I p) to a processing sub-unit (704p). The processing sub-unit (704p) receives furthermore feedback signals from a down converting unit (704c) which feedback signals are used to determine the magnitude (B) of the amplified output signal and the actual error phase. The magnitude (A) of the polar signal and the determined magnitude (B) are applied to a comparator (710) having its output connected to the input of a predistortion unit (214, 216). The output of the predistortion unit (214, 216) is connected to the input of a pulse width modulating unit (210, 212) which comprises a mapping unit (210) outputting two constant magnitude signals. The actual error phase and the phase component of the polar signal are used to generate a corrected phase component which is applied to a further mapping unit (202) forming part of a phase modulating unit (202, 204).

Abstract: A switch-modulator for a radio-frequency power amplifier, arranged to modulate the I-signal and the Q-signal of the complex components (I+j·Q) separately in an I-signal part and a Q-signal part in order to create a modulated I-signal pulse sequence and a modulated Q-signal pulse sequence, wherein the modulation comprises a time-shift of the pulse positions within a sample interval.

Abstract: A radio communication apparatus includes a baseband signal generator to generate digital data; a clock generator to generate 2N pulse signals corresponding to the digital data; a selector to select one of the 2N pulse signals; and a short pulse generator to reduce a pulse width of the signal selected by the selector, wherein the 2N pulse signals include a whole-period non-transmission pulse, a whole-period transmission pulse, and 2N-2 partial-period transmission pulses, when the partial-period transmission pulse is selected, a band pass filter outputs a signal that lasts for part of a period having a 1-symbol length, when the whole-period non-transmission pulse is selected, the band pass filter outputs a signal attenuated by offsetting signals corresponding to the whole-period non-transmission pulse, and when the whole-period transmission pulse is selected, the band pass filter outputs a signal that lasts for a whole of the period having the 1-symbol length.

Abstract: The present disclosure provides a high-stability pulse width modulation device which easily changes distortion compensation characteristics of an output pulse signal. The pulse width modulation device modulates a digital signal to a pulse signal having a pulse width corresponding to the value of the signal. A quantizer converts an output of a noise shaping filter to a digital signal with a small bit number. The pulse width modulator converts an output of the quantizer to the pulse signal. A compensation circuit receives the output of the quantizer, and outputs a compensation signal for compensating non-linear distortion of the pulse signal. The noise shaping filter receives both of the output of the quantizer and the compensation signal, and executes noise shaping of the input digital signal.

Abstract: A novel receiver structure is proposed for detecting a time-hopping ultra-wide bandwidth signal in the presence of multiple access interference. The proposed structure achieves better bit error rate performance than the conventional matched receiver when operating in multiple access interference. When operating in a multiple access interference-plus-Gaussian-noise environment, the receiver structure outperforms the conventional matched filter receiver for moderate to large values of signal-to-noise ratio. A receiver structure with adaptive limiting threshold is further proposed to ensure the performance of the soft-limiting receiver always meets or surpasses the performance of the conventional UWB receiver for all values of signal-to-noise ratio.

Abstract: In one aspect, the present disclosure relates to a dimmable beacon light source for a light based positioning system. In some embodiments, the light source includes a dimmer control switch configured to generate a dimmer signal having a desired light output level, a dimmable driver for controlling the light output of the light source, and a modulator for receiving the dimmer signal from the dimmer control switch, generating a digital pulse recognition signal by controlling the frequency of the dimmer signal to a desired frequency value, and transmitting the digital pulse recognition signal to the dimmable driver to drive the light output of the light source. In some embodiments, the digital pulse recognition signal is a pulse width modulated signal. In some embodiments, the digital pulse recognition signal has a duty cycle based on the dimmer signal.

Abstract: Multi-phase, frequency coherent pulse width modulation (PWM) signals are generated that maintain PWM data-set coherency regardless of user or system events. PWM data-set coherency is accomplished by adding data buffers to hold and transfer new PWM data during a data-set update from a processor. After the data-set transfer to the data buffers is complete and when the next PWM cycle is about to start, the data-set stored in the data buffers is transferred to the active PWM registers in time for the start of the next PWM cycle.

Abstract: An A/D converter circuit includes first to fourth pulse circulation circuits and first and second counters and configured to provide high conversion accuracy irrespective of a temperature change. The first pulse circulation circuit operates with a difference voltage of a specified voltage and an analog input voltage. The first counter outputs a difference of the number of pulse circulation in the first and the second pulse circulation circuits. The third pulse circulation circuit operates with a difference voltage of the specified voltage and a set voltage. The fourth pulse circulation circuit operates with the set voltage. The second counter outputs a difference of the number of pulse circulation in the third and the fourth pulse circulation circuits. When an output value of the second counter reaches a specified value, an output value of the first counter at that time is outputted as A/D conversion data.

Abstract: Extending pulse width modulation phase offset when generating phase shifted groups of pulse width modulation (PWM) signals is accomplished with a separate phase counter that is independent of the time-base counters used in traditional PWM generation circuits and that is prevented from being retriggered until an existing duty cycle has completed. This is accomplished with a phase offset counter, a phase comparator and a circuit that is triggered via a master time base for overall synchronization of the multi-phase PWM signal generation.

Abstract: Multiple pulse width modulation (PWM) generators each have a separate phase offset counter creating a phase shift. The phase shifting process is separated from the duty cycle generation process, thereby easing the task of preserving the duty cycle and phase relationships among the various PWM channels following an asynchronous external synchronization event. A master time base generates a PWM cycle start signal that resets the phase offset counters in each of the PWM generator circuits. The phase offset counter continues counting until it matches the respective phase offset value. Then, the associated duty cycle counter is reset and restarted. The duty cycle continues until its count matches the specified value at which time the duty cycle counter stops until reset by the terminal count from the phase offset counter. The output of the duty cycle comparators provide the output PWM signals as a repetitive series of single cycle PWM signals.

Abstract: Methods and apparatus for translating duty cycle information in duty-cycle-modulated signals to higher frequencies or higher data rates. An exemplary duty cycle translator includes a duty cycle evaluator, a high-speed digital counter, and a comparator. The duty cycle evaluator generates a first digital number representing a duty cycle of a low-frequency input duty-cycle-modulated (DCM) signal. The comparator compares the first digital number to a second digital number generated by the high-speed digital counter, and generates, based on the comparison, an output DCM signal having a higher frequency or data rate than the frequency or data rate of the low-frequency input DCM signal but a duty cycle that is substantially the same as the duty cycle of the low-frequency input DCM signal.

Abstract: A technique for modulating light by an optically addressed, electric charge accumulating spatial light modulator achieves substantially monotonic gray scale response. Embodiments digitally modulate the voltage across a photoreceptive material included in the spatial light modulator. The digital modulation scheme entails illuminating the photoreceptor with a series of light pulses propagating from an LCoS, in which the durations of the light pulses and their positions in time combine to produce binary-weighted equivalent rms voltages on the photoreceptor. The light pulses originate from a light-emitting diode or other switchable light source, and the timing of the light pulses is controlled such that they are emitted only when the associated LCoS is in a stable state. Emitting light pulses while the LCoS is in a stable state avoids non-monotonic behavior.

Abstract: In an embodiment, a method of producing a multi-level RF signal includes producing plurality of pulse-width modulated signals based on an input signal. The method further includes driving a corresponding plurality of parallel amplifiers with the plurality of pulse-width modulated signals by setting a parallel amplifier to have a first output impedance when a corresponding pulse-width modulated signal is in an active state and setting the parallel amplifier to have a second output impedance when the corresponding pulse-width is in an inactive state. The method also includes phase shifting the outputs of the plurality of parallel amplifiers, wherein phase shifting transforms the second output impedance into a third impedance that is higher than the second output impedance, and combining the phase shifted outputs.

Abstract: A PWM (Pulse Width Modulation) signal outputting circuit includes a counting unit for counting a number of clocks to output a counter value, and for resetting the counter value to resume counting when a reset signal is input to the counting unit; a dead time value storage unit for storing a dead time value; and a plurality of PWM signal outputting units for setting a start setting value and a termination setting value. The PWM signal outputting unit generates a termination signal and a start signal. Further, the PWM signal outputting unit is configured to output a PWM signal, which is raised according to the start signal generated by itself and is decreased according to the termination signal generated by itself. Further, the PWM signal outputting units is configured to generate the termination signal when the counter value matches to the termination setting value generated by itself.

Abstract: An vector modulator using a time delay and a phase shifter is disclosed, the vector modulator including a time delay (110) varying a phase of an input signal by time-delaying the input signal; a first coupler (120) converting the signal outputted in changed phase through the time delay to an I channel signal and a Q channel signal each having a 90° phase difference and outputting the I/Q channel signals; a first phase shifter (130) varying the phase of the I channel signal outputted from the first coupler within a predetermined phase range and outputting the phase-variable I channel signal; a second phase shifter (140) varying the Q channel signal outputted from the first coupler within a predetermined phase range and outputting the phase-variable Q channel signal; and a second coupler (150) coupling phase-variable I/Q channel signals and outputting the coupled signals.

Abstract: A triangular wave generator in a pulse width modulation signal generator to generate a triangular wave signal and a pair of pulse signals. The first pulse signal is pulsed for a given duration of time when the triangular wave signal reaches a minimum limit thereof. The second pulse signal is pulsed for a given duration of time when the triangular wave signal reaches a maximum limit thereof. The voltage comparator generates a first pulse width modulation signal by comparing the triangular wave signal with an externally supplied direct current signal. The wave shaping circuit generates a second pulse width modulation signal by removing chattering components occurring immediately after rising and falling edges of the first pulse width modulation signal with a masking signal generated based on the first and second pulse signals and the first pulse width modulation signal.

Abstract: An apparatus and methods for a baseband modulator configured to code amplitude signals into pulse width modulated time signals comprising at least two amplitude levels is disclosed. A pulse width modulator can receive a component signal of a baseband complex signal and generate a discrete-time pulse width modulated signal. This signal can be converted to a continuous time signal, such as a pulse-width modulated time signal and can be shifted to a carrier signal corresponding respectively to the component signal by a switch. Bursts sequences are generated to an input of a switched amplifier for driving operation of the amplifier therein.

Abstract: An example PWM includes a driver and a two-way oscillator. The oscillator includes, a first frequency adjust current source, a second frequency adjust current source, a capacitor, a switching reference and a comparator. The capacitor integrates a frequency adjust current by charging with the first frequency adjust current source. The capacitor subsequently integrates a second frequency adjust current by discharging with the second frequency adjust current source. The switching reference outputs a first reference voltage and a second reference voltage responsive to an oscillator signal. The comparator compares the output of the switching reference with a voltage on the capacitor. The first and second frequency adjust current sources vary the first and second frequency adjust currents to vary the frequency of the PWM signal to spread energy of switching harmonics over a frequency band and to reduce EMI.

Abstract: A pulse width modulation (PWM) controller includes a first counter for counting a reference clock signal, and thus outputting a first count value, a leading edge control signal generator for outputting a leading edge control signal on a basis of the first count value, an adjustment clock generator for generating an adjustment clock signal, a second counter controller for instructing the adjustment clock generator to start to output the adjustment clock signal, a second counter for outputting a second count value, a trailing edge control signal generator for outputting a trailing edge control signal on a basis of the second count value, and a PWM pulse generator for synthesizing the leading edge control signal and the trailing edge control signal, and thus generating a pulse width modulation signal.

Abstract: A pulse width modulation method for controlling the output power of a pulsed gas discharge laser powered by a pulsed RF power supply comprises delivering a train of digital pulses to the RF power supply. Each pulse in the train has an incrementally variable duration. The power supply is arranged to deliver a train of RF pulses corresponding in number and duration to the train of digital pulses received. The average power in the RF-pulse train can be varied by incrementally varying the duration of one or more of the digital pulses in the digital pulse train. The train of RF pulses is used to power a gas discharge laser. The gas discharge laser outputs a pulse train corresponding to the RF pulse train.

Abstract: A modulation arrangement comprises an input (E) for supplying a data signal (DS), a pre-modulator (VMod) that is coupled to the input (E) and features a clock pulse input (TEV) for supplying a pre-clock pulse (VT), a main modulator (HMod) that is coupled to the pre-modulator (VMod) on the input side and comprises a clock pulse input (TEH) for supplying a main clock pulse (HT), as well as an output for providing a modulated control signal (ST), and a switchable current source (Q, S) for providing a current (IS) that is controlled by the modulated control signal (ST) at an output (A) of the modulation arrangement. Furthermore, a method for providing a modulated control signal is disclosed.

Abstract: A method suppresses high-frequency perturbations in a pulse-width modulated signal. The pulse-width modulation may superpose a carrier signal onto an input signal having a predetermined modulation frequency. The carrier signals may be phase-shifted. The resulting modulated signals may then be filtered and combined.

Abstract: A device for detecting a PWM wave, comprising: a PWM wave generating module, configured to generate the PWM wave; a detecting module coupled to the PWM wave generating module, configured to receive the PWM wave and to determine an electric level of the PWM wave; a timer coupled to the detecting module, configured to start a counting when the detecting module receives the PWM wave, and to interrupt the counting when the counting reaches a predetermined value, the detecting module determining whether the electric level of the PWM wave is a high electric level or a low electric level when the counting is interrupted; and a calculating module coupled to the detecting module, configured to calculate a duty ratio of the PWM wave based on a number of high electric level and a number of low electric level of the PWM wave determined within one period of the PWM wave.

Abstract: A variable modulus sigma delta (??) modulator for a fractional-N frequency synthesizer in accordance with the present invention may include an integer division unit; a pulse-width modulation (PWM) generator, a ?? noise-shaping unit, a first input FRAC for receiving a first programmable integer, and a second input MOD for receiving a second input, wherein the integer division unit is configured to perform a translation from the first input and the second input into a first output FRAC? and a second output R, the PWM generator is configured to receive the second input MOD and the second output R, and generate a modulated pulse signal, and the ?? noise-shaping unit is configured to receive the first output and the modulated pulse signal, and generate a sequence whose average equals approximately the first input over the second input.

Abstract: A control circuit and method for a PWM voltage regulator combine a high frequency feedback technique with a constant on-time or constant off-time topology to improve the transient performance of the PWM voltage regulator. The PWM voltage regulator generates a constant on-time or constant off-time depending on a current for generating a PWM signal, and dynamically adjusts the current according to the droop-voltage at its output during a transient period. Therefore, the PWM voltage regulator boosts its transient response without any threshold for load step detection.

Abstract: A signal converter with an overcurrent protection mechanism comprises a pulse width modulation (PWM) unit, a timing processing and multi-level conversion unit, an overcurrent detection unit, and a pulse width control unit. The PWM unit converts an analog signal into a pulse signal. The timing processing and multi-level conversion unit receives the pulse signal and converts the pulse signal into a multi-level digital signal. The overcurrent detection unit has a reference voltage terminal outputting a reference voltage. The overcurrent detection unit receives the multi-level digital signal and converts the multi-level digital signal into a detection voltage. The pulse width control unit compares the detection voltage with the reference voltage and outputs a control signal to the PWM unit. Thereby is formed a feedback mechanism to adjust the output voltage and prevent the succeeding circuit from being damaged caused by overcurrent of the pulse signal.

Abstract: There is disclosed a method and apparatus for generating, in an envelope tracking modulator of a mobile radio transmission apparatus, a pulse width modulated, PWM, signal representing a time-varying signal, the method comprising, for each time cycle: a) generating a rising ramp from a first voltage level to a second voltage level; b) generating a falling ramp from the second voltage level to the first voltage level; c) detecting a rising slope of the time-varying signal crossing the falling ramp and responsive thereto if the PWM signal is at the first voltage level, transitioning the PWM signal to the second voltage signal; d) detecting a falling slope of the time-varying signal crossing the rising ramp, and responsive thereto if the PWM signal is at the second voltage level, transitioning the PWM signal to the first voltage signal.

Abstract: Apparatus and methods apply pre-emphasis to the phase rather of a signal than to the amplitude of a single. This approach can provide superior pre-emphasis performance than the conventional amplitude pre-emphasis techniques in certain situations, such as when a non-linear slicer is present in the signal path. For example, electrical-to-optical (E/O) and optical-to-electrical (O/E) converters can effectively slice a signal.

Abstract: An example two-way integrator includes a first current source, a second current source, a first offset current source, a second offset current source, a capacitor, a switching reference and a comparator. The capacitor integrates a sum of a first input current and a first offset current by charging with both the first current source and the first offset current source. The capacitor subsequently integrates a sum of the second input current and the second offset current by discharging with both the second current source and the second offset current source. The switching reference outputs a first reference voltage and a second reference voltage responsive to pulses of a pulse signal. The comparator is coupled to compare the switching reference with a voltage on the capacitor.

Abstract: A method is provided for controlling an actuator that can be switched into an on state and an off state by means of pulse duration modulation, as well as to a control system. The inventive method includes, but is not limited to defining a standard pulse repetition period for the square wave signal for a range of a nominal pulse-duty factor, and increasing the pulse repetition period of the square wave signal referred to the standard pulse repetition period if a nominal pulse-duty factor falls short of a first lower threshold value and/or if a nominal pulse-duty factor exceeds a first upper threshold value.

Abstract: An improved method for generating pulse width modulated signals, e.g., for use in audio amplifiers, power amplifiers, etc. An input digital value is received and divided by a number N, producing a quotient and a residue. A plurality N of edge modulation values may then be generated based on the quotient and the residue. Each of the N edge modulation values specifies an edge of the pulse width modulated signal to be generated. Generation of the N edge modulation values may comprise applying the residue to one or more of the N edge modulation values when the residue is greater than zero. The residue may be applied to different ones of the plurality N of edge modulation values during different iterations of the method in a non-stationary fashion. The pulse width modulated signal may then be generated based on the N edge modulation values.

Abstract: The present invention discloses a pulse width modulation driving IC. The pulse width modulation driving IC includes a first pin, for receiving a first signal, a second pin, for receiving a second signal, a comparing unit, for comparing the first signal with a reference voltage, to generate a comparison result indicating a operating mode of the pulse width modulation driving IC, and an output unit, for outputting a pulse width modulation output signal according to the first signal, the second signal and the comparison result.

Abstract: A method and system process a signal for PWM modulation. An amplitude control signal adjusts the amplitude of an input signal, and an offset is added to the amplitude-adjusted signal to produce an offset-adjusted signal. The offset is selected according to the amplitude adjustment applied to the input signal. The offset-adjusted signal is pulse-width modulated the to produce a pulse-width modulated signal, and the pulse-width modulated signal is filtered to reduce high frequency components thereof.

Abstract: The invention provides a method and a modulation circuit for pulse width modulation with feedback, wherein a pulse width modulated signal is provided on the basis of an input signal and a reference signal that is periodic and has a reference frequency. The pulse width modulated signal is provided in that an output signal is switched from a first voltage level to a second voltage level in dependence on a comparison between the input signal and the reference signal at least once in every cycle of the reference signal, and in that at least once at a fixed moment in time in every cycle the pulse width modulated signal is switched from the second voltage level to the first voltage level. Furthermore, a periodic correction signal is added for compensation of the switching from the second voltage level to the first voltage level in the pulse width modulated signal.

Abstract: In an embodiment, a method of generating a pulse-width modulated signal from an input signal includes calculating a finite number of basis functions of a first pulse-width modulated signal based on the input signal, and forming an electronic output based on the calculated finite number of basis functions.

Abstract: Systems and methods for the demodulation of pulse edge modulated signals for communications systems which are useful in body implanted electronics. A pulse edge modulated signal is generated by retarding or advancing each pulse edge of a carrier to be modulated relative to its original position in time, depending on the state of the digital bit to be modulated on that edge. Each modulated edge of a pulse edge modulated signal is demodulated by determining the position in time of the modulated edge relative to the original respective position of the modulated edge prior to modulation.

Abstract: A pulse width modulation (PWM) controller includes: a first counter for counting a reference clock signal, and thus outputting a first count value, a leading edge control signal generator for outputting a leading edge control signal on a basis of the first count value, an adjustment clock generator for generating an adjustment clock signal, a second counter controller for instructing the adjustment clock generator to start to output the adjustment clock signal, a second counter for outputting a second count value, a trailing edge control signal generator for outputting a trailing edge control signal on a basis of the second count value, and a PWM pulse generator for synthesizing the leading edge control signal and the trailing edge control signal, and thus generating a pulse width modulation signal.

Abstract: Systems and devices for ripple reduction in a DC/DC converter are presented. The disclosed systems and methods enable ripple reduction in discontinuous conduction mode (DCM) operation. In DCM, the inductor current peak to peak ripple may be reduced based on the load current. To achieve the reduction of the inductor peak to peak current ripple, a digital counter is used to count the time between consecutive PWM pulses. The digital output of the counter is used to control the pulse width modulation. As the digital output of the counter increases, the PWM on-time decreases. Since the PWM pulse is demanded by the load in DCM mode, the peak to peak inductor ripple is modulated by the counter, or, in turn, modulated by the load current.