Abstract: A frequency generator is provided. The generator comprises two voltage controlled oscillators generating a first signal of a given multiple of a predetermined raster frequency, and a second signal of another given multiple of a predetermined raster frequency, dividers dividing the output signal of the oscillator until the frequency of both divided output signals is equal to the raster frequency, a filter arrangement connected to the output of the dividers, and a single sideband mixer. The mixer produces as output a signal having a frequency which is equal to the frequency of the output signal of either one of the oscillators or to the frequency of the output signal of either one of the oscillators from which the output signal of the filter arrangement has been subtracted or to which the output signal of the filter arrangement has been added.

Abstract: The phase locked loop (PLL) frequency synthesizer includes a phase detector receiving a reference signal, a controlled oscillator (e.g. a voltage controlled oscillator) connected to the phase detector and generating a synthesized frequency output signal based upon the reference signal, a mixer (e.g. an in-phase and quadrature-phase (IQ) modulator) connected to the controlled oscillator, a divider connected between the mixer and the phase detector, and a signal source driving the mixer. The frequency synthesizer and method have narrow frequency steps (e.g. as low as fractions of a Hertz) while using a relatively high reference frequency to maintain low phase noise. Furthermore, the fine frequency tuning resolution is achieved while also reducing output spurs and using a relatively simple topology.

Abstract: A time-sliced discrete-time Phase Locked Loop which is suitable for simultaneously synchronizing multiple input signals to multiple output signals is provided by implementing a discrete-time phase detector, loop filter, and voltage controlled oscillator that together operate as a single discrete-time PLL in hardware and applying control logic to retrieve the history for each signal pair from a context memory (RAM), to enable the discrete-time PLL hardware, and to store the resulting history in the context memory for use in subsequent operations for a particular input/output signal pair.

Abstract: A problem of the present invention is to provide a wide band modulation PLL having good modulation accuracy at low cost. With respect to a PLL having a VCO (21), a frequency divider (22), a phase comparator (23), a charge pump (24) and a loop filter (25), the VCO (21) and a frequency dividing ratio of the frequency divider (22) are controlled to perform modulation. The VCO (21) has two control terminals for PLL and modulation, and a control signal generation part (28) generates a control voltage Vtm of the VCO (21) based on phase modulation data and an input voltage Vtl to the control terminal for PLL. At the time of adjusting a modulation factor, the control voltage Vtm to the control terminal for modulation of the VCO (21) is controlled and also the input voltage Vtl is measured and a modulation sensitivity of a frequency of the VCO (21) to Vtm is calculated and a modulation factor of the phase modulation data is adjusted based on the modulation sensitivity obtained.

Abstract: A voltage controlled oscillator 1, a variable frequency divider 2, a phase comparator 3, and a loop filter 4 form a Phase Locked Loop (PLL). A sigma-delta modulator 5 sigma-delta modulates data obtained by adding a fractional part M2 of the frequency division factor data with modulation data X by using an output signal of the variable frequency divider 2 as a clock. An output signal of the sigma-delta modulator 5 is added to an integral part M1 of the frequency division factor data, and the resultant data becomes effective frequency division factor data 13 of the variable frequency divider 2. An output signal of the sigma-delta modulator 5 also becomes control data 14 after passing through a D/A converter 6, a low-pass filter 7, and an amplitude adjustment circuit 8. The control data 14 is inputted into a frequency modulation terminal of the voltage controlled oscillator 1.

Abstract: A phase modulation apparatus is provided whereby excellent RF phase modulation signals can be obtained even when the modulation sensitivity of a voltage controlled oscillator varies. Phase modulation apparatus 100 has: phase detector 105 that performs phase detection with respect to an RF phase modulation signal outputted from VCO 101; comparator 106 that compares the phase of the detected signal with the phase of a baseband phase modulation signal and outputs the difference between the signals; variable gain amplifier 107 that controls the gain of the baseband phase modulation signal based on the output of comparator 106 and supplies the gain-controlled baseband phase modulation signal to VCO 101.

Abstract: A frequency modulation apparatus 100 has a synthesizer 101, a differentiator 102 that differentiates phase modulation data and generates differential phase modulation data, an adder 103 that adds together that differential phase modulation data and carrier frequency data fractional part K and generates addition fractional part K1, an input data operation section 104 that receives addition fractional part K1 and carrier frequency data integer part M, generates integer part input data M1 and fractional part input data K2, and provides fractional part input data K2 to synthesizer 101, and an integer part data delay section 105 that delays integer part input data M1 before providing it to synthesizer 101. Input data operation section 104 makes M1=M?1 and K2=K1+1 when K1<0, makes M1=M and K2=K1 when 0?K1<1, and makes M1=M+1 and K2=K1?1 when 1?K1.

Abstract: A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.

Abstract: First and second calibration signals (308, 309) are sent to a frequency divider (102) and an adder (116) of a PLL section (100A), demodulated in a demodulator (111), filtered through a low pass filter (113) and a high pass filter (114) and thereafter sent to a modulation signal control circuit (115). The modulation signal control circuit (115) generates control information (318) in comparison with the phase and amplitude of the first and second calibration signals (308 and 309) and sends the control information (318) to a modulation control signal generator (106). Modulation control signal generator (106) holds the control information (318) and controls the values of the first modulation signal and second modulation signal sent to the frequency divider (102) and adder (116) on the based on the control information (318) held in modulation operation.

Abstract: A PLL circuit is tuned to a first frequency by using a first digital modulation signal and subsequently tuned to a second frequency by using a second digital modulation signal. A differential signal, that is a function of the change in voltage of a VCO control signal generated by the modulation signals, is compared with a comparison signal, that is characteristic of the analog modulation amplitude. Based on the comparison the analog modulation amplitude is changed to minimize or substantially eliminate a deviation between the signals.

Abstract: A two-point modulator includes a PLL circuit and a simplified digital pre-filtering system. The two-point modulator includes a first circuit path for impressing an analog modulation signal into a first point in the PLL circuit, and a second circuit path for impressing a digital modulation signal into a second point in the PLL circuit. The second circuit path actuates a frequency divider in the feedback path in the PLL circuit and contains a digital filter which has a square-wave pulse response.

Abstract: A two-point modulator arrangement is specified, said arrangement being developed with respect to conventional two-point modulators to the effect that the high-pass coupling-in point of the modulator that comprises a phase locked loop is formed by an expanded loop filter. In accordance with the present principle, the expanded loop filter comprises a coupling-in element, at which the modulation signal is combined with the output signal of a phase comparator. A voltage-controlled oscillator having only one tuning input can thus advantageously be used.

Abstract: A frequency synthesizer is provided having a fractional-N control circuit and method that can selectively apply any fractional ratio to a frequency divider within the feedback loop of a PLL. A special digital delta-sigma modulator can be implemented as the control circuit and can receive any arbitrary numerator and denominator value, or their arithmetic combination, or a positive and negative vector values used by the modulator to achieve an average fractional division. Both the numerator and denominator (or the positive and negative vectors) can be chosen based on any integer value to achieve a more optimal, higher frequency resolution and efficient fractional-N control circuit and methodology thereof.

Abstract: A method and apparatus for generating a burst FSK signal having precisely shaped transitions between modulation states. The apparatus uses feedforward compensation of phase gain and phase preemphasis coefficients for compensating the frequency conversion gain of the apparatus, and the phase gain coefficient is used for stabilizing a frequency synthesis loop. The phase gain and preemphasis coefficients are determined in a calibration within the time constraints of on-line signal bursts based upon measured phase errors and accelerated predicted phase gain and preemphasis phase errors.

Abstract: A method and apparatus for generating a burst FSK signal having precisely shaped transitions between modulation states. The apparatus uses feedforward compensation of phase gain and phase preemphasis coefficients for compensating the frequency conversion gain of the apparatus, and the phase gain coefficient is used for stabilizing a frequency synthesis loop. The phase gain and preemphasis coefficients are determined in a calibration within the time constraints of on-line signal bursts based upon measured phase errors and accelerated predicted phase gain and preemphasis phase errors.

Abstract: A method and apparatus for generating a burst FSK signal having precisely shaped transitions between modulation states. The apparatus uses feedforward compensation of phase gain and phase preemphasis coefficients for compensating the frequency conversion gain of the apparatus, and the phase gain coefficient is used for stabilizing a frequency synthesis loop. The phase gain and preemphasis coefficients are determined in a calibration within the time constraints of on-line signal bursts based upon measured phase errors and accelerated predicted phase gain and preemphasis phase errors.

Abstract: A dual-port modulator comprising a first Phase Locked Loop (‘PLL’) (15) including a first Voltage Controlled Oscillator (‘VCO’) (10), a first variable frequency divider (20), a first multi-accumulator sequence generator (21) responsive to a phase modulation signal for controlling the division ratio (1/Nr) of the first variable frequency divider, a first phase detector (30) responsive to the relative phases of the reference signal and the first frequency divider signal for producing a first control signal through a first low pass filter (40).

Abstract: A VCO system embodying the features of the present invention includes a frequency tuning circuit, a modulation circuit coupled in a parallel fashion with the frequency tuning circuit, a band tuning circuit coupled with the frequency tuning circuit in a parallel fashion having at least one switching circuit, a core circuit coupled with the frequency tuning circuit, the modulation circuit, and the band tuning circuit, wherein upon asserting a switching signal and upon adjusting a frequency turning signal, a frequency tuning bias signal, and a band tuning signal, the switching circuit is enabled for configuring the band tuning circuit to join the frequency tuning circuit for adjusting a predetermined output frequency based on a total inductance and a total capacitance provided by the core circuit, the frequency tuning circuit, the modulation circuit and the band tuning circuit.

Abstract: A voltage controlled oscillator 1, a variable frequency divider 2, a phase comparator 3, and a loop filter 4 form a Phase Locked Loop (PLL). A sigma-delta modulator 5 sigma-delta modulates data obtained by adding a fractional part M2 of the frequency division factor data with modulation data X by using an output signal of the variable frequency divider 2 as a clock. An output signal of the sigma-delta modulator 5 is added to an integral part M1 of the frequency division factor data, and the resultant data becomes effective frequency division factor data 13 of the variable frequency divider 2. An output signal of the sigma-delta modulator 5 also becomes control data 14 after passing through a D/A converter 6, a low-pass filter 7, and an amplitude adjustment circuit 8. The control data 14 is inputted into a frequency modulation terminal of the voltage controlled oscillator 1.

Abstract: Disclosed is a delta-sigma modulated fractional-N PLL frequency synthesizer which performs fractional-N by modulating a divider that divides output frequencies from a voltage controlled oscillator. Fractional part data F from a register is forwarded to a second adder. A first adder adds output from a delta-sigma modulator to output therefrom delayed and inverted by a delay inverter to generate an artificially random bit stream averaging zero. The second adder adds fractional part data F to output from the first adder to generate an artificially random data sequence averaging a value of fractional part data. The generated data sequence is forwarded to the delta-sigma modulator. An adder adds integral part data to output from the delta-sigma modulator. Added output is forwarded to the divider.

Abstract: A digital signal processor generates in-phase, quadrature-phase and amplitude signals from a baseband signal. A modulator modulates the in-phase and quadrature-phase signals to produce a modulated signal. A phase locked loop is responsive to the modulated signal. The phase locked loop includes a controlled oscillator having a controlled oscillator input. An amplifier includes a signal input, amplitude control input and an output. The signal input is responsive to the controlled oscillator output and the amplitude control input is responsive to the amplitude signal. The phase locked loop that is responsive to the modulated signal includes a controlled oscillator output and a feedback loop between the controlled oscillator input and the controlled oscillator output. The feedback loop includes a mixer that is responsive to a local oscillator. The modulator may be placed in the phase locked loop.

Abstract: Method and system are disclosed for automated calibration of the VCO gain in phase modulators. The method and system of the invention comprises synthesizing, in a phase modulator, a signal having a given output frequency using a controlled oscillator having a frequency control input, a modulation input, and a feedback loop. A frequency control signal is applied to the frequency control input, and gain variation of the controlled oscillator is compensated for outside of the feedback loop via the modulation input. The method and system of the invention may be employed in any telecommunication system that uses phase and amplitude modulation, including EDGE and WCDMA systems.

Abstract: There is provided a VCO having a modulation function capable of easily constituting a correction circuit which can obtain a predetermined modulation degree even when element irregularities are present. A modulation current terminal is connected to an anode side connection point of a first and a second varactor diode. A first resistor is connected between the connection point and an anode side connection point (grounding voltage) of a third and a fourth varactor diode. Voltage deciding the oscillation frequency is input from the voltage input terminal via the second resistor to the cathode side connection point of the first and the third varactor diode and via the third resistor to the cathode side connection point of the second and the fourth varactor diode. A first and a second capacitor are connected from a power source via a first and a second inductor to the cathode side of the first and the second varactor diode.

Abstract: The present invention provides a communication semiconductor integrated circuit wherein a first control voltage for a voltage-controlled oscillator circuit is controlled based on a feedback signal sent from a PLL loop to generate a carrier frequency signal used as a carrier, and under the generation of the carrier frequency signal, a second control voltage for the voltage-controlled oscillator circuit is controlled based on the output of a DA converter circuit for DA-converting a code generated based on transmit data to thereby frequency-modulate an oscillation signal. The communication semiconductor integrated circuit is provided with a frequency adjustment/control circuit which measures the frequency of an oscillation output of the voltage-controlled oscillator circuit and adjusts a reference current value of the DA converter circuit according to the difference between the measured value and a target value to thereby correct the frequency.

Abstract: A gain compensation technique for a fractional-N phase lock loop includes locking a reference signal with the N divider feedback signal in a phase lock loop including a phase detector, charge pump, loop filter and voltage control oscillator with an N divider in its feedback loop; driving the N divider with a sigma delta modulator including at least one integrator to obtain a predetermined fractional-N feedback signal; and commanding a scaling in phase lock loop gain by a predetermined factor and synchronously inversely scaling by that factor the contents of at least one of the integrators.

Abstract: A direct frequency modulation apparatus modulates frequency by applying a transmission data-dependent voltage to the control terminal of a voltage-controlled oscillator without the mediacy of a phased-locked loop. The direct frequency modulation apparatus is set such that the temperature dependencies of a terminal voltage in PLL locking and a modulation voltage in an open state correspond to that of a varicap diode.

Abstract: A translational-loop transmitter generates RF signals using at most one phase-locked-loop (PLL) circuit. In one embodiment, a single PLL generates two local oscillation signals. The first oscillation signal is mixed with a baseband signal to generate an intermediate frequency signal. The second oscillation signal is input into the translational loop to adjust a voltage-controlled oscillator to the desired carrier frequency. In order to perform this type of modulation, the frequencies of the local oscillation signals are set so that they are harmonically related to one another relative to the carrier frequency. Other embodiments generate only one oscillation signal. Under these conditions, the intermediate frequency signal is generated using the oscillation signal, and a frequency divider in the translational loop is used to generate a control signal for adjusting the voltage-controlled oscillator to the carrier frequency.

Abstract: A fractional-N frequency synthesizer using the first order Delta-Sigma frequency discriminator which is composed of only a dual modulus frequency divider and a D flip-flop is used to replace the function of phase detector is disclosed. The invented structure is characterized by generating the feedback error signal indirectly from the output bit stream of said discriminator in such a way that the quantization noise contained in the bit stream is maximally canceled by comparing it with another bit stream generated by an accumulator digitally performing the first order Delta-Sigma modulation to the required fractional number, so that there is almost no discrete fractional spurs in the output spectrum of the synthesizer. Most other circuit of the synthesizer could be formed digitally so that high integration level and low noise performance could be achieved. Narrow or wideband phase or frequency modulation could also be conveniently added digitally with good accuracy.

Abstract: In the case of a trimming method for a PLL circuit operating based on the principle of a two-point modulation, the PLL circuit is locked without any modulation being impressed and then an analog and a digital modulation signal are impressed into the locked PLL circuit. A signal that is characteristic of the PLL control error is tapped from the PLL circuit, and the modulation swing in the analog modulation signal is changed such that the characteristic signal has the same value as before the analog and digital modulation signals were impressed.

Abstract: A correction circuit for a voltage-controlled oscillator (VCO) is arranged outwardly of the voltage-controlled oscillator. The oscillation of the selected frequency and the frequency modulation are carried out independently of each other. The correction circuit includes a frequency selection controller generating a frequency selection signal of the DC potential, and a frequency modulation controller generating a modulation adjusting signal responsive to the input of a modulating signal. When a frequency modulation control signal, including the DC potential of the frequency selection signal and the modulation adjusting signal, is supplied to the voltage-controlled oscillator, the capacitance is lowered even if the frequency is increased, thus allowing the modulation degree to frequency to be decreased to a substantially constant level.

Abstract: A digitally controlled circuit for reducing the phase modulation of a signal. The circuit has a multiphase clock generator that produces n phases of a clock that is m-times the signal. The circuit further has a multiplexer with n inputs for the n phases of the clock and with one output which supplies the output signal. The output signal and the signal are connected to the inputs of a phase comparator. The output signal of the comparator is supplied to a sigma-delta modulator whose output signals are used for controlling the multiplexer. A jittered input signal is compared in the phase comparator with a master clock. The determined phase difference is integrated in a sigma-delta modulator. The aim of the circuit is to generate a clock without jitter, digitally and without using external components. This circuit provides 20 dB/decade attenuation of the jitter received in the SYNC signal, based on the P-regulator characteristic.

Abstract: A sigma-delta programmer is supplied with a data word having a word length of N bits. The most significant L bits of the data word represent the places before the decimal point, and the remaining N−L less significant bits represent the places after the decimal point in the data word. A sigma-delta modulator is supplied with the N−L+1 less significant bits of the data word. An adder receives the L−1 most significant bits of the data word and a data word that is output by the sigma-delta modulator, and outputs a signal, which is multiplied by the value two by a multiplier.

Abstract: Direct frequency modulation of a phase-locked loop (PLL) output signal is achieved by means of a modulation signal comprising a digital sequence. The digital modulation signal is coupled to the input of the VCO of the PLL, and is also coupled to drive an up-down counter. The output of the counter is coupled to a D/A converter to provide a compensation signal for the PLL. When the counter output reaches values representing modulation-induced phase errors of +360 degrees and −360 degrees, the counter generates signals respectively corresponding thereto to adjust the PLL frequency divider.

Abstract: In generating a frequency-modulated clock, a first frequency modulation (FM) signal having frequency fm1 is frequency-modulated by a second FM signal having a second frequency fm2, generating a clock modulation signal fm0. The clock generation signal fm0 is used to frequency-modulate the system clock CLK by the clock modulation signal fm0. Thus, the spectrum of the clock is doubly dispersed by the first and the second FM frequencies. As a result, peak levels at the fundamental and higher harmonic frequencies are reduced as compared with conventional clock generation device.

Abstract: A modulator according to the invention includes: a PLL circuit that detects a phase difference between an input signal and a reference signal, an AGC circuit that controls a gain of a modulating signal and outputs a control signal, and a voltage controlled oscillation circuit that controls an oscillation frequency of a signal outputted from the PLL circuit on the basis of the control signal. Here, the voltage controlled oscillation circuit includes: a first voltage controlled reactance unit that inputs the signal outputted from the PLL circuit, a second voltage controlled reactance unit that inputs the control signal, and a high-frequency oscillation circuit connected in parallel with the first and second voltage controlled reactance units, which outputs the input signal. Thereby, the invention achieves to provide a modulator capable of compensating the deviation of the modulation factor, even when the frequency of the carrier signal varies.

Abstract: A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.

Abstract: A circuit for generating a pulse-width-modulated signal comprises a phase-locked loop (PLL) having a duty-cycle-insensitive phase comparator and a Sigma-Delta pulse width modulation circuit suitable for providing the voltage-controlled oscillator function of the PLL. Thereby, frequency of the signal generated is synchronized by the PLL to the specified frequency of a synchronization signal, and is thus independent of the duty cycle.

Abstract: A frequency sythesizer and a method for synthesizing a signal having a given output frequency includes providing a controlled oscillator having a frequency control input and a feedback loop, applying a frequency control signal to the frequency control input, and compensating gain variation of the controlled oscillator outside of the feedback loop.

Abstract: Phase-locked loop methods and structures are provided for generating modulated communication signals with nonconstant envelopes. These methods and structures realize the improved communication performance of nonconstant-envelope modulations with the upconversion advantages of phase-locked loops. The structures include transmitters in which a phase-locked loop is augmented with first and second feedforward paths that substantially restore phase and amplitude information to a transmit signal that is generated by a voltage-controlled oscillator of the phase-locked loop. The first feedforward path is configured to realize a path transfer function of s/Kv wherein the voltage-controlled oscillator has a transfer function of Kv/s. The second feedforward path extracts an envelope-correction signal from the modulated intermediate-frequency signal and a variable-gain output amplifier amplifies the transmit signal with a gain that responds to the envelope-correction signal.

Abstract: An apparatus for generating a modulated signal which includes a modulator operative for receiving a first signal and input data signals, and modulating the first signal in accordance with the input data signals so as to produce a modulated reference signal; a first frequency divider coupled to the modulator output, operative to reduce the frequency of the modulated reference signal by a predetermined factor; a signal generator operative to produce a second signal; a first mixer having a first input coupled to an output of the first frequency divider and a second input coupled to the output of the signal generator. The first mixer operates to frequency translate the modulated reference signal by an amount equal to the frequency of the second signal. In addition, the signal generator of the present invention contains a direct digital synthesizer coupled to a second phase lock loop which operates to up-convert the output signal of the DDS to the microwave region.

Abstract: A phase modulator for direct wideband linear phase modulation of a microwave continuous wave carrier signal which is suitable for many analog and digital phase or frequency modulation techniques. Linear phase modulation range in excess of 360 degrees is provided as a result of linear variation in the modulating signal. A conditioned baseband modulating signal is injected into a highly linear fractional range phase shifter, operating at a subharmonic of the desired output frequency. A nonlinear circuit is used to perform frequency and instantaneous phase multiplication, thus expanding the linear phase modulation range to greater than 360 degrees at the desired output frequency. With special conditioning of the baseband modulating signal, the phase modulator can be made frequency agile in ultra-small frequency steps, without requiring a stable, frequency agile reference signal or frequency synthesizer.

Abstract: A method for generating a plurality of frequencies having predetermined frequency deviations from a phase lock loop device including a VCO having a main voltage input, a modulation voltage input and a frequency output, a first and second feedback loop digital divider, each having an input and an output, a phase frequency detector having a first and second input and an output, a reference frequency generator such as a crystal oscillator having an output, a first and second reference frequency digital divider, each having an input and an output, a loop filter having an input and an output, a switch having an input and a first and a second switched output, a hold circuit having an input and an output, a memory circuit for storing the a lock voltage and the corresponding loop output frequency, the steps including; setting a first initial predetermined value of the first feedback loop digital divider, connecting a switch output to the main input of the VCO, supplying a first predetermined reference frequency to th

Abstract: An optoelectronic phase locked loop for clock recovery in high-speed optical time division multiplexed systems. The optoelectronic phase locked loop includes a balanced photodetector through which the polarity ambiguity in error signal is resolved and the cancellation of laser noise enabling clock recovery with low timing jitter. The optoelectronic phase locked loop also includes an electroabsorption modulator as a phase detector, a lowpass filter, a variable controlled oscillator, a power divider and an amplifer.

Abstract: PLL frequency synthesizers and their calibration techniques are described. The PLL frequency synthesizers are used to generate digital modulation of a carrier signal. A digital frequency divider in the feedback path of the loop has its division ratio controlled by a digital &Dgr;-&Sgr; modulator. The modulation of the carrier is achieved by applying a modulation signal to the input of the &Dgr;-&Sgr; modulator and to the input of the voltage-controlled oscillator of the PLL. The high frequency path and low frequency path of the modulation signal must be adjusted with respect to one another in order to obtain a good modulation. As the low frequency path can be accurately set, the calibration is performed only on the high frequency path. Digital calibration techniques for the high frequency path are described.

Abstract: Direct frequency modulation of a phase-locked loop (PLL) output signal is achieved by means of a modulation signal comprising a digital sequence. The digital modulation signal is coupled to the input of the VCO of the PLL, and is also coupled to drive an up-down counter. The output of the counter is coupled to a D/A converter to provide a compensation signal for the PLL. When the counter output reaches values representing modulation-induced phase errors of +360 degrees and −360 degrees, the counter generates signals respectively corresponding thereto to adjust the PLL frequency divider.

Abstract: A frequency modulator having variable carrier frequency is provided. A VCO frequency-modulates an oscillator input signal using an oscillation frequency set by a set signal as the carrier frequency. A phase/frequency detector outputs phase and frequency differences between a VCO output signal and a reference signal. A filter receives a phase/frequency detector output and generates the set signal. An amplifier generates a pair of output signals whose voltage levels change in opposite directions. A compensation circuit changes the voltage levels of the output signal pair and provides resulting signals to the VCO as the oscillator input signal.

Abstract: The proposed phase lock technique uses various feedback loops to lock the frequency and phase of a CATV modulator output signal to that of an off-air signal without directly measuring the output frequency. One embodiment includes a tuner for receiving the off-air signal and generating an intermediate frequency signal and a phase-frequency detector for comparing the frequency and phase of the intermediate frequency signal generated by the tuner with the frequency and phase of an intermediate frequency signal generated by the modulator based on a reference input signal. The output of the phase-frequency detector is used to control the reference input signal into the modulator and the reference input signal to the tuner such that the frequency and phase of the modulator output signal is locked to the frequency and phase of the received off-air signal.

Abstract: A dual-mode wireless telephone which is capable of operating on two different bands of frequencies. The dual-mode telephone having a single phase lock loop combined with a single local oscillator that can select between two frequencies in two widely spread output frequency bands such as the bands in the GSM and DCS standards. A switch in the phase lock loop selectively swaps an UP signal and a DOWN signal to achieve either a high side lock or a low side lock. When the phase lock loop is high side locked, a target frequency in a higher band of output frequencies is generated. When the phase lock loop is low side locked, a target frequency in a lower band of output frequencies is generated.

Abstract: A digital signal processor generates in-phase, quadrature-phase and amplitude signals from a baseband signal. A modulator modulates the in-phase and quadrature-phase signals to produce a modulated signal. A phase locked loop is responsive to the modulated signal. The phase locked loop includes a controlled oscillator having a controlled oscillator input. An amplifier includes a signal input, amplitude control input and an output. The signal input is responsive to the controlled oscillator output and the amplitude control input is responsive to the amplitude signal. The phase locked loop that is responsive to the modulated signal includes a controlled oscillator output and a feedback loop between the controlled oscillator input and the controlled oscillator output. The feedback loop includes a mixer that is responsive to a local oscillator. The modulator may be placed in the phase locked loop.

Abstract: A frequency shift modulation circuit has a direct digital synthesizer DDS and a phase-locked loop PLL. DDS stores output signal frequency data in a plurality of registers. DDS selects the register storing the frequency data in accordance with a frequency shift keying FSK data signal whose voltage was controlled by a comparator. A signal output from DDS is input to PLL. PLL generates a signal whose phase is synchronized with the signal supplied from DDS, and outputs a frequency shift signal having a shift amount corresponding to the digital value of the FSK data signal. The FSK data signal is input via a balance adjustor to PLL so that a large frequency shift is possible. Since the frequency data is set to DDS, a stable modulation even for a low frequency is possible. In this manner, the frequency of an output signal can be stably shifted.