Abstract: A frequency modulator having variable carrier frequency is provided. A VCO frequency-modulates an oscillator input signal using an oscillation frequency set by a set signal as the carrier frequency. A phase/frequency detector outputs phase and frequency differences between a VCO output signal and a reference signal. A filter receives a phase/frequency detector output and generates the set signal. An amplifier generates a pair of output signals whose voltage levels change in opposite directions. A compensation circuit changes the voltage levels of the output signal pair and provides resulting signals to the VCO as the oscillator input signal.

Abstract: A VSAT system for generating and transmitting a modulated data signal to a satellite. The VSAT system includes an indoor unit for generating a modulated data signal having an envelope of constant amplitude, and an outdoor unit including a transmitter module operative to receive the modulated data signal and to frequency multiply and amplify the modulated data signal so as to produce a modulated carrier signal having an envelope of constant amplitude. The transmitter module includes a multiplier operative to frequency multiply the modulated data signal to the frequency of the modulated carrier signal, and a power amplifier operated in the saturation mode, which amplifies the modulated carrier signal to the desired power level. The components constituting the transmitter module are formed on a single integrated circuit.

Abstract: An apparatus for generating a modulated signal which includes a modulator operative for receiving a first signal and input data signals, and modulating the first signal in accordance with the input data signals so as to produce a modulated reference signal; a first frequency divider coupled to the modulator output, operative to reduce the frequency of the modulated reference signal by a predetermined factor; a signal generator operative to produce a second signal; a first mixer having a first input coupled to an output of the first frequency divider and a second input coupled to the output of the signal generator. The first mixer operates to frequency translate the modulated reference signal by an amount equal to the frequency of the second signal. In addition, the signal generator of the present invention contains a direct digital synthesizer coupled to a second phase lock loop which operates to up-convert the output signal of the DDS to the microwave region.

Abstract: The invention discloses an apparatus and method for reducing frequency pulling. Further, the invention provides amplitude modulation techniques to eliminate spurious signals and injection locking of the VCO to the output transmitted carrier. The architecture includes at least one synthesizer, a plurality of frequency dividers, an output VCO, a low pass filter, a mixer, a pretransmission filter and an amplifier connected in a manner to generate an output frequency which is non-harmonically related to the synthesizer VCO and to maintain the magnitude of the output frequency at, preferably, exactly 1.5 times higher than the VCO frequency.

Abstract: A pulse density modulator for performing a modulation process by changing a pulse density per unit time. The pulse density modulator includes a counting circuit for counting supplied clock signals, a first waveform data generating circuit for synthesizing count data outputted from the counting circuit to generate basic waveform data, a second waveform data generating circuit for synthesizing the basic waveform data outputted from the first waveform data generating circuit to generate pulse density modulated waveform data corresponding to digital data supplied externally, a clock correction signal generating circuit for generating a clock correction signal indicating the phase of an unequal cycle component included in the clock signals, and a waveform data correcting circuit for correcting the pulse density modulated waveform data based on the clock correction signal.

Abstract: The present invention relates to a frequency synthesizer for generating an output signal (So) the frequency of which has a non-integer, fractional relationship of value Nn/Nd, where Nn and Nd are integer numbers, with respect to a frequency (fr) of an input signal (Sr). The synthesizer is characterized in that it comprises a device for multiplying by M, where M is an integer number, the frequency of the input signal in order to produce a high frequency intermediate signal (Si), and a device for dividing the frequency of this intermediate signal by (M×Nd)/Nn in order to generate the output signal (So).

Abstract: A frequency synthesizer with a digital frequency lock loop (FLL) having a fast frequency lock time uses a frequency counter circuit in the feedback loop to count the output signal frequency and produce frequency count data. A modulation control circuit provides modulation data and a corresponding modulation control signal for modulating the FLL signal source. A microprocessor processes the frequency count data along with the modulation data to provide a frequency control signal for controlling the nominal, or center, frequency of the FLL signal source. By processing these data together, thereby accounting for the amount of modulation applied to the FLL signal source, the center frequency can be maintained more consistently notwithstanding the presence of modulation within the feedback loop signal.

Abstract: This device includes a frequency synthesizer (12) comprising two phase-locked loops (L1 and L2). The one comprises a low-pass filter (68) and the other a high-pass filter (49). The loop with the low-pass filter fixes the basic frequency of the synthesizer and the other corrects the phase noise. With this arrangement it is easy to apply a modulation frequency to the terminal (11) that is not disturbed by said loops if this modulation frequency is found to be higher than the cut-off frequency of the low-pass filter.

Abstract: A frequency shift keying device includes a reference oscillator which provides a reference signal, and a controlled oscillator having a control input and an output signal. A phase detector compares the output phase of the output signal with a reference phase of the reference signal to form an error signal on a detector output of the phase detector. The error signal provides phase locking of the output signal. A compensation circuit having a compensation input is connected to a modulation output of a modulation source which outputs a modulation signal. The compensation circuit also has a compensation output connected to the detector output. The compensation circuit provides a compensation signal which counteracts the error signal to form a modified error signal for attenuating the phase locking so that it becomes possible to modulate the controlled oscillator at a low rate without disturbing the sound spectrum which is also transmitted using a carrier generated by the controlled oscillator.

Abstract: In accordance with the present invention, a frequency modulating phase-locked-loop (FMPLL) (100) architecture is implemented. The frequency of the FMPLL (100) is controlled using a current controlled oscillator (ICO) (126). The ICO (126) receives a current signal incorporating feedback to maintain a fixed gain. The ICO (126) associated with the FMPLL (100) establishes a predictable change in the output frequency for a given change in its input controlled current (ICTL). Relying upon this fixed gain, a frequency shift can be created by summing in an additional delta current (IMOD) to the input control current. By periodically varying the magnitude of the current IMOD, a frequency modulated clock is produced at the output of the ICO 126. The magnitude of IMOD controls the amount of frequency shift of the frequency modulated clock. By providing an IMOD signal which is proportional to the generated system frequency, a frequency shift proportional to the average, or center, frequency is produced.

Abstract: A phase-locked loop applied as a phase modulator using an external analog control signal whereby a single-ended pulse-width modulated digital signal may be derived from the phase detector output, and two phase modulated square-wave digital signals may be derived from a reference oscillator and the feedback voltage controlled oscillator. The pulse width modulation and/or phase modulation in power applications can be achieved with far greater speed, precision, simplicity and economy than by existing techniques.

Abstract: A circuit for generating a modulated signal contains a reference oscillator for generating a reference signal, a digital synthesis circuit having a clock input and an addition value input for generating a synthesis signal, and a phase comparator for generating a tuning signal depending on the result of a comparison of the phase of the reference signal with the phase of the synthesis signal. An oscillator is provided, which is controlled in a manner dependent on the tuning signal and serves for generating the modulated signal and a further oscillator signal, from which a clock signal present at the clock input of the digital synthesis circuit can be derived. The circuit has a drive device, which generates a digital drive signal from carrier frequency and modulation signals. The drive signal being present at the addition value input of the digital synthesis circuit.

Abstract: A direct modulation phase lock loop (PLL) a voltage controlled oscillator (VCO) (114). A divider (118) has a first divider input coupled to the VCO and a second divider input to receive a modulation inducing divisor sequence. A phase detector (102) has a first detector input coupled to the divider to receive the output thereof, and a second detector input to receive a reference input. A tuning circuit (306, 406) is coupled to the phase detector and the VCO, the tuning circuit responsive to a variable DC reference potential such that the tuning circuit has a frequency response that is constant over the modulation bandwidth whereby the PLL is a type 1 PLL with low modulation distortion.

Abstract: A transmitter in which a complex low IF digitised signal is applied in quadrature to a complex phase comparator together with a digitised frequency down-converted version of an analogue signal produced by a transmitter VCO. The low IF digitised signal serves as a reference against which the digitised frequency down-converted version of the transmitter VCO is compared. The output of the complex phase comparator is converted to an analogue signal which is applied as a control signal to the transmitter VCO. An analogue embodiment of the transmitter which uses zero-IF signals is also disclosed.

Abstract: The purpose of the present invention is to provide a frequency synthesizer which does not have spurious components. Automatic reference correcting circuit 4 is provided to frequency synthesizer 1 which changes the frequency division value of the divider and makes the frequency of external output signal (OUT) into a value equal to the frequency of the reference clock signal multiplied by the average frequency division value, charge pump circuit 35 measures the ripple component contained in the output control signal, and ripple correcting circuit 39 forms compensation current, which is superimposed on the control signal in order to minimize the ripple component. If composed for control circuit 55 to obtain the optimum compensation current and output to ripple correcting circuit 39 while negative feedback which minimizes the ripple component is being formed, output signal (OUT) which does not have spurious components can be obtained.

Abstract: An apparatus for generating a modulated signal which includes a modulator operative for receiving a first signal and input data signals, and modulating the first signal in accordance with the input data signals so as to produce a modulated reference signal; a first frequency divider coupled to the modulator output, operative to reduce the frequency of the modulated reference signal by a predetermined factor; a signal generator operative to produce a second signal; a first mixer having a first input coupled to an output of the first frequency divider and a second input coupled to the output of the signal generator. The first mixer operates to frequency translate the modulated reference signal by an amount equal to the frequency of the second signal. In addition, the signal generator of the present invention contains a direct digital synthesizer coupled to a second phase lock loop which operates to up-convert the output signal of the DDS to the microwave region.

Abstract: A sequence generator 10 for a frequency synthesiser 1,2,3,4,5,10 forming part of a direct modulator comprises an input 10a for receiving an input multibit signal X(z), an output 10c for outputting an output digital signal Y(z) and sequence generation means 10b. The sequence generation means is adapted to produce a noise transfer function which has a minimum value both at the frequency corresponding to the dc component of the input signal and at one or more frequencies away from the frequency corresponding to the dc component of the input signal.

Abstract: Given a target frequency (F.sub.VE), a reference frequency (F.sub.R), an error limit (E.sub.L), and a first divider range (150), a first (R) and a second (N) integer divider value are computed. First, an initial first divider (R) is selected (152). Then, a second divider (N) is computed as equal to the target frequency (F.sub.VE) divided by the reference frequency (F.sub.R) multiplied times the selected first divider (154). Then an error term (E) is computed to quantify the error introduced by using integers as dividers (156). The divider terms are accepted (166) if the error term is less than the error limit (158). Otherwise, a new first integer divider (R) is selected (160), repeating the computation of the second (N) divider (154), the computation of the error (E) term (156), and the test of the error term (E) against a limit as a loop (158). This loop is repeated until either the error term (E) is less than the error (E.sub.

Abstract: In a method and an arrangement for frequency modulation of a high-frequency signal, where the high-frequency signal is generated with an oscillator which is controlled by comparison of an actual frequency signal with a variable set frequency signal, the actual frequency signal contains pulses with an average repetition frequency which corresponds to an actual frequency, with one pulse being derived from one edge of the high-frequency signal and its phase angle being determined by a predetermined clock pulse. The set frequency signal comprises pulses with an average repetition frequency which corresponds to a set frequency. The pulses increment or decrement an up/down counter from whose count a control voltage is derived for the oscillator.

Abstract: An apparatus transmits RF signals in two widely separated frequency bands. The RF signals in the two frequency bands have the same modulated bandwidth. The apparatus utilizes substantially the same radio communication apparatus structure as in a radio communication apparatus designed for only one frequency band. RF signals for one frequency band are obtained when a first frequency multiplier is connected, generating RF signals by multiplying VCO signals from a VCO by a factor k. The RF signals for the other frequency band are obtained from the VCO when the first frequency multiplier is not connected. When the first frequency multiplier is connected, the modulated bandwidth of the VCO signals will multiplied by the factor k. This is compensated in a phase locked loop by connecting a second frequency multiplier, having the same multiplication factor k, at the same time as the first multiplier is connected.

Abstract: A transmitter and a phase locked loop (30) for a transmitter are disclosed. The phase locked loop (30) upconverts the frequency of a baseband signal to a frequency for radio transmission. As well as the usual components, the phase locked loop (30) comprises a modulator (39) for modulating a baseband signal (f.sub.bb) onto a carrier (f.sub.ref /R) and forwarding the resultant modulated signal (f.sub.c) to one of the inputs of the phase detector (33). It also comprises a low pass filter (38) in its forward path between the phase detector (33) and the voltage controlled oscillator (34) for passing signals having baseband signal frequencies. A mixer (35) and main frequency divider (36) are provided in the feedback path to downconvert the transmit signal (f.sub.tx). This low division eliminates large amounts of multiplicative noise within the loop bandwidth, and therefore enables a large loop bandwidth to be used. Consequently, the settling time of the phase locked loop is improved.

Abstract: A method and apparatus are provided for modulating a frequency synthesizer with an adjusted frequency control word determined by adjusting a carrier frequency control word based upon a bit content of a unsigned modulation control word. The method includes the steps of inverting a most significant bit of the unsigned modulation control word to produce an adjusted modulation control word and replicating the inverted most significant bit and appending the replicated bits to a most significant bit side of the adjusted modulation control word to increase a width of the adjusted modulation control word to a width of the carrier frequency control word. The method further includes the step of adjusting the carrier frequency control word by adding the replicated bits and the adjusted modulation control word to corresponding bits of the carrier frequency control word.

Abstract: A .SIGMA..DELTA. modulator-controlled, phase-locked-loop circuit, and an associated method, generates a frequency-regulated signal which does not exhibit undesired tones. Dithering signals are generated and are provided to a .SIGMA..DELTA. modulator. The .SIGMA..DELTA. modulator forms a division-factor control signal used to control the division factor of a frequency divider forming a portion of the PLL circuit. The dithering signals applied to the .SIGMA..DELTA. modulator reduce the likelihood that the .SIGMA..DELTA. modulator shall enter a limit cycle and generate repetitive output signals.

Abstract: Apparatus for generating the family of PSK (phase shift keyed) modulations, which include BPSK (binary PSK), QPSK (quaternary PSK), MSK (minimum shift keying) and the like. The carrier is generated with the desired digital information already phase-modulated onto it by directly introducing a phase shift or delay onto the error path of a phase-locked loop. causing the phase-locked loop to create the phase modulation. The [proposed scheme differs from common practice approaches, which are usually implemented by linear synthesis (an AM technique); rather, it] invention employs direct nonlinear synthesis (an FM technique). The invention [yields good phase precision with arbitrary spectral shaping under the constraint of constant envelope signaling. It] permits the connection of the output of a simple, inexpensive VCO (voltage controlled oscillator) directly to a system's antenna without the need for intervening circuit elements such as phase splitters, mixers, and the like which is applicable to [.

Abstract: An apparatus is disclosed for processing an input signal. The apparatus includes two feedback loops for generating output signal components from the input signal. Each loop contains an oscillator, which has a frequency or phase which is variable in response to a control signal, and a comparator for generating the control signal. The oscillator generates a loop output signal which forms one of the components of the output signal. The apparatus also includes a combiner for combining the loop output signals to produce the output signal. For each loop, the apparatus also produces a feedback loop operating signal, these signals being dependent on the output signal and in phase quadrature with one another. One input of the comparator in each loop receives the feedback loop operating signal, and the other input of the comparator receives a component of the input signal.

Abstract: A programmable apparatus is disclosed for generating a frequency modulated signal at a selected center frequency in accordance with digital data of at least first and second data levels. The modulating apparatus comprises a modulator having an input and an output and is responsive to an input modulation signal applied to its input for generating at its output the frequency modulated signal at a center frequency dependent on a quiescent voltage appearing at its input. A circuit is provided for sampling and storing a value of the quiescent voltage. An addressable memory stores a plurality of offsets. A programmable adding circuit adds a downloaded offset voltage to the stored value of the quiescent voltage to output a high modulation voltage. A programmable subtracting circuit subtracts a downloaded offset voltage from the stored value of the quiescent voltage to provide a low modulation voltage.

Abstract: A phase-locked loop frequency synthesizer system is provided using fractional frequency division and a fractional control number for phase modulating an output of the frequency synthesizer using an incoming information signal. The apparatus includes a delta-sigma converter which adjusts a divisor of the frequency divider by operating upon a magnitude modulated fractional frequency control number. The system further includes a differentiator which provides the magnitude modulated input stream to the delta-sigma modulator by modulating the fractional control number with detected differences in the incoming information signal.

Abstract: A mechanism for reducing a frequency transient appearing at the output of a voltage controlled oscillator (VCO) in a frequency synthesizer when a load is connected to the VCO. In accordance with the present invention, the magnitude and direction of (a) the frequency transient and (b) the frequency deviation of the VCO signal in response to a reference input voltage may be measured, and those measurements used to generate a frequency correction voltage which would cause the VCO signal to deviate in an equal amplitude but in an opposite direction to the frequency transient. The frequency correction voltage then can be applied to the VCO when it is connected to the load so as to substantially cancel the frequency transient.

Abstract: A wideband phase-lock loop frequency synthesizer (200) used in a radio transceiver capable of being reconfigured to operate in either a transmit, receive, or battery save mode. The wideband phase-lock loop frequency synthesizer (200) includes, a divide-by-two divider (205), quadrature detector (204), offset VCO (209) and offset mixer (207) for generating a quadrature phase modulated signal. Moreover, a programmable filter (211) is used for removing predetermined harmonic components of the offset mixed signal enabling the synthesizer to operate over a wide frequency range.

Abstract: The output of a voltage-controlled oscillator (VCO), after being passed through a resonator having a single-peak characteristic, is detected by a detector. The output of the detector is sampled and held at a time instant that the control input voltage to the VCO reaches a maximum and also at a time instant that it reaches a minimum, and the difference between them is fed back to the control input of the VCO. In this way, the center frequency of the VCO is controlled so that it becomes equal to the center frequency of the resonator. In the case of a VCO as an FM modulator in an FM-CW radar, the sample-and-hold timing is derived from a clock signal based on which a triangle wave is generated. In the case of a VCO as an FSK modulator, the sample-and-hold timing is obtained by detecting a 0 and a 1 in input data.

Abstract: A frequency synthesizer includes a controlled oscillator which is responsive to a frequency control input signal, to generate an output frequency. A programmable frequency divider is responsive to the output frequency and to a divider control input, to divide the output frequency by a first integral ratio or by a second integral ratio in response to the divider control input, to thereby produce a divided signal. A phase comparator is responsive to a reference frequency signal and to the divided signal, to compare the reference frequency signal and the divided signal, and thereby produce a first error signal. A sigma-delta modulator is responsive to a modulation input to produce the divider control input. A loop filter is responsive to the first error signal, to thereby produce the frequency control input signal. Ripple compensation signals and direct modulation signals may also be provided, to provide a three-point modulator for a frequency synthesizer. Analog and digital embodiments may also be provided.

Abstract: An improvement on the phase-locked loop (PLL) circuit, in which an amplifier is disposed at the modulating signal input end of the PLL, and the output end of the amplifier is connected in series to a resistor and an inductor, followed by a resistor connected to a higher DC bias as well as a variable capacitance diode connected to ground. In such a way, the variable capacitance diode is under the higher bias and thus has a smaller capacitance change, while having its Q-value property opposite to the resonance curve formed by the crystal unit of an oscillator which is associated in parallel with the variable capacitance diode, thereby forming in a good compensation for the linearity of the circuit architecture and achieving an ideal frequency deviation and a reduced distortion caused by the modulation.

Abstract: A Gaussian Minimum Shift Keying modulator that provides direct modulation of a carrier signal, produced by a single microwave high power voltage controlled oscillator. A continuous phase frequency shift keyed modulated signal with a modulation index of 0.5 is produced at the desired output frequency using a full 360 degree linear continuous phase modulator, controlled by a linear baseband signal that is the integral of the binary baseband information signal. This modulated signal is used as the reference signal for a phase locked high power voltage controlled oscillator. The phase locked loop provides frequency tracking and Gaussian spectral shaping to the modulated output signal.

Abstract: A first phase-locked loop (PLL) includes a first integrated voltage-controlled oscillator (VCO) whose output signal has a frequency modulated by an input signal of the device about a multiple of a reference frequency. A second PLL includes a second integrated VCO and frequency transposition means. The transposition circuit receive the output signal of the second VCO and a transposition signal having a non-modulated frequency. The second PLL addresses to the second VCO a control signal capable of aligning the frequency of the output signal of the transposition circuit with the frequency of the first VCO. The output signal of the second VCO forms the frequency modulation transmission signal produced by the device.

Abstract: A selective call receiver (100) for receiving and transmitting paging signals has a transceiver (104) having an integer divide synthesizer (105) for achieving a fast lock time. The transceiver (104) has a reference oscillator (202) that generates a reference signal in a direct injection path and a modulator (206) coupled in the direct injection path modulates the reference signal to generate a modulated reference signal. A phase locked offset loop (220) coupled to the direct injection path generates a low frequency signal derived from the reference signal, a multiplier (210) coupled to the modulator (206) multiplies the modulated reference signal, and a mixer (214) coupled to the multiplier (210) receives the modulated reference signal in the direct injection path and an output signal from the phase locked offset loop (220) to generate a first local oscillator output signal and a modulated transmit carrier.

Abstract: Spurious energy suppression for a data communication system is achieved without using a large order noise suppression filter, by means of a pre-mixer tracking filter incorporated into an emitter-coupled logic configured buffer of a carrier frequency generator, using a MOSFET-implemented current-controlled resistance component of a resistor-capacitor network and an associated current control stage. The MOSFET-implemented resistance components of the filter are controlled by the same control current that establishes the carrier generator's output frequency. As a result, the cut-off frequency of the tracking filter is linearly proportional to the carrier and effectively independent of process parameters.

Abstract: A highly efficient linear amplifier and/or modulator and demodulator comprising first and second feedback loops is provided. Each loop processes a component of the input signal and the component signals are recombined at, for example, a summing junction 18. The feedback signals for each loop are dependent upon the output signal and are in phase quadrature. The input signal is separated into I and Q signals, which are also in phase quadrature, by a component separator 10.

Abstract: An VCO generates a high-frequency signal based on a modulating signal and a phase-locking control signal. A first distributor separates the high-frequency signal into two parts, one of which is outputted as an oscillator output signal. An n-multiplier and a microwave amplifier for n-multiplication adjust the level of the reference signal while the frequency of it is multiplied by `n`. A second distributor separates the output from the microwave amplifier for n-multiplication into two parts, one of which is made to be a comparative signal, the other is made to be a locally oscillated signal. A frequency mixer and a microwave amplifier for frequency mixing produce an intermediate frequency signal using the other output from the first distributor and the locally generated signal. The phase comparator compares the intermediate frequency signal with the comparative signal to output an error signal. An LPF generates the phase-locking control signal by removing unwanted signals from the error signal.

Abstract: A frequency-locked loop (100) employs a controllable oscillator (102) for generating an output signal having a frequency, optional sampler (104), coupled to oscillator (102), for sampling the frequency of the output signal, a divider (106), coupled to optional sampling circuit (104), for dividing the output signal frequency to generate a prescaled signal and a microprocessor (108), coupled between the divider 106 and oscillator (102), for comparing the prescaled signal to a reference signal and generating a control signal for correcting frequency shifts based upon the comparison. The control signal generated by microprocessor (108) is non-continuous. During that time when microprocessor (108) generates no control signals, power is removed from various frequency-locked loop circuitry.

Abstract: The output frequency of a PLL frequency synthesizer and the output frequency of a fixed oscillator are mixed together in a mixer to produce sum and difference frequencies. The sum frequency is used as a local frequency, and the difference frequency is fed back to the PLL frequency synthesizer. In addition, the output frequency of the fixed oscillator is divided in a predetermined ratio to use it as a local frequency for the second or other subsequent frequency converting stage on the receiver or transmitter side.

Abstract: A VCO circuit has a voltage variable capacitance CVD2 connected in series with or in parallel to a condenser C3 connected in series with an inductance L1, which constitutes a resonator of the VCO circuit. An adjustment voltage VD2 is applied to a cathode of the voltage variable capacitance CVD2, such that the relation between a control voltage VD1 and an oscillation frequency f0 of the VCO circuit is electrically adjusted to improve the fabrication yield.

Abstract: In accordance with a loop open/close control signal, an analog switch closes or opens a loop including a voltage controlled oscillator, a variable frequency divider, a phase comparator, and a first loop filter, the analog switch, and a second loop filter. In order to reduce the change of frequency caused when the open loop state is set immediately after the output frequency is changed, the second loop filter uses a capacitor which shows properties of a small change of capacitance in response to an applied voltage and a small hysteresis. In another embodiment, the voltage controlled oscillator includes a second diode, one terminal of which is grounded, connected in reverses parallel to a first diode switch which switches the output oscillation frequency ranges of the voltage controlled oscillator.

Abstract: A frequency modulating system for frequency-modulating an input signal with a predetermined carrier frequency comprising a controller circuit and a frequency modulator is provided. The controller circuit includes an automatic frequency detecting circuit, a voltage controlled oscillator, an error current generator, a feedback clamping circuit, a deviation current generator, and an adder circuit generating a frequency deviation/carrier frequency correction signal provided to the frequency modulator. The frequency modulator modulates the frequency in response to an output of the controller circuit and includes an oscillator having the same structure as that of the voltage controlled oscillator.

Abstract: A radio frequency (RF) transceiver for modulating and demodulating RF signals with a direct modulation transmitter and a dual intermediate frequency (IF) receiver, respectively, includes a local oscillator, three frequency converters, a demodulator, a carrier generator, a modulator, a controller and two signal switches. The local oscillator (e.g. phase lock loop PLL!) provides a first local oscillator (LO) signal. One frequency converter (e.g. mixer) frequency converts an incoming modulated RF signal with the first LO signal to provide a first modulated IF signal. A second frequency converter frequency converts the first modulated IF signal with a second LO signal to provide a second modulated IF signal. The demodulator also receives the second LO signal and demodulates therewith the second modulated IF signal. The carrier generator (e.g. voltage-controlled oscillator VCO!) receives a transmitter control signal and in accordance therewith generates a transmitter carrier signal.

Abstract: A frequency modulating system for frequency-modulating an input signal with a predetermined carrier frequency comprising a controller circuit and a frequency modulator is provided. The controller circuit includes an automatic frequency detecting circuit, a voltage controlled oscillator, an error current generator, a feedback clamping circuit, a deviation current generator, and an adder circuit generating a frequency deviation/carrier frequency correction signal provided to the frequency modulator. The frequency modulator modulates the frequency in response to an output of the controller circuit and includes an oscillator having the same structure as that of the voltage controlled oscillator.

Abstract: A frequency modulating system for frequency-modulating an input signal with a predetermined carrier frequency comprising a controller circuit and a frequency modulator is provided. The controller circuit includes an automatic frequency detecting circuit, a voltage controlled oscillator, an error current generator, a feedback clamping circuit, a deviation current generator, and an adder circuit generating a frequency deviation/carrier frequency correction signal provided to the frequency modulator. The frequency modulator modulates the frequency in response to an output of the controller circuit and includes an oscillator having the same structure as that of the voltage controlled oscillator.

Abstract: A modulator for digital modulation is described to produce a modulated output from a voltage controlled oscillator in a phase locked loop during transmission of a random modulating input. The input voltage is applied to a coupling capacitor and when transmission ceases, the state of charge on the capacitor will not change because of a biasing circuit which comprises two resistors fed by a tri-state buffer which holds the input terminal of the capacitor at the average level between logic zero and logic one when no modulation is applied.

Abstract: A frequency synthesizer 10 having a digital to analog converter (DAC) 40 and a feedback system which detects the deviation of a frequency modulated signal and aligns the detected deviation. DAC 40 provides a presteering stimulus for alignment purposes. After presteering alignment, the gain of DAC 40 is accurately set for frequency deviation because modulation is sourced from the same digital to analog converter that performs presteering.

Abstract: An apparatus for generating output signals having predetermined frequency shifts relative to a frequency provided by a reference signal is included in a system (500) comprising a phase-locked loop (206) coupled to the reference signal for generating the first and second output signals. The apparatus comprises pulse addition circuitry (204) coupled to the reference signal and the phase-locked loop (206) for adding pulses to the reference signal at a first cyclical rate to generate the first output signal and for adding pulses to the reference signal at a second cyclical rate to generate the second output signal.

Abstract: A radio transmission and reception apparatus having a transmitting section and a receiving section for bidirectional data transmission between two end units in the time-division multiplex mode. Prior art radio transmission and reception apparatuses are equipped with a transmitting section and a receiving section that have separate PLL circuits for signal modulation and demodulation. The resultant expense for relatively expensive components can be considerably reduced in radio transmission and reception apparatuses if only one PLL circuit is provided in accordance with the invention, to which both the transmitting section and the receiving section have alternating access.