Abstract: A metal strip resistor is provided. The metal strip resistor includes a metal strip forming a resistive element and providing support for the metal strip resistor without use of a separate substrate. There are first and second opposite terminations overlaying the metal strip. There is plating on each of the first and second opposite terminations. There is also an insulating material overlaying the metal strip between the first and second opposite terminations. A method for forming a metal strip resistor wherein a metal strip provides support for the metal strip resistor without use of a separate substrate is provided. The method includes coating an insulative material to the metal strip, applying a lithographic process to form a conductive pattern overlaying the resistive material wherein the conductive pattern includes first and second opposite terminations, electroplating the conductive pattern, and adjusting resistance of the metal strip.

Abstract: There are provided a chip resistor and a method of manufacturing the same. The chip resistor includes a ceramic substrate; an adhesion portion formed on a surface of the ceramic substrate; and a resistor formed on the adhesion portion, wherein the adhesion portion includes at least one of copper (Cu), nickel (Ni), and copper-nickel (Cu—Ni).

Abstract: A manufacturing technique for constructing passive electronic components in vertical configurations is disclosed. Electrically passive components are constructed in a structure that is substantially perpendicular to target platform including a first plane to provide a larger electrode contact area and a smaller physical dimension. Passive components structured to be substantially perpendicular to a plane associated with a target platform can be directly connected to pad contacts of an integrated circuit or substrate or can be embedded in a package to reduce the area overhead of a passive component while improving the effectiveness of the passive components in their applications.

Abstract: The present disclosure relates to a thin film resistor that is formed on a substrate along with other semiconductor devices to form all or part of an electronic circuit. The thin film resistor includes a resistor segment that is formed over the substrate and a protective cap that is formed over the resistor segment. The protective cap is provided to keep at least a portion of the resistor segment from oxidizing during fabrication of the thin film resistor and other components that are provided on the semiconductor substrate. As such, no oxide layer is formed between the resistor segment and the protective cap. Contacts for the thin film resistor may be provided at various locations on the protective cap, and as such, are not provided solely over a portion of the resistor segment that is covered with an oxide layer.

Abstract: There is disclosed a honeycomb structure including a honeycomb structure section, and a pair of band-like electrode sections arranged on a side surface of the honeycomb structure section, an electrical resistivity of the honeycomb structure section is from 1 to 200 ?cm, in a cross section which is perpendicular to a cell extending direction, the one electrode section is disposed on an opposite side of the other electrode section via the center O, an angle which is 0.5 time as large as a central angle of the electrode section is from 15 to 65°, and each of the electrode sections is formed so as to become thinner from a center portion in a peripheral direction toward both ends in the peripheral direction, and in the cross section which is perpendicular to the extending direction of the cells, the whole outer peripheral shape is a round shape.

Abstract: A chip resistor includes an insulating substrate 11, top terminal electrodes 12 formed on top surface of the substrate using silver-based cermet, bottom electrodes 13, resistive element 14 that is situated between the top terminal electrodes 12 and overlaps them partially, an optional internal protective coating 15 that covers resistive element 14 completely or partially, an external protective coating 16 that covers completely the internal protection coating 15 and partially covers top terminal electrodes 12, a plated layer of nickel 17 that covers face sides of the substrate, top 12 and bottom 13 electrodes, and overlaps partially external protective coating 16, finishing plated layer 18 that covers nickel layer 17. The overlap of nickel layer 17 and external protective layer 16 possesses a sealing property because of metallization of the edges of external protective layer 16 prior to the nickel plating process.

Abstract: A micro heater includes a first electrode, a second electrode, a first carbon nanotube, and a second carbon nanotube. The first carbon nanotube extends from the first electrode. The second carbon nanotube branches from the second electrode. The first carbon nanotube and the second carbon nanotube intersect with each other to define a node therebetween.

Abstract: Provided may be a semiconductor resistance element including resistance patterns disposed on an insulating substrate. The substrate may have first and second planar surfaces disposed in a first direction, third and fourth planar surfaces at least between the first and second planar surfaces in a second direction and fifth and sixth planar surfaces at least between the first and second planar surfaces in a third direction. The semiconductor resistance element may include a first resistance pattern configured to cover a selected one of the first and second planar surfaces and a second resistance pattern on at least one of the third through sixth planar surfaces.

Abstract: An over-current protection device comprises a PTC material layer, first and second conductive layers, first and second electrodes, and four conductive vias. The first and second conductive layers are in physical contact with first and second surfaces of the PTC material layer, respectively. The first electrode contains a pair of first metal foils, and the second electrode contains a pair of second metal foils. The four conductive vias are formed at the corners each defined by two adjacent planar lateral surfaces. Two conductive vias connect the pair of the first metal foils and the first conductive layer, and the other two conductive vias connect the pair of the second metal foils and the second conductive layer. The ratio of the sum of the cross-sectional areas of the conductive vias to a form factor area of the device is in the range of 7% to 20%.

Abstract: An electrical multilayer component includes a base body with at least two external electrodes. The electrical multilayer component includes at least a first and a second internal electrode, which are each electrically conductively connected to a respective external electrode. The electrical multilayer component includes at least one ceramic varistor layer encompassing at least the first internal electrode. The electrical multilayer component includes at least one dielectric layer arranged between the at least one varistor layer and the second internal electrode. The dielectric layer has at least one opening, which can be filled with a gaseous medium.

Abstract: There is provided a chip resistor including a ceramic substrate; a first resistance layer formed on the ceramic substrate and including a first conductive metal and a first glass; and a second resistance layer formed on the first resistance layer, including a second conductive metal and a second glass, and having a smaller content of glass than the first resistance layer, thereby obtaining relatively low resistance and a relatively small temperature coefficient of resistance (TCR).

Abstract: A chip resistor device includes: a dielectric substrate that has top and bottom surfaces and two opposite edge faces interconnecting the top and bottom surfaces; two electrodes that are formed on two opposite sides of the dielectric substrate and that cover the edge faces and parts of the top and bottom surfaces; a resistor layer that is formed on one of the top and bottom surfaces of the dielectric substrate between the electrodes and that is brought into contact with the electrodes; and a heat conductive layer that is disposed on the resistor layer oppositely of the dielectric substrate and between the electrodes, that contacts the resistor layer and the two electrodes, and that has a higher resistance than that of the resistor layer. A method for making the chip resistor device is also disclosed.

Abstract: A co-fired multi-layer stack chip resistor is provided. The co-fired multi-layer stack chip resistor includes a ceramic substrate and a multi-layer stack resistance structure monomer. The ceramic substrate is formed by stacking multiple layers of the ceramic membranes, wherein the ceramic membranes is formed of a bearing membrane and a porcelain slurry with the solvent, the binder and the dispersant. The multi-layer stack resistance structure monomer is stacked on the ceramic substrate, and includes multiple bearing membranes and multiple resistive layers, wherein each resistive layer is formed on the surface of the corresponding bearing membrane, the resistive layers are parallel to each other, and the contiguous resistive layers are stacked with the interval of the predetermined distance along the vertical direction.

Abstract: A system for effectively defrosting a plastic window includes a transparent plastic panel, a heater grid having a plurality of grid lines that are integrally formed with the plastic panel, and equalizing means for equalizing the electrical current traveling through each of the grid lines.

Abstract: A co-fired multi-layer stack chip resistor is provided. The co-fired multi-layer stack chip resistor includes a ceramic substrate and a multi-layer stack resistance structure monomer. The ceramic substrate is formed by stacking multiple layers of the ceramic membranes, wherein the ceramic membranes is formed of a bearing membrane and a porcelain slurry with the solvent, the binder and the dispersant. The multi-layer stack resistance structure monomer is stacked on the ceramic substrate, and includes multiple bearing membranes and multiple resistive layers, wherein each resistive layer is formed on the surface of the corresponding bearing membrane, the resistive layers are parallel to each other, and the contiguous resistive layers are stacked with the interval of the predetermined distance along the vertical direction.

Abstract: The electrical multilayer component includes a base body with external electrodes and internal electrodes. A ceramic varistor layer is provided with the first internal electrode, and a dielectric layer adjoins the varistor layer. The dielectric layer has at least one opening filled with a semiconducting material or a metal.

Abstract: A semiconductor ceramic and a positive-coefficient characteristic thermistor are provided which have a stable PTC characteristic, a high double point, and a wide operating temperature range. The semiconductor ceramic contains, as a main component, a barium titanate-based composition having a perovskite structure expressed by a general formula AmBO3. Out of 100 mol % of the Ti, an amount in a range of 0.05 mol % or more to 0.3 mol % or less of Ti is replaced with W as a semiconductor forming agent, the ratio m of A sites mainly to B sites is 0.99?m?1.002, and an actually-measured sintered density is 70% or more and 90% or less of the theoretical sintered density. In the positive-coefficient characteristic thermistor, a component body is formed of the semiconductor ceramic.

Abstract: A multilayer ceramic substrate includes a ceramic laminated body including a plurality of ceramic layers stacked on each other, a resistor, and a resistor connecting conductor with a portion overlapping the resistor and an overcoat layer that covers the resistor located on a principal surface of the ceramic laminated body. An overcoat layer is made relatively thick during firing, thereby making cracks less likely to be caused, and after the firing step, the thickness of the overcoat layer is reduced by physically scraping down the surface of the overcoat layer, thereby reducing the trimming time. In the overcoat layer, a region that covers a portion in which a resistor overlaps a resistor connecting conductor is thicker than a region that covers the other portion.

Abstract: Provided may be a semiconductor resistance element including resistance patterns disposed on an insulating substrate. The substrate may have first and second planer surfaces disposed in a first direction, third and fourth planar surfaces at least between the first and second planar surfaces in a second direction and fifth and sixth planar surfaces at least between the first and second planar surfaces in a third direction. The semiconductor resistance element may include a first resistance pattern configured to cover a selected one of the first and second planar surfaces and a second resistance pattern on at least one of the third through sixth planar surfaces.

Abstract: A multilayer PTC thermistor 100 includes a ceramic body 10 having a plurality of ceramic layers 12 and internal electrodes 14 between adjacent ceramic layers 12, external electrodes 30 on the end faces 10a, 10b of the ceramic body 10, and a glass layer 20 on the surfaces 10c, 10d of the ceramic body 10, the glass layer 20 containing an oxide of at least one element selected from the group consisting of zinc and bismuth as the major component, wherein the alkali oxide content of the glass layer is no greater than 0.8 mass %.

Abstract: A chip resistor includes a substrate, a pair of electrode elements, a resistive layer, and a protective layer. The substrate is insulating and includes a first surface, a second surface opposite the first surface and a thickness defined between the first and second surface. The electrode elements are formed on the first and spaced apart. The resistive layer is formed on the first surface and electrically connected to the electrode elements. The protective layer to covers the resistive layer. The first surface faces toward a mounting target, on which the chip resistor is mounted. Each of the electrode elements comprises an electrode layer and a conductive layer formed on the electrode layer. The boundary between the electrode layer and the conductive layer in each of the electrode elements is positioned closer to the substrate than the end surface of the protective layer in the thickness direction of the substrate.

Abstract: A metal strip resistor is provided with a resistive element disposed between a first termination and a second termination. The resistive element, first termination, and second termination form a substantially flat plate. A thermally conductive and electrically non-conductive thermal interface material such as a thermally conductive adhesive is disposed between the resistive element and first and second heat pads that are placed on top of the resistive element and adjacent to the first and second terminations, respectively.

Abstract: Disclosed are low profile discrete electronic component structures that are suitable for placement and use in a vertical interconnection mode either within an electronic interconnection substrate, between interconnection substrate and electronic component or within an IC package.

Abstract: A chip resistor having first and second opposite ends includes a rigid insulated substrate having a top surface and an opposite bottom surface, a first electrically conductive termination pad and a second electrically conductive termination pad, both termination pads on the top surface of the rigid insulated substrate, a layer of resistive material between the first and second electrically conductive termination pads, and a first and a second flexible lead, each made of an electrically conductive metal with a solder enhancing coating. The first flexible lead attached and electrically connected to the first electrically conductive termination pad and the second flexible lead attached and electrically connected to the second electrically conductive termination pad. Each of the flexible leads has a plurality of lead sections facilitating bending around the end of the chip resistor.

Abstract: A circuitized substrate and method of making same in which quantities of thru-holes are formed within a dielectric interposer layer. The substrate includes two printed circuit board (PCB) layers bonded to opposing sides of the interposer with electrically conductive features of each PCB aligned with the interposer thru-holes. Resistive paste is positioned on the conductive features located adjacent the thru-holes to form controlled electrically resistive connections between conductive features of the two PCBs. A circuitized substrate assembly and method of making same are also disclosed.

Abstract: The present invention provides an array type chip resistor including: a substrate having a plurality of grooves formed on both sides thereof at equal spaces; lower electrodes formed on both sides of a bottom surface of the substrate; upper electrodes formed on both sides of a top surface of the substrate; side electrodes electrically connected to the upper and lower electrodes; a resistive element interposed between lower electrodes of the bottom surface of the substrate; a protection layer covered on the resistive element, the protection layer having both sides which cover a part of the lower electrodes and the resistive element; leveling electrodes being in contact with the lower electrodes exposed to outside of the protection layer; and a plating layer formed on the leveling electrodes.

Abstract: A chip resistor device includes: a dielectric substrate that has top and bottom surfaces and two opposite edge faces interconnecting the top and bottom surfaces; two electrodes that are formed on two opposite sides of the dielectric substrate and that cover the edge faces and parts of the top and bottom surfaces; a resistor layer that is formed on one of the top and bottom surfaces of the dielectric substrate between the electrodes and that is brought into contact with the electrodes; and a heat conductive layer that is disposed on the resistor layer oppositely of the dielectric substrate and between the electrodes, that contacts the resistor layer and the two electrodes, and that has a higher resistance than that of the resistor layer. A method for making the chip resistor device is also disclosed.

Abstract: A metal strip resistor is provided. The metal strip resistor includes a metal strip forming a resistive element and providing support for the metal strip resistor without use of a separate substrate. There are first and second opposite terminations overlaying the metal strip. There is plating on each of the first and second opposite terminations. There is also an insulating material overlaying the metal strip between the first and second opposite terminations. A method for forming a metal strip resistor wherein a metal strip provides support for the metal strip resistor without use of a separate substrate is provided. The method includes coating an insulative material to the metal strip, applying a lithographic process to form a conductive pattern overlaying the resistive material wherein the conductive pattern includes first and second opposite terminations, electroplating the conductive pattern, and adjusting resistance of the metal strip.

Abstract: A chip-like electric component such as a chip resistor is provided, which is easy to manufacture and in which cracks or fractures of an insulating substrate are unlikely to occur. A pair of surface electrodes 21, 23 are formed so that thicknesses of the pair of surface electrodes increase from a resistor layer 13 toward end portions 30 of an insulating substrate 29 in a direction in which the pair of surface electrodes 21, 23 are arranged. A plating reservoir S is formed between one of the surface electrodes 21, 23 and an insulating protective layer 15. When forming at least one plated layer 33, a plated metal pools in the plating reservoir S. The at least one plated layer 33 may work to reduce to some extent a height difference between a soldering electrode portion 21, 23, 27, 33 and the insulating protective layer 15.

Abstract: An integrated method includes fabricating a metal gate and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a polysilicon structure of the polysilicon resistor. When the gate conductor of a poly gate transistor is etched, the part of the polysilicon structure is protected by the patterned photoresistor layer. After the polysilicon resistor and the metal gate are formed. The polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.

Abstract: A chip resistor includes an insulating substrate 11, top terminal electrodes 12 formed on top surface of the substrate using silver-based cermet, bottom electrodes 13, resistive element 14 that is situated between the top terminal electrodes 12 and overlaps them partially, an optional internal protective coating 15 that covers resistive element 14 completely or partially, an external protective coating 16 that covers completely the internal protection coating 15 and partially covers top terminal electrodes 12, a plated layer of nickel 17 that covers face sides of the substrate, top 12 and bottom 13 electrodes, and overlaps partially external protective coating 16, finishing plated layer 18 that covers nickel layer 17. The overlap of nickel layer 17 and external protective layer 16 possesses a sealing property because of metallization of the edges of external protective layer 16 prior to the nickel plating process.

Abstract: A resistor device includes a resistor plate having a first aperture, a second aperture, a third aperture and a fourth aperture respectively arranged on a first side, a second side, a third side and a fourth side thereof. A first electrode plate is coupled to the first side of the resistor plate and includes a first measurement zone and a second measurement zone disposed at opposite sides of the first aperture; and a second electrode plate is coupled to the third side of the resistor plate and including a third measurement zone and a fourth measurement zone disposed at opposite sides of the third aperture, wherein the first measurement zone and the third measurement zone are disposed at opposite sides of the second aperture, and the second measurement zone and the fourth measurement zone are disposed at opposite sides of the fourth aperture.

Abstract: The present invention provides an array type chip resistor including: a substrate formed in a rectangular parallelepiped shape; lower electrodes disposed on both sides of a bottom surface of the substrate at equal spaces; side electrodes extended from some of lower electrodes, formed on outermost edges of both sides of the substrate, in all lower electrodes, to a side surface of the substrate; a resistive element interposed between lower electrodes of the bottom surface of the substrate; a protection layer covered on the resistive element, the protection layer having both sides which cover a part of the lower electrodes and the resistive element; leveling electrodes being in contact with the lower electrodes exposed to outside of the protection layer; and a plating layer formed on the leveling electrodes.

Abstract: A resistor R1 formed by forming a first resistor layer 5a of 20 nm thickness including a tantalum nitride film at a concentration of nitrogen of less than 30 at % and a second resistor layer of 5 nm thickness including a tantalum nitride film at a concentration of nitrogen of 30 at % or more successively by a reactive DC sputtering method using tantalum as a sputtering target material and using a gas mixture of argon and nitrogen as a sputtering gas, and then fabricating the first and the second resistor layers, in which the resistance change ratio of the resistor can be suppressed to less than 1% even when a thermal load is applied in the interconnection step, by the provision of the upper region at a concentration of nitrogen of 30 at % or more.

Abstract: In an exemplary decision-feedback equalizer (DFE) of a serializer/deserializer (SerDes) receiver, a single current mirror array is shared by multiple current digital-to-analog converter (IDAC) functions. The DFE has an initial amplifier stage that applies an initial coefficient COEFF0 to an input data signal and a number of (e.g., five) additional amplifier stages that apply additional coefficients (e.g., COEFF1-COEFF5) to different delayed versions of the recovered output data stream. The outputs of the initial and multiple additional amplifier stages are summed to generate an equalized data signal that is applied to a clock-and-data recovery (CDR) circuit. Due to certain characteristics of the equalizer function, the multiple additional amplifier stages can be implemented using a single shared current mirror array, which save significant amounts of chip area compared to conventional implementations in which each additional amplifier stage has its own dedicated current mirror array.

Abstract: An electrical multilayer component has a stack of dielectric layers and electrode layers arranged one above another. Electrode layers of identical electrical polarity are jointly contacted to an external contact arranged at a side face of the stack. A resistor sintered to the stack and containing ceramic resistance material is arranged on an end face of the stack.

Abstract: A positive temperature coefficient heater may include at least one positive temperature coefficient rod having a heating module inserted into a rod case made of brass and plated with tin, at least one heat-radiating fin made of brass, plated with tin, and contacted and coupled with each of opposite outer faces of the positive temperature coefficient rod, and upper and lower housings coupled to opposite longitudinal ends of the positive temperature coefficient rod, wherein the positive temperature coefficient rod and the heat-radiating fin are joined together by soldered portions.

Abstract: The invention discloses a variable attenuator, comprising two or more resistors each resistor having its own effective resistance value, and means for simultaneously short circuiting at least a portion of two or more of said resistors, whereby simultaneously changing the effective resistance values. The variable attenuator of the invention is suitable for use in various high frequency and microwave circuits and systems, and has the features of a wide frequency band, small size, easy fabrication, low cost, and so on.

Abstract: A chip resistor (A1) includes a chip-like resistor element (1), two electrodes (31) spaced from each other on the bottom surface (1a) of the resistor element, and an insulation film (21) between the two electrodes. Each electrode (31) has an overlapping portion (31c) which overlaps the insulation film (21) as viewed in the vertical direction.

Abstract: A method for manufacturing rectangular plate type chip resistors and a rectangular plate type chip resistor obtained by this method. The method includes the steps of (A) providing a resistive alloy plate strip of predetermined width and thickness, (B) forming an insulating protective film of a predetermined width longitudinally along the middle of upper and lower faces of the alloy plate strip, (C) forming an electrode layer composed of integrated surface, back, and end electrodes, along both sides of the protective film by electroplating, and (D) cutting the alloy plate strip coated with the protective films and the electrode layers in step (C) transversely in predetermined lengths, wherein resistance is controlled to be within a predetermined range by adjusting the thickness of the alloy plate strip in step (A), the width of the protective film formed in step (B), and the cutting length in step (D).

Abstract: A varistor 1 comprises a varistor element 10, a pair of external electrodes 30a, 30b on one main side of the varistor element 10 and a resistor 60 on the same main side, wherein the resistor 60 is formed so as to connect the pair of external electrodes 30a, 30b. The varistor element 10 contains zinc oxide as the main component and Ca oxides, Si oxides and rare earth metal oxides as accessory components, wherein the proportion X of the calcium oxides in terms of calcium atoms is 2-80 atomic percent with respect to 100 mol of the main component and the proportion Y of the silicon oxides in terms of silicon atoms is 1-40 atomic percent with respect to 100 mol of the main component, X/Y satisfying formula (1) below, and the external electrodes and resistor contain oxides other than bismuth oxide and copper oxide 1?X/Y<3??(1).

Abstract: A multilayer element has a body in which at least one first internal electrode and at least one second internal electrode are arranged. These internal electrodes have an overlapping region, which extends up to the surface of the body on at least one side. The internal electrodes have a recess in a corner region of the body.

Abstract: A heating system in the form of a multi-layer, yet relatively thin and flexible panel. The panel contains a number of layers including first, second and third electrically insulating layers. A first electrically conductive resistive layer (heater layer) is sandwiched between the first and second insulating layers. A second electrically conductive resistive layer (resistive neutral plane layer) is sandwiched between the second and third insulating layers. The heater layer has a neutral electrical connection and a live electrical connection. The neutral and live electrical connections are electrically connected to each other at the panel only by electrically resistive material of the heater layer extending between the neutral and live electrical connections. The resistive neutral plane layer has a neutral electrical connection electrically connected with the neutral connection of the heater layer.

Abstract: The present invention relates to a chip resistor and method for making the same. The chip resistor includes a substrate, a pair of bottom electrodes, a resistive film, a pair of main upper electrodes, a first protective coat, a pair of barrier layers, a second protective coat, a pair of side electrodes and at least one plated layer. The first protective coat is disposed over the resistive film, and covers part of the main upper electrodes. The barrier layers are disposed on the main upper electrodes, and cover part of the first protective coat. The second protective coat is disposed on the first protective coat, and covers part of the barrier layers. The plated layers cover the barrier layers, the bottom electrodes and the side electrodes. As a result, the chip resistor features high corrosion resistance.

Abstract: The present invention relates to a chip resistor having low resistance and a method for manufacturing the same. The chip resistor includes a substrate, a resistive layer, a pair of conducting layers and at least one protective layer. The substrate has a first surface. The resistive layer is disposed on the first surface of the substrate. The conducting layers are disposed adjacent to the first surface of the substrate. The at least one protective layer is disposed on the resistive layer or the conducting layers. As a result, the resistive layer has a precise pattern, and the duration of sputtering is reduced, thereby improving yield rate and efficiency while reducing manufacturing cost.

Abstract: A thin-film resistor with a layer structure with a Ti layer and a TiN layer is described, wherein a layer thickness of the Ti layer and a layer thickness of the TiN layer are selected such that a resulting temperature coefficient of resistance (TCR) is smaller than 1000 ppm/° C.

Abstract: A resistive component suitable for detecting electric current in a circuit and a method of manufacturing the resistive component are provided. The resistive component includes a carrier, a resistive layer, an electrode unit, an upper oxide layer and a protective layer. The resistive layer comprises copper alloy and is disposed on the carrier. The electrode unit is electrically connected to the resistive layer. The upper oxide layer is disposed on a part of a surface of the resistive layer and includes oxides of the resistive layer. The protective layer covers at least a part of the upper oxide layer.

Abstract: The invention relates to a resistor (18), particularly an SMD resistor, including a planar, metallic support element (19) that has a top surface and a bottom surface, a planar resistor element (21) which is made of a resistive material and is disposed on the bottom surface of the support element (19), and at least two separate metallic connecting parts (23, 23) which electrically contact the resistor element (21) and are arranged in part on the bottom surface of the support element (19). The connecting parts (22, 23) are laterally exposed on the resistor (18) and can be laterally wetted in a visible manner by a solder. The invention further relates to a corresponding production method.

Abstract: Provided are a stacked electronic part that can sufficiently suppress plating deposition on the surface of a porous green body when a terminal electrode is formed on an external electrode, thereby enabling a decrease in the reliability of products to be prevented, and a method of manufacturing the stacked electronic part. The stacked electronic part 1 is a PTC thermistor having a stacked body 4 containing a porous green body 2 made of ceramics and having a plurality of vacancies and a plurality of internal electrodes 3 formed within the porous green body 2, and is provided with at least one unit structure 10 in which the porous green body 2 and the internal electrode 3 are stacked. External electrodes 5, 5 are connected to the internal electrode 2, and upon the external electrodes 5, 5 are formed terminal electrodes 7, 7 by plating. Resin is filled in the plurality of vacancies of the porous green body 2 at a filling ratio of not less than 60%.

Abstract: An electrical component includes a first varistor and a second varistor. The first varistor includes first electrodes and ceramic between the first electrodes. At least part of the first electrodes overlap vertically. The second varistor includes second electrodes and ceramic between the second electrodes. The second electrodes are in a substantially same horizontal plane.