Terminal Coated On Patents (Class 338/309)
  • Publication number: 20080290984
    Abstract: An embedded resistor device includes a resistor, a ground plane located near a first side of the resistor and electrically coupled to a first end of the resistor, at the ground plane a hole is provided, a first dielectric layer exists between the resistor and the ground plane, a conductive wire, which is electrically coupled to a second end of the resistor different from the first end of the resistor and partially surrounds the resistor, is used as an auxiliary for supporting a resistor-coating process of the resistor and to provide a terminal of the embedded resistor device at the conductive wire, a conductive region located near a second side of the ground plane different from the first side of the resistor, a second dielectric layer exists between the ground plane and the conductive region, and a conductive path to electrically couple the conductive wire to the conductive region through the hole.
    Type: Application
    Filed: September 7, 2007
    Publication date: November 27, 2008
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chang-Lin Wei, Chang-Sheng Chen, Cheng-Hua Tsai, Syun Yu, Chin-Sun Shyu
  • Publication number: 20080224818
    Abstract: A chip resistor (A1) includes a chip-like resistor element (1), two electrodes (31) spaced from each other on the bottom surface (1a) of the resistor element, and an insulation film (21) between the two electrodes. Each electrode (31) has an overlapping portion (31c) which overlaps the insulation film (21) as viewed in the vertical direction.
    Type: Application
    Filed: March 23, 2005
    Publication date: September 18, 2008
    Applicant: ROHM CO., LTD
    Inventors: Masanori Tanimura, Torayuki Tsukada, Kousaku Tanaka
  • Publication number: 20080218306
    Abstract: A chip resistor includes an insulating substrate, a pair of electrodes formed on a main surface of the substrate and a resistor element electrically connected to the electrodes. The paired electrodes are spaced from each other in a first direction. The main surface of the substrate is formed with a raised portion in the form of a plateau which is smaller in size than the substrate in a second direction perpendicular to the first direction. The paired electrodes are formed on the raised portion. The resistor element is equal in size to the raised portion in the second direction.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 11, 2008
    Applicant: ROHM CO., LTD.
    Inventor: Yoshikazu Tamaki
  • Publication number: 20080211036
    Abstract: A nonvolatile memory device includes a semiconductor substrate, a first electrode on the semiconductor substrate, a resistive layer on the first electrode, a second electrode on the resistive layer and at least one tunneling layer interposed between the resistive layer and the first electrode and/or the second electrode. The resistive layer and the tunneling layer may support transition between first and second resistance states responsive to first and second voltages applied across the first and second electrodes. The first and second voltages may have opposite polarities.
    Type: Application
    Filed: February 26, 2008
    Publication date: September 4, 2008
    Inventors: Jin Shi Zhao, Jang-eun Lee, In-gyu Baek, Se-chung Oh, Kyung-tae Nam, Eun-kyung Yim
  • Publication number: 20080211619
    Abstract: A chip resistor includes an insulating substrate 11, top terminal electrodes 12 formed on top surface of the substrate using silver-based cermet, bottom electrodes 13, resistive element 14 that is situated between the top terminal electrodes 12 and overlaps them partially, an optional internal protective coating 15 that covers resistive element 14 completely or partially, an external protective coating 16 that covers completely the internal protection coating 15 and partially covers top terminal electrodes 12, a plated layer of nickel 17 that covers face sides of the substrate, top 12 and bottom 13 electrodes, and overlaps partially external protective coating 16, finishing plated layer 18 that covers nickel layer 17. The overlap of nickel layer 17 and external protective layer 16 possesses a sealing property because of metallization of the edges of external protective layer 16 prior to the nickel plating process.
    Type: Application
    Filed: February 13, 2008
    Publication date: September 4, 2008
    Applicant: VISHAY INTERTECHNOLOGY, INC.
    Inventors: Michael Belman, Leonid Akhtman
  • Publication number: 20080197967
    Abstract: The present invention relates to an adjustable resistor embedded in a circuit board and a method of fabricating the same. The adjustable resistor comprises a resistor with a number of connection terminals, and a number of via holes extending to contact with the resistor. The resistive value of the resistor is variable depending on the size of the via holes, the number of the via holes, or the distance between the via holes.
    Type: Application
    Filed: February 16, 2007
    Publication date: August 21, 2008
    Inventors: Chin-Sun Shyu, Chang-Sheng Chen, Chang-Lin Wei, Wei-Ting Chen
  • Patent number: 7403095
    Abstract: A thin film resistor structure and a method of fabricating a thin film resistor structure is provided. The thin film resistor structure includes an electrical interface layer or head layer that is a combination of a Titanium (Ti) layer and a Titanium Nitride (TiN) layer. The combination of the Ti layer and the TiN layer mitigates resistance associated with the electrical interface layers.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: July 22, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Brian Vialpando, Eric William Beach, Philipp Steinmann
  • Patent number: 7403094
    Abstract: An integrated circuit thin film resistor structure includes a first dielectric layer (18A) disposed on a semiconductor layer (16), a first dummy fill layer (9A) disposed on the first dielectric layer (18B), a second dielectric layer (18C) disposed on the first dummy fill layer (9A), the second dielectric layer (18B) having a first planar surface (18-3), a first thin film resistor (2) disposed on the first planar surface (18-3) over the first dummy fill layer (9A). A first metal interconnect layer (22A,B) includes a first portion (22A) contacting a first head portion of the thin film resistor (2). A third dielectric layer (21) is disposed on the thin film resistor (2) and the first metal interconnect layer (22A,B). Preferably, the first thin film resistor (2) is symmetrically aligned with the first dummy fill layer (9A). In the described embodiments, the first dummy fill layer is composed of metal (integrated circuit metallization).
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: July 22, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Eric W. Beach, Walter B. Meinel, Philipp Steinmann
  • Patent number: 7394344
    Abstract: A chip resistor includes a chip substrate, a terminal electrode formed on an upper surface of the chip substrate in a region close to the respective end portions, and a resistant film formed in a zigzag-folded shape on the upper surface of the chip substrate between the terminal electrodes. An inner edge of at least one of the terminal electrodes includes a protrusion integrally formed so as to project from a portion close to a side edge of the chip substrate toward the resistant film, for achieving electrical connection between the resistant film and the protrusion. A side edge of the protrusion facing inward farther from the side edge of the chip substrate is inclined such that a front edge of the protrusion has a narrower width.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: July 1, 2008
    Assignee: Rohm Co., Ltd.
    Inventor: Masaki Yoneda
  • Publication number: 20080129443
    Abstract: The chip resistor (1) includes an insulating substrate (2) and a main upper electrode (4) formed on a main surface of the insulating substrate (2). On the main surface of the insulating substrate (2) , a resistor film (5) including an end (5a) overlapping the upper surface of main upper electrode (4) is formed. The resistor film (5) is covered by a protective coat (7, 8). An auxiliary upper electrode (6) is formed on the upper surface of the main upper electrode (4). The auxiliary upper electrode (6) includes an inner end (6a) overlapping the upper surface of the end (5a) of the resistor film (5). The protective coat (7, 8) overlaps the inner end (6a) of the auxiliary upper electrode (6).
    Type: Application
    Filed: February 28, 2006
    Publication date: June 5, 2008
    Applicant: ROHM CO., LTD.
    Inventors: Torayuki Tsukada, Masaki Yoneda
  • Patent number: 7378937
    Abstract: A chip resistor includes a resistor element in the form of a chip, and at least two electrodes formed on the resistor element. The resistor element includes an upper surface, a lower surface, and two end surfaces extending between the upper and the lower surfaces and spaced from each other. The two electrodes are provided on the lower surface of the resistor element. Each of the end surfaces of the resistor element is formed with a conductor film integrally connected to a corresponding one of the electrodes. The conductor film is made of copper, for example, and is higher in solder-wettability than the resistor element.
    Type: Grant
    Filed: February 8, 2007
    Date of Patent: May 27, 2008
    Assignee: Rohm Co., Ltd.
    Inventor: Torayuki Tsukada
  • Patent number: 7352273
    Abstract: The invention relates to a method of making a chip resistor using a material substrate for which are set a plurality of first cutting lines extending in a first direction and a plurality of second cutting lines extending in a second direction perpendicular to the first direction. The method includes an upper electrode forming step A for forming a thick upper conductor layer on the upper surface of the substrate by printing and baking a metal organic paste, a lower electrode forming step B for forming a thick lower conductor layer on the lower surface of the substrate by printing and baking metal organic paste, and a resistor element forming step C for forming a thin resistor layer by depositing a resistor material on the upper surface of the substrate. Preferably, the upper and the lower surfaces of the material substrate are flat.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: April 1, 2008
    Assignee: Rohm Co., Ltd.
    Inventor: Masanori Tanimura
  • Patent number: 7342480
    Abstract: A chip resistor includes a resistor element of a rectangular solid made of an alloy composed of high-resistant metal and low-resistant metal. The resistor has connection terminal electrodes disposed at the ends of the resistor element that are spaced longitudinally of the rectangular solid. The resistance of the chip resistor is lowered without incurring an increase in the temperature coefficient of resistance and the weight. A plating layer is formed on the resistor element, where the plating element is made of pure metal having a lower resistance that that of the alloy constituting the resistor element.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: March 11, 2008
    Assignee: Rohm Co., Ltd.
    Inventor: Torayuki Tsukada
  • Patent number: 7334318
    Abstract: A method of manufacturing an inexpensive fine resistor which do not require dimensional classifications of discrete substrates is disclosed. The method eliminates a process of replacing a mask according to a dimensional ranking of each discrete substrate. The method includes: dividing an insulated substrate sheet along a first slit dividing portion and a second dividing portion perpendicular to the first dividing portion; forming a top electrode layer on a top face of the discrete substrate; forming a resistor layer such that a part of the resistor layer overlaps the top electrode layer; forming protective layers so as to cover the resistor layer; and forming side electrode layer on a side face of the discrete substrate such that the side electrode layer is electrically coupled to the top electrode layer.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: February 26, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masato Hashimoto, Yoshiro Morimoto, Akio Fukuoka, Hiroaki Kaito, Hiroyuki Saikawa, Toshiki Matsukawa, Junichi Hayase
  • Patent number: 7330099
    Abstract: A chip resistor includes a resistive element (1), an insulation layer (4) formed in a back surface of the flat surface, and two electrodes (3) spaced from each other via the insulation layer. Each electrode (3) makes contact with the insulation layer (4). Each electrode (3) has a lower surface formed with a solder layer (39).
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: February 12, 2008
    Assignee: Rohm Co., Ltd.
    Inventor: Torayuki Tsukada
  • Patent number: 7326889
    Abstract: A method of manufacturing a PTC element comprising a pair of lead terminals bonded together by thermocompression with a matrix held therebetween comprises a matrix preparing step of preparing a matrix constructed by dispersing a conductive filler into a crystalline polymer; a terminal preparing step of preparing a pair of lead terminals holding the matrix therebetween, a surface of each lead terminal facing the matrix being formed with a plurality of anchor protrusions separated from each other; a flattening step of flattening the anchor protrusions formed in respective nonoverlapping areas in the pair of lead terminals kept from overlapping the matrix; and a thermocompression bonding step of holding the matrix between respective overlapping areas in the pair of lead terminals overlapping the matrix, and securing the pair of lead terminals and the matrix together by thermocompression bonding.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: February 5, 2008
    Assignee: TDK Corporation
    Inventors: Hisanao Tosaka, Tokuhiko Handa, Hirokazu Satoh, Tsutomu Hatakeyama
  • Patent number: 7327214
    Abstract: A chip resistor includes a metal resistor element having a flat lower surface. The lower surface is formed with two electrodes spaced from each other, and an insulating resin film is formed between these electrodes. Each of the electrodes partially overlaps the insulating film so that a portion of the insulating film is inserted between each of the electrodes and the lower surface of the resistor element.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: February 5, 2008
    Assignee: Rohm Co., Ltd.
    Inventor: Torayuki Tsukada
  • Patent number: 7310036
    Abstract: A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.
    Type: Grant
    Filed: January 10, 2005
    Date of Patent: December 18, 2007
    Assignee: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Terence B. Hook, Robert M. Rassel, Edmund J. Sprogis, Anthony K Stamper, William J. Murphy
  • Patent number: 7305754
    Abstract: In manufacturing a chip resistor by dividing a chip resistance substrate which includes an insulator, resistance film formed on a surface of the insulator, and a plurality of conductive strips disposed on the resistance film at fixed intervals, grooves are formed by removing a predetermined width of the resistance film including at least second prescribed severing lines. After forming the grooves, the chip resistance substrate is severed in longitudinal and lateral directions along first prescribed severing lines for dividing the conductive strips into two parts and the second prescribed severing lines perpendicular to the first prescribed severing lines so as to produce discrete chip resistors.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: December 11, 2007
    Assignee: Disco Corporation
    Inventors: Kazuma Sekiya, Toshiaki Takahashi
  • Patent number: 7297902
    Abstract: The present invention provides a window assembly having a transparent panel and a conductive heater grid formed integrally with the transparent panel. The conductive heater grid has a first group of grid lines and a second group of grid lines, with opposing ends of each group being connected to first and second busbars. Grid lines of the second group are spaced between adjacent grid lines of the first group, with the height of the grid lines themselves in the second group being less than the height of the grid lines in the first group.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: November 20, 2007
    Assignee: Exatec, LLC
    Inventor: Keith D. Weiss
  • Patent number: 7286039
    Abstract: A chip resistor is provided which includes a resistor film 5 formed between a pair of terminal electrodes 2 and 3 on an upper surface of an insulating substrate 2. The resistor film is formed with two inward grooves 7, 8 and two trimming grooves 9, 10 which are alternately provided for causing the current path in the resistor film to have a winding shape. The two inward grooves 7 and 8 are provided approximately at the midpoint between one end edge 5a and the other end edge 5b of the resistor film 5. The trimming groove 9 is provided between the inward groove 8 and the end edge 5a of the resistor film, whereas the other trimming groove 10 is provided between the inward groove 7 and the end edge 5b of the resistor film, whereby the time required for the trimming adjustment to adjust the resistance to a predetermined value is shortened, and the yield rate is reduced to reduce the cost.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: October 23, 2007
    Assignee: Rohm Co., Ltd.
    Inventor: Masaki Yoneda
  • Patent number: 7278202
    Abstract: A surface mount resistor includes an elongated piece of resistive material having strips of conductive material attached to its opposite ends. The strips of conductive material are separated to create an exposed central portion of the resistive material therebetween. According to the method the resistive strip is attached to a single co extensive strip of conductive material and a central portion of the conductive material is removed to create the exposed central portion of the resistive strip.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: October 9, 2007
    Assignee: Vishay Dale Electronics, Inc.
    Inventors: Joel J. Smejkal, Steve E. Hendricks
  • Patent number: 7277006
    Abstract: Chip resistor includes the rectangular first substrate made of ceramics and having surfaces, the rectangular second substrate made of ceramics and having surfaces, and a joint layer interposed between the surfaces, and electrodes are formed on two opposing sides of the substrate and resistor is formed between the electrodes. Further, electrodes are formed on two opposing sides of the substrate and resistor is formed between the electrodes.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: October 2, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideo Yokoo
  • Patent number: 7277005
    Abstract: Disclosed is a PCB including an embedded resistor and a method of fabricating the same. The PCB includes a plurality of circuit layers in which circuit patterns are formed. A plurality of insulating layers is each interposed between the circuit layers. The embedded resistor is made of a resistive material and received in a receiving hole formed in the plurality of circuit layers and the plurality of insulating layers such that walls defining the receiving hole extends from one of the circuit layers to another circuit layer. The receiving hole has a closed section, and a conductive material is plated on the opposite walls of the walls defining the receiving hole.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: October 2, 2007
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Myung Sam Kang, Chang Sup Ryu, Jong Kuk Hong
  • Patent number: 7271700
    Abstract: A thin film resistor device and method of manufacture includes a layer of a thin film conductor material and a current density enhancing layer (CDEL). The CDEL is an insulator material adapted to adhere to the thin film conductor material and enables the said thin film resistor to carry higher current densities with reduced shift in resistance. In one embodiment, the thin film resistor device includes a single CDEL layer formed on one side (atop or underneath) the thin film conductor material. In a second embodiment, two CDEL layers are formed on both sides (atop and underneath) of the thin film conductor material. The resistor device may be manufactured as part of both BEOL and FEOL processes.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: September 18, 2007
    Assignee: International Business Machines Corporation
    Inventors: Anil K. Chinthakindi, Ebenezer E. Eshun
  • Patent number: 7262682
    Abstract: A stress sensor in which the direction and magnitude of a stress being applied to a post bonded to or integrated with an insulating board can be grasped from variation in the resistance of resistor elements being stimulated by application of the stress while suppressing variation in the shape of each resistor. The resistor element comprises a resistor formed, by screen print, between a pair of electrodes for the resistor element, i.e. circuit pattern electrodes, arranged on the surface of the insulating board. The electrode is connected, through a conductor, with a board terminal part arranged at one end of the insulating board. The electrode and the conductor or a print accuracy adjusting member have a constant height from the surface of the insulating board. Arrangement of the conductor, electrode and print accuracy adjusting member is entirely identical or similar for the resistor elements in the vicinity thereof.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: August 28, 2007
    Assignee: Elantech Devices Corporation
    Inventors: Etsuo Ooba, Atsuomi Inukai, Fumiaki Karasawa, Hiroshi Yajima
  • Patent number: 7241131
    Abstract: A thick-film electric heater having thick-film layers applied directly on a thermally conductive non-flat substrate. Preferably, the substrate is cylindrically shaped. A dielectric layer is silk-screened on the substrate surface. A resistive layer is silk-screened on the dielectric layer to form a circuit for the generation of heat. The resistive layer has at least one resistive trace in a pattern that is discontinuous circumferentially. At least a pair of silk-screened contact pads are applied in electrical communication with the resistive layer for electrical connection to a power source. An insulation layer is applied over the resistive layer.
    Type: Grant
    Filed: June 19, 2000
    Date of Patent: July 10, 2007
    Assignee: Husky Injection Molding Systems Ltd.
    Inventors: Andrew Booth, Harold Warren, Wink Winkelmann, Edward Jenko, Jim Pilavdzic
  • Patent number: 7221254
    Abstract: A resistor, including a resistive element made of a metal plate, has a low resistance resulting from connection terminal electrodes formed on both ends of the lower surface of the resistive element. The object thereof is to achieve weight reduction and lower costs by reducing the height of the resistor. To achieve the above object, the ends of the lower surface of the resistive element are provided with recesses for accommodating the connection terminal electrodes, while at least the intermediate area of the lower surface of the resistive element between the connection terminal electrodes is covered with an insulator. Alternatively, a recess may be formed in the middle of the lower surface of the resistive element for using the ends of the lower surface as a pair of connection terminal electrodes, the recess being internally covered with an insulator.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: May 22, 2007
    Assignee: Rohm Co., Ltd.
    Inventor: Torayuki Tsukada
  • Patent number: 7203049
    Abstract: The over-current protection device of the present invention uses the unbalanced properties of the thermal expansion coefficients between the outer and inner sides for an upper metallic conductive sheet and a lower metallic conductive sheet to generate a torque to deform outwardly. The torque is used to pull a current-sensing element and present with at least a cracking face, so as to introduce an electrically open effect similar to a fuse. Thus, the present invention can achieve the object for preventing the danger of circuit system by the short circuit during the burning of over-current protection device.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: April 10, 2007
    Assignee: Polytronics Technology Corporation
    Inventors: Edward Fu-Hua Chu, David Shau-Chew Wang, Yun-Ching Ma
  • Patent number: 7199446
    Abstract: An electrical resistor structure overlies a substrate and comprises a composite resistor having a first resistor of relatively low resistance and a second resistor of relatively high resistance overlying the first resistor. First and second electrodes make contact with the composite resistor at spaced locations, and a bond pad overlies the second resistor at a position between the electrodes. A metallized fiber is soldered a to a metal bond pad by providing a stacked resistor structure beneath the bond pad, disposing a solder preform over the bond pad, disposing the metallized fiber over the bond pad, and flowing a current through the stacked resistor structure. The stacked resistor structure, when subjected to a current flowing generally along a first axis, is characterized by a temperature profile that has first and second peaks on either side of the bond pad.
    Type: Grant
    Filed: February 18, 2003
    Date of Patent: April 3, 2007
    Assignee: K2 Optronics, Inc.
    Inventors: Zequn Mei, Richard D. Bjorn, Frans Kusnadi, John Cameron Major
  • Patent number: 7199016
    Abstract: An integrated circuit resistor is provided that comprises a mesa 14 between electrical contacts 16 and 18. The electrical resistance between electrical contacts 16 and 18 is selectively increased through the formation of recesses 20 and 22 in the mesa 14. The size of recesses 20 and 22 can be used to tune the value of the electrical resistance between contacts 16 and 18.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: April 3, 2007
    Assignee: Raytheon Company
    Inventors: David D. Heston, Jon E. Mooney
  • Patent number: 7193500
    Abstract: An integrated circuit includes a bilayer thin film resistor in which the lower layer is a seed layer that controls the crystal structure of the upper layer. The thickness of the lower layer and the thickness of the upper layer may be chosen to form a resistor with a TCR having a design value.
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: March 20, 2007
    Assignee: International Business Machines Corporation
    Inventors: Anil K. Chinthakindi, Anita Madan, Kenneth J. Stein, Kwong Hon Wong
  • Patent number: 7192654
    Abstract: The invention concerns multilayered constructions useful for forming resistors and capacitors, for the manufacture of printed circuit boards or other microelectronic devices. The multilayered constructions comprise sequentially attached layers comprising: a first electrically conductive layer, a first thermosetting polymer layer, a heat resistant film layer, a second thermosetting polymer layer, and a nickel-phosphorus electrical resistance material layer electroplated onto a second electrically conductive layer.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: March 20, 2007
    Assignees: Oak-Mitsui Inc., Ohmega Technologies Inc.
    Inventors: John A. Andresakis, Pranabes K. Pramanik, Bruce Mahler, Daniel Brandler
  • Patent number: 7193499
    Abstract: A chip resistor includes a resistor element in the form of a chip, and at least two electrodes formed on the resistor element. The resistor element includes an upper surface, a lower surface, and two end surfaces extending between the upper and the lower surfaces and spaced from each other. The two electrodes are provided on the lower surface of the resistor element. Each of the end surfaces of the resistor element is formed with a conductor film integrally connected to a corresponding one of the electrodes. The conductor film is made of copper, for example, and is higher in solder-wettability than the resistor element.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: March 20, 2007
    Assignee: Rohm Co., Ltd.
    Inventor: Torayuki Tsukada
  • Patent number: 7188404
    Abstract: An inexpensive fine resistor which do not require dimensional classifications of discrete substrates, eliminating a process of replacing a mask according to a dimensional ranking of each discrete substrate as in the prior art. The resistor includes discrete substrate made into pieces by dividing an insulated substrate sheet along a first slit dividing portion and a second dividing portion perpendicular to the first dividing portion; top electrode layer formed on a top face of discrete substrate; resistor layer formed such that a part of resistor layer overlaps top electrode layer; protective layers formed so as to cover resistor layer; side electrode layer formed on a side face of discrete substrate such that side electrode layer is electrically coupled to top electrode layer.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: March 13, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masato Hashimoto, Yoshiro Morimoto, Akio Fukuoka, Hiroaki Kaito, Hiroyuki Saikawa, Toshiki Matsukawa, Junichi Hayase
  • Patent number: 7190252
    Abstract: An electrical resistor is provided with a resistive element and terminations extending from opposite ends of the resistive element. The terminations are folded under the resistive element, with a thermally conductive and electrically insulative filler being sandwiched and bonded between the resistive element and the terminations. The terminations provide for mounting of the resistor to an electronic circuit assembly. The intimate bond between the resistive element, filler and terminations allow for enhanced dissipation of heat generated in the use of the resistive element, so as to produce a resistor which operates at a lower temperature, and improves component reliability.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: March 13, 2007
    Assignee: Vishay Dale Electronics, Inc.
    Inventors: Clark L. Smith, Thomas L. Veik, Todd L. Wyatt, Thomas L. Bertsch, Rodney Brune, William Mac Arthur
  • Patent number: 7176781
    Abstract: A resistor formed on a material layer of a semiconductor integrated circuit and a method for forming the resistor. The resistor comprises a region of resistive material with a plurality of conductive contacts or plugs in electrical contact with and extending away from the resistive material. A first and a second interconnect line are formed overlying the plugs and in conductive contact with one or more of the plurality of plugs, such that a portion of the resistive material between the first and the second interconnect lines provides a desired resistance. According to a method of the present invention, the plurality of conductive contacts are formed using a first photolithographic mask and the first and the second interconnect lines are formed using a second photolithographic mask. The desired resistance is changed by modifying the first or the second mask such that one or more dimensions of a region of the resistive material between the first and the second interconnect lines is altered.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: February 13, 2007
    Assignee: Agere Systems Inc
    Inventors: Daniel Charles Kerr, Roger W. Key, Bradley J. Albers, William A. Russell, Alan Sangone Chen
  • Patent number: 7170389
    Abstract: The present invention discloses a method of manufacturing a thin resistor with a moisture barrier by depositing a metal film layer on a substrate and depositing a layer of tantalum pentoxide film overlaying the metal film layer. The present invention also includes a thin film resistor having a substrate; a metal film layer attached to the substrate; and a tantalum pentoxide layer overlaying the metal film layer, the tantalum pentoxide layer providing a barrier to moisture, the tantalum pentoxide layer not overlaid by and oxidation process.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: January 30, 2007
    Assignee: Vishay Dale Electronics, Inc.
    Inventor: Stephen C. Vincent
  • Patent number: 7165315
    Abstract: An inexpensive fine resistor which do not require dimensional classifications of discrete substrates, eliminating a process of replacing a mask according to a dimensional ranking of each discrete substrate as in the prior art. The resistor includes discrete substrate made into pieces by dividing an insulated substrate sheet along a first slit dividing portion and a second dividing portion perpendicular to the first dividing portion; top electrode layer formed on a top face of discrete substrate; resistor layer formed such that a part of resistor layer overlaps top electrode layer; protective layers formed so as to cover resistor layer; side electrode layer formed on a side face of discrete substrate such that side electrode layer is electrically coupled to top electrode layer.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: January 23, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masato Hashimoto, Yoshiro Morimoto, Akio Fukuoka, Hiroaki Kaito, Hiroyuki Saikawa, Toshiki Matsukawa, Junichi Hayase
  • Patent number: 7161459
    Abstract: In chip electronic components, the application state of conductive paste that makes side electrodes can be optically distinguished in the production of small-sized chip electronic components. The chip electronic component comprises a substrate, and side electrodes disposed at the end portions of the substrate. The lightness of an entire surface of the side electrode is not more than 6 as defined in JIS-Z8721.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: January 9, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuru Harada, Kazunori Omoya, Masato Hashimoto, Akio Fukuoka
  • Patent number: 7129814
    Abstract: A chip resistor includes a metal resistor element having a flat lower surface. The lower surface is formed with two electrodes spaced from each other, and an insulating resin film is formed between these electrodes. Each of the electrodes partially overlaps the insulating film so that a portion of the insulating film is inserted between each of the electrodes and the lower surface of the resistor element.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: October 31, 2006
    Assignee: Rohm Co., Ltd.
    Inventor: Torayuki Tsukada
  • Patent number: 7119657
    Abstract: A semiconductor device includes a polysilicon resistor that can suppress variations in resistance value in environments with an ambient temperature higher than room temperature. The resistance value Rcon of a polysilicon contact is reduced to 2% or less of the sum of the resistance value Rcon of the polysilicon contact and the resistance value Rpoly of a polysilicon resistor. Hence, a semiconductor device that is not significantly affected by a variation in the resistance of the polysilicon contact is realized. This device suppresses variations in resistance value in environments with an ambient temperature higher than room temperature.
    Type: Grant
    Filed: April 10, 2002
    Date of Patent: October 10, 2006
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Katsumichi Ueyanagi, Mutsuo Nishikawa, Katsuyuki Uematsu
  • Patent number: 7103965
    Abstract: The invention relates to a method of making a chip resistor using a material substrate for which are set a plurality of first cutting lines extending in a first direction and a plurality of second cutting lines extending in a second direction perpendicular to the first direction. The method includes an upper electrode forming step A for forming a thick upper conductor layer on the upper surface of the substrate by printing and baking a metal organic paste, a lower electrode forming step B for forming a thick lower conductor layer on the lower surface of the substrate by printing and baking metal organic paste, and a resistor element forming step C for forming a thin resistor layer by depositing a resistor material on the upper surface of the substrate. Preferably, the upper and the lower surfaces of the material substrate are flat.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: September 12, 2006
    Assignee: Rohm Co., Ltd.
    Inventor: Masanori Tanimura
  • Patent number: 7098768
    Abstract: A chip resistor includes: an insulating chip substrate 11 having an upper surface formed with a resistive film 12 and a pair of left and right upper electrodes 13 at two ends thereof; a cover coat 14 covering the resistive film; auxiliary upper electrodes 15 formed on upper surfaces of the upper electrodes 13 to overlap the cover coat 14; a left and a right side electrodes 16 formed on a left and a right end surfaces 11a of the insulating substrate 11; and metal plate layers formed on surfaces of the auxiliary upper electrodes and side electrodes. The cover coat 14 is formed with an uppermost over coat 19 covering a region where the auxiliary upper electrodes 15 overlap the cover coat 14, whereby the upper electrodes 13 and the auxiliary upper electrodes 15 are protected from migration caused by sulfur gases.
    Type: Grant
    Filed: November 28, 2002
    Date of Patent: August 29, 2006
    Assignee: Rohm Co., Ltd.
    Inventor: Masato Doi
  • Patent number: 7088217
    Abstract: A shunt resistor of the present invention has a configuration including a substantially planar resistor (10) having a predetermined resistance value; a first fixed terminal plate (20) that has one end portion (21) connected to an edge of the resistor (10); and a second fixed terminal plate (30) that has one end portion (31) connected to the other edge of the resistor (10), that has a portion in the vicinity of the end portion (31) which is bent substantially in the shape of the letter ā€œUā€, and that opposes at least a portion of the first fixed terminal plate (20), wherein a plurality of terminal tabs (12) for taking a voltage drop in the resistor (10) as a voltage signal is provided protrusive from a side edge of the resistor (10), and lead wires (40) are connected to the terminal tabs (12).
    Type: Grant
    Filed: January 10, 2002
    Date of Patent: August 8, 2006
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Hideki Enomoto, Riichi Uotome, Narutoshi Hoshino
  • Patent number: 7084733
    Abstract: In chip electronic components, the application state of conductive paste that makes side electrodes can be optically distinguished in the production of small-sized chip electronic components. The chip electronic component comprises a substrate, and side electrodes disposed at the end portions of the substrate. The lightness of an entire surface of the side electrode is not more than 6 as defined in JIS-Z8721.
    Type: Grant
    Filed: January 24, 2002
    Date of Patent: August 1, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuru Harada, Kazunori Omoya, Masato Hashimoto, Akio Fukuoka
  • Patent number: 7071811
    Abstract: The present invention provides a diffusion resistor that is formed in the substrate. A diffusion region is formed within the substrate that contains a first and second contact region. These contact regions extend downward from the surface of the substrate. A third contact is located within the diffusion region between the first and second contacts. This contact also extends downward from the surface of the substrate. These contacts are connected to metal layers. The first and second contacts form the two ends of the diffusion resistor. The third contact forms a Schottky diode such that application of a voltage to this contact forms a depletion region within the diffusion region. The depletion region changes in size depending on the voltage applied to the third contact to change the resistance of the depletion resistor.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: July 4, 2006
    Assignee: LSI Logic Corporation
    Inventors: Sean Christopher Erickson, Jonathan Alan Shaw, Jay Tatsuo Fukumoto
  • Patent number: 7057490
    Abstract: A resistor having reliability in electrical connection between an upper surface electrode and a side face electrode, and in bonding strength between a first thin film and a second thin film is provided. The resistor includes upper surface electrodes formed on a main surface a substrate and side face electrodes disposed to side faces of the substrate and connected electrically to the pair of upper surface electrodes, respectively. The upper surface electrode includes a first upper surface electrode layer and a bonding layer overlying the first upper surface electrode layer. The side face electrode includes a first thin film disposed to a side face of the substrate, a second thin film composed of copper-base alloy film and connected electrically to the first thin film, a first plating film formed by nickel plating for covering the second thin film, and a second plating film covering the first plating film.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: June 6, 2006
    Assignee: Matsushita Electric Industrial Co. Ltd.
    Inventors: Masato Hashimoto, Akio Fukuoka, Toshiki Matsukawa, Hiroyuki Saikawa, Tsutomu Nakanishi
  • Patent number: 7049927
    Abstract: A resistance substrate includes a substrate member, two conductive elements provided on the substrate member, and a resistor element provided on the substrate member, the resistor element electrically connecting the conductive elements to each other. Each of the conductive elements includes an exposed portion of a metal terminal and an electrode film, the exposed portion of the metal terminal being exposed on a surface of the substrate member and the electrode film being electrically connected to the exposed portion and extending along a direction in which the resistor element extends. Each of the conductive elements is covered by an insulator film such that an exposed portion of the electrode film is left uncovered. The resistor element is electrically connected to the exposed portions of the electrode films at both ends thereof.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: May 23, 2006
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Naotake Hasegawa
  • Patent number: RE39660
    Abstract: An electrical resistor has a surface mounted four terminal current sensor of a very low resistance value and capable of handling short pulses of high power. It comprises a flat metal late, 1 to 50 mils thick, of an alloy of high electrical resistivity, to which are welded, on two opposite sides, two flat metal plates of very high electrical conductivity which serve as terminations for electrical interconnection. A slot is cut, from the outside edge toward the center, into each of the two termination plates which divides them into a wide pad for connection of current carrying wires and a narrow one for voltage sensing. The depth of the slots is optimized to get the best stability of resistance readings with changing ambient temperature and under influence of the self-heating effect.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: May 29, 2007
    Assignee: Vishay Dale Electronics, Inc.
    Inventors: Joseph Szwarc, Joel J. Smejkal