Terminal Coated On Patents (Class 338/309)
  • Publication number: 20020125987
    Abstract: A resistance layer, a buffering layer and a protective layer are formed in a predetermined area of a dielectric layer. An insulating layer is formed on the semiconductor wafer to cover the upper and side surfaces of the protective layer, the side surfaces of the buffering layer and the resistance layer, and the surface of the dielectric layer outside of the predetermined area. Two openings extending down to the protective layer are formed by performing a dry-etching process on the insulating layer. Two openings extending down to the buffering layer are formed by performing a first wet-etching process on the protective layer below the two openings of the insulating layer. Two openings extending down to the resistance layer are formed by performing a second wet-etching process on the buffering layer below the two openings of the protective layer.
    Type: Application
    Filed: March 8, 2001
    Publication date: September 12, 2002
    Inventor: Jia-Sheng Lee
  • Publication number: 20020125986
    Abstract: A high density resistor structure and a method for forming the structure are disclosed. The high density resistor structure can be constructed by an electrically insulative substrate; a refractory metal-silicon-nitrogen layer deposited on the top surface; and at least one resistor element patterned in the refractory metal-silicon-nitrogen layer in a plane parallel to the top surface. The method can be carried out by first providing the electrically insulative semiconductor substrate or a glass substrate, then sputter-depositing a TaSiN layer having a thickness between 200 Å and 2000 Å on top of the substrate; and then forming by a reactive ion etching technique at least one resistor element in the TaSiN film in a plane that is parallel to the top surface of the substrate.
    Type: Application
    Filed: January 12, 2001
    Publication date: September 12, 2002
    Applicant: International Business Machines Corporation
    Inventors: Cyril Cabral, Lawrence Clevenger, Louis Lu-Chen Hsu, Keith Kwong Hon Wong
  • Publication number: 20020118094
    Abstract: A resistor includes an insulating substrate, a resistive layer formed on the substrate, electrodes connected to the resistive layer, and a protection cover overlapping with the resistive layer. The resistive layer is made of tantalum. The resistive layer is processed into a predetermined pattern by photolithography in which a photo resist layer is formed by the spin coating method applied to a circular mother substrate.
    Type: Application
    Filed: April 8, 2002
    Publication date: August 29, 2002
    Inventors: Shigeru Kambara, Toshihiro Teramae
  • Patent number: 6429533
    Abstract: An electronic device includes a first conductive polymer layer sandwiched between a first external metal foil electrode and a first internal metal foil electrode, a second conductive polymer layer sandwiched between a second internal metal foil electrode and a second external metal foil electrode, a layer of fiber-reinforced epoxy resin bonding the first and second internal electrodes together, a first terminal providing electrical contact between the first internal electrode and the second external electrode, and a second terminal providing electrical contact between the second internal electrode and the first external electrode. In a preferred embodiment, the polymer layers exhibit PTC behavior, and the terminals are formed by a solder layer applied over a plated layer of conductive metal. Insulative layers are preferably provided on the external electrodes, and located so as to insulate the first and second terminals from each other.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: August 6, 2002
    Assignee: Bourns Inc.
    Inventors: Wen Been Li, Kun Ming Yang
  • Publication number: 20020101329
    Abstract: A method and apparatus for an electronic component package of a passive component using wafer level processing is provided. Posts are formed on the active side of the substrate of an electronic component. A conductive layer leads the contact areas of the electronic component to the tops of the posts. The conductive layer on the top of the posts acting as leads, attaching to traces on a printed circuit board.
    Type: Application
    Filed: February 11, 2002
    Publication date: August 1, 2002
    Inventors: Phil P. Marcoux, James L. Young, Changsheng Chen
  • Publication number: 20020097137
    Abstract: A fast heat rise resistor comprising a substrate, a foil bridge on the surface of the substrate, the foil bridge having an elevated portion and a contact portion, the elevated portion above the substrate, the contact portion in contact with the substrate, a conductive layer attached to the contact portion of said foil bridge. The activation energy and/or response time is reduced as the foil bridge is suspended over the substrate. Another aspect of the invention include a method of manufacturing the foil bridge and application to autoignition vehicle airbags.
    Type: Application
    Filed: January 19, 2001
    Publication date: July 25, 2002
    Inventors: George V. Gerber, Anthony E. Troianello, Haim Goldberger
  • Publication number: 20020097138
    Abstract: A fast heat rise resistor comprising a substrate, a foil bridge on the surface of the substrate, the foil bridge having an elevated portion and a contact portion, the elevated portion above the substrate, the contact portion in contact with the substrate, a conductive layer attached to the contact portion of said foil bridge. The activation energy and/or response time is reduced as the foil bridge is suspended over the substrate. Another aspect of the invention include a method of manufacturing the foil bridge and application to autoignition vehicle airbags.
    Type: Application
    Filed: February 20, 2002
    Publication date: July 25, 2002
    Inventors: George V. Gerber, Anthony E. Troianello, Haim Goldberger
  • Publication number: 20020097139
    Abstract: A fast heat rise resistor comprising a substrate, a foil bridge on the surface of the substrate, the foil bridge having an elevated portion and a contact portion, the elevated portion above the substrate, the contact portion in contact with the substrate, a conductive layer attached to the contact portion of said foil bridge. The activation energy and/or response time is reduced as the foil bridge is suspended over the substrate. Another aspect of the invention include a method of manufacturing the foil bridge and application to autoignition vehicle airbags.
    Type: Application
    Filed: February 20, 2002
    Publication date: July 25, 2002
    Inventors: George V. Gerber, Anthony E. Troianello, Haim Goldberger
  • Publication number: 20020093417
    Abstract: An electrical resistor including a resistance zone and connections that are connected to electrically conductive supply leads. The supply leads are designed as busbars that run parallel to one another and are also intermeshed in one another or coaxial and between which is arranged an electrically insulating layer that is a good thermal conductor. The construction including the resistor and the supply leads is surrounded by a layer that is a good thermal conductor.
    Type: Application
    Filed: October 22, 2001
    Publication date: July 18, 2002
    Inventor: Reiner Gross
  • Patent number: 6414585
    Abstract: A method and apparatus for an electronic component package of a passive component using wafer level processing is provided. Posts are formed on the active side of the substrate of an electronic component. A conductive layer leads the contact areas of the electronic component to the tops of the posts. The conductive layer on the top of the posts acting as leads, attaching to traces on a printed circuit board.
    Type: Grant
    Filed: May 13, 1997
    Date of Patent: July 2, 2002
    Assignee: Chipscale, Inc.
    Inventors: Phil P. Marcoux, James L. Young, Changsheng Chen
  • Patent number: 6411109
    Abstract: A lug with relatively small resistance is provided that allows current to be determined between a source and a load by measuring the voltage drop across the lug. The voltage drop is sufficient to be above the electronic noise, and yet the resistance of the lug is low enough so that the heat produced by current flow is small compared with the heat generated by the source. The material comprising the lug is of a type and strength to be readily manufactured, and its resistivity varies by a relatively small amount with temperature.
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: June 25, 2002
    Assignee: Hamilton Sundstrand Corporation
    Inventor: Michael Hanson
  • Patent number: 6404324
    Abstract: A resistor having a generally planar substrate with a resistive element located on each side of the substrate and a plurality of terminals for connecting opposing portions of each of the resistive elements to an electronic circuit. The resistive elements have substantially equal dimensions and resistive properties such that they have substantially equal resistance values and exhibit substantially equal current densities for any given applied voltage. The substrate can be a ceramic-coated metal core with the resistive elements silk-screened onto opposite sides of the substrate. The resistive elements have a substantially uniform thickness so that they exhibit a uniform current density when subjected to an applied voltage. With this dual resistive layer design, thermal bending of the resistor due to differential thermal expansion at one of the ceramic layers is substantially offset by thermal bending due to differential thermal expansion at the other ceramic layer.
    Type: Grant
    Filed: September 7, 1999
    Date of Patent: June 11, 2002
    Assignee: General Motors Corporation
    Inventors: David B. Witt, Scott E. Crawford
  • Patent number: 6404331
    Abstract: A fuel-level indicator for a motor vehicle fuel tank includes an insulating base carrier; an electrically conducting slide track mounted on the base carrier and containing at least one metal; and a movable transmitter arm carrying a slide contact and being in sliding engagement with the slide track. The slide track is free from silver.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: June 11, 2002
    Assignee: Alfmeier Präzision AG Baugruppen und System1ösungen
    Inventors: Roland Hüttinger, Jachin Schwalbe
  • Patent number: 6400252
    Abstract: A resistor has a resistor body of polycrystalline silicon and electric contact regions arranged on and/or in the resistor body, so that a resistor part is formed between the contact regions, which gives the resistor its resistance. The material in the resistor body is doped with for example boron to define its resistance. To give the resistor a good long term stability the resistor part is protected by one or more oxide based blocking layers produced from transition metals. These blocking layers can prevent movable kinds of atoms such as hydrogen from reaching the unsaturated bonds in the polysilicon. Such movable kinds of atoms can for example exist in passivation layers located outermost in an integrated electronic circuit in which the resistor is included. The blocking layers can be produced from layers having 30% titanium and 70% tungsten, which are oxidized using hydrogen peroxide.
    Type: Grant
    Filed: February 14, 2000
    Date of Patent: June 4, 2002
    Assignee: Telefonaktiebolaget LM Ericsson
    Inventors: Ulf Smith, Matts Rydberg
  • Patent number: 6396387
    Abstract: In thin layer resistors comprising a patch of a layer of resistive material on an insulating substrate and means at spaced apart locations on the patch, the resistive material is formed of 95 to 99.5 wt % of a zero valence metal and between 5 and 0.5 wt % of a dielectric material.
    Type: Grant
    Filed: April 13, 1999
    Date of Patent: May 28, 2002
    Assignee: MicroCoating Technologies, Inc.
    Inventors: Andrew T. Hunt, Wen-Yi Lin, Shara S. Shoup
  • Publication number: 20020050921
    Abstract: The invention relates to a circuit arrangement comprising an SMD-component (1), in particular a temperature sensor with a thermistor element (1), having two electroconductive contacts (2a, 2b), which are each conductively connected to a conductor track (3a, 3b) provided on a substrate (4). A firm, mechanical connection as well as a good electroconductive connection between the SMD-component and the conductor tracks is achieved in that the contacts (2a, 2b) are each made of a metal-glass layer (6) forming the connection to the conductor tracks (3a, 3b), and in that the metal-glass layer (6) is manufactured by heating a glass particle-containing metal until melting or softening of the glass particles occurs. The invention also relates to a method of manufacturing a temperature sensor and to a method of manufacturing such a connection.
    Type: Application
    Filed: August 24, 1998
    Publication date: May 2, 2002
    Inventors: WILHELM A. GROEN, VALERIE R.C.M.J. SILLEN
  • Patent number: 6362723
    Abstract: A chip thermistor is produced by first preparing green sheets containing a thermistor ceramic material and an organic binder, then applying a resistor paste on one or more of these green sheets and an inner electrode paste on some others, and forming a layered structure by stacking and compressing together specified numbers of these green sheets. The layered structure is then subjected to a firing process and outer electrodes are formed on oppositely facing pair of outer end surfaces of the layered structure. The chip thermistor thus produced has a main body of a thermistor ceramic material having a specified resistance-temperature characteristic, a pair of outer electrodes on its end surfaces, at least one resistor having resistance greater than 1&OHgr;, and at least one pair of inner electrodes opposite each other and separated from each other with the thermistor ceramic material in between.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: March 26, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Masahiko Kawase
  • Patent number: 6359546
    Abstract: A chip device and a manufacturing method therefor are disclosed, in which the resistivity of the chip resistor device is constantly maintained even without using silver for lowering the self resistance in portions other than the upper electrode, thereby curtailing the manufacturing cost of the chip resistor. The chip resistor device 1 includes a chip block 10 having an upper face 12 and a pair of mutually oppositely facing side faces 14. An electrode part 20 has an upper electrode 22 formed on the upper face 12 of the chip block 10, and a side electrode 24 formed on the side faces 14 of the chip block 10. A special electrical property layer 30 is connected to the upper electrode 22 of the chip block 10. A protecting layer 40 is formed upon the special electrical property layer 30 to protect it. A terminal electrode layer 50 is formed on the electrode part 20 of the chip block 10, and a terminal connection part S is necessarily provided to form a signal bypassing path.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: March 19, 2002
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Soon Hee Oh
  • Patent number: 6356184
    Abstract: A resistor chip has a pair of mutually separated upper-surface electrodes on the upper surface of an electrically insulating substrate in a form of a chip, an resistor film having end portions which are each over a corresponding one of these upper-surface electrodes, a cover coating made of a glass material which is over a portion of this resistor film, and a pair of plated metallic layers each over a corresponding one of end surfaces of the substrate. Edge sections of the insulator film over the upper-surface electrodes are not covered by the cover coating and are each directly covered by one of these plated metallic layers.
    Type: Grant
    Filed: November 3, 1999
    Date of Patent: March 12, 2002
    Assignee: Rohm Co., Ltd.
    Inventors: Masato Doi, Susumu Okuno
  • Patent number: 6348852
    Abstract: The PTC thermistor chip of the present invention comprises a conductive polymer having PTC properties, a first outer electrode, a second outer layer electrode, not less than one inner electrode sandwiched between the conductive polymer, a first electrode electrically directly coupled with the first outer electrode, and a second electrode disposed electrically independently from the first electrode. When counting from one of the inner electrodes closest to the first outer layer electrode, and defining the inner layer electrode in a “n”th position as the “n”th inner electrode, the odd-numbered inner layer electrodes are directly coupled with the second electrode and the even-numbered inner layer electrodes, with the first electrode. In this PTC thermistor, the cross sections where the odd-numbered and even numbered inner electrodes are respectively in contact with the second and first electrodes are thicker than the other sections.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: February 19, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Junji Kojima, Kiyoshi Ikeuchi, Takashi Ikeda, Koichi Morimoto, Toshiyuki Iwao
  • Patent number: 6344973
    Abstract: The invention relates to a power module with a circuit arrangement provided with active semiconductor components and passive components and with a circuit substrate, whereby at least a portion of the active semiconductor components are soldered onto a DCB substrate and at least a portion of the passive components are printed in thick film technology on at least one ceramic substrate. The upper side of the DCB substrate is structured to form track conductors and connecting surfaces for receiving the active semiconductor components and passive components of the circuit arrangement. On the ceramic substrate, for each passive component, a first print layer is printed in thick film technology and at least one contact surface as additional print layer laterally adjoining the first print layer.
    Type: Grant
    Filed: July 13, 1999
    Date of Patent: February 5, 2002
    Assignee: Alcatel
    Inventors: Hans-Peter Feustel, Friedrich Loskarn, Reinhard Rückert
  • Patent number: 6326677
    Abstract: A ball grid array resistor network has a substrate that has top and bottom surfaces. Resistors are disposed on the top surface. Conductors are disposed on the top surface, and each conductor is electrically connected to an end of each resistor. Vias extend through the substrate and are electrically connected to the conductors. Solder spheres are disposed on the bottom surface, and are electrically connected to the vias. A cover coat is disposed over the conductors and resistors. In an alternative embodiment, the vias are eliminated and the resistor network is formed on the bottom surface of the substrate. The resistor network provides a high density of resistors per unit area.
    Type: Grant
    Filed: September 4, 1998
    Date of Patent: December 4, 2001
    Assignee: CTS Corporation
    Inventors: Terry R. Bloom, Stephen W. Burry, Lewis L. Seffernick, Robert M. VandenBoom, John Zdanys, Jr.
  • Patent number: 6314637
    Abstract: The invention relates to a chip resistor which is used as a circuit part for various electric apparatuses. The object of the invention is to realize a low resistance and a low TCR, and also high accuracy and high reliability. In order to achieve the object, a chip resistor is configured so as to have: a substrate; a resistance layer which is formed on at least one face of the substrate and which is made of a copper nickel alloy; upper-face electrode layers which make surface contact with the upper faces of both the end portions of the resistance layer; and end-face electrodes which are formed so as to cover the upper-face electrode layers. Since the bonding between the resistance layer and the upper-face electrode layers is conducted by metal-to-metal bonding, particularly, impurities which may affect the Properties do not exist in the interface. As a result, it is possible to realize a chip resistor which is excellent in heat resistance, and which has a low resistance and a low TCR.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: November 13, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Suzushi Kimura, Koji Shimoyama, Naotugu Yoneda, Keiichi Nakao
  • Patent number: 6317023
    Abstract: The invention is directed to a method of embedding thick film passive components on an organic substrate wherein a flexible metallic substrate has a conductive paste underprint applied thereon. The method comprises the following steps: applying a conductor paste underprint onto a flexible metallic substrate; firing the preceding article; applying at least one passive component paste onto the underprint; firing the preceding article; and applying the passive component side of the metallic substrate onto at least one side of an organic layer which is at least partially coated with an adhesive layer wherein the passive component side of the article is embedded into the adhesive layer.
    Type: Grant
    Filed: October 15, 1999
    Date of Patent: November 13, 2001
    Assignee: E. I. du Pont de Nemours and Company
    Inventor: John James Felten
  • Patent number: 6310536
    Abstract: A printed circuit board having resistors formed therein. A conductive layer composed of two different metals is provided on top of an insulating layer in a printed circuit board. The first metal layer is highly conductive and the second metal layer is highly resistive. For a major portion of the layer, both layers are connected electrically in parallel so that they provide a highly conductive path. At selected locations throughout the printed circuit board, the highly conductive metal is removed providing only the high resistivity metal to act as a resistor between selected locations in the conductive layer. Many resistors are formed at the same time, thus providing ease of fabrication and precision in resistor values across the entire printed circuit board. Following the formation of the resistor, additional insulating and conductive layers are formed to complete the printed circuit board.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: October 30, 2001
    Assignee: Cray Inc.
    Inventor: Steven V. R. Hellriegel
  • Patent number: 6304167
    Abstract: A resistor for use in high density printed circuit board, having low current noise and improved resistance accuracy, and a method of manufacturing the resistor. A resistor of the present invention includes a substrate, a pair of upper-surface electrode layers formed on the end sections of the upper surface of said substrate, a resistor layer formed so that the layer is connected electrically to said upper-surface electrode layers, a first trimming groove formed by cutting said resistor layer, a resistance restoring layer which is formed to cover at least said first trimming groove, a second trimming groove formed by cutting the resistance layer and resistance restoring layer, and a protective layer provided to cover at least the resistance layer and second trimming groove. In this way, the resistors having a superior property in both the current noise characteristic and the resistance accuracy are obtained.
    Type: Grant
    Filed: April 13, 2000
    Date of Patent: October 16, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Shogo Nakayama
  • Publication number: 20010026211
    Abstract: The invention provides a production method capable of forming a thin film resistance element having a thickness and a shape controlled in a high accuracy in a printed circuit board (core material). The production method of a thin film resistance element formed on a printed circuit board, has the steps of forming a thin film resistance layer having a predetermined thickness on the printed circuit board through an insulation layer by a dry process used in producing a semiconductor, forming an electrically conductive layer on the thin resistance layer, and etching the electrically conductive layer selectively so as to make, at least, a pair of electrically conductive pads, resulting in the thin film resistance element having a predetermined value of resistivity between the pair of electrically conductive pads. Thereby, it is possible to form the thin film resistance element having a thickness and a shape controlled in a high accuracy on the printed circuit board (core material).
    Type: Application
    Filed: February 27, 2001
    Publication date: October 4, 2001
    Inventors: Motoshi Shindoh, Keiji Segawa, Mitsuru Otsuki
  • Patent number: 6288627
    Abstract: A resistor may be embedded into a substrate. A portion of the resistor may be exposed, by segmenting the substrate, for instance, so that the resistor may be trimmed to a desired resistance level. Alternatively, a portion of a resistor may be embedded into a substrate, with another portion of the resistor being disposed on the outer surface of the substrate. The portion of the resistor on the outer surface may be trimmed to adjust the resistance of the resistor to a desired level.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: September 11, 2001
    Assignee: Intermedics Inc.
    Inventor: Kenneth R. Ulmer
  • Publication number: 20010019301
    Abstract: A thin-film resistor that enables a pattern to be simply formed by means of wet etching, that has an excellent resistance temperature characteristic, and that can be easily manufactured, and a method for manufacturing this thin-film resistor, as well as a wiring substrate with this thin-film resistor formed therein. A thin resistor film according to this invention has a structure in which crystal grains deposit in the matrix of amorphous titanium nitride. The thin resistor film is formed on a substrate. The crystal grains includes at least one of crystal titanium nitride and crystal titanium. The thin resistor film can be manufactured using a simple process and can provide a wide range of resistance values with a small tolerance and a temperature coefficient of resistance close to zero.
    Type: Application
    Filed: June 7, 1999
    Publication date: September 6, 2001
    Inventors: AKINOBU SHIBUYA, KOJI MATSUI
  • Patent number: 6278356
    Abstract: A flat, built-in resistor and capacitor has a substrate (10) made of dielectric material; a copper layer (12) formed on each surface of the substrate (10) and having an etched image (30) formed in each of the copper layers (12); a dielectric material layer (40) printed onto the copper layer (12) and filling up the etched image; and a resistance layer (50) printed onto the copper layer (12) and the dielectric material layer (40).
    Type: Grant
    Filed: May 17, 2000
    Date of Patent: August 21, 2001
    Assignee: Compeq Manufacturing Company Limited
    Inventors: Wen-Yen Lin, Lin-Yeh Chen, Chin-Chi Chang, Shih-Ting Huang
  • Patent number: 6256866
    Abstract: A method of manufacturing a printed circuit board with a polymer thick-film (PTF) resistor whose dimensions can be defined with improved precision by providing a circuit board construction having a planar surface where the resistor is to be deposited. To achieve the desired board construction, the interconnect for the resistor is pattern plated using a permanent photodielectric layer as a plating mask instead of a sacrificial plating resist. The interconnect can be patterned before or after the PTF resistor ink is printed. The x and z dimensions (width and thickness, respectively) of the resistor are determined by the deposition process, while the y dimension (electrical length) is accurately determined by copper terminations.
    Type: Grant
    Filed: May 11, 1999
    Date of Patent: July 10, 2001
    Assignee: Motorola, Inc.
    Inventor: Gregory Dunn
  • Patent number: 6253446
    Abstract: A fault current fusing resistor, comprising a substrate on which there is a line of resistive film formed of metal and glass in a conductive film, which line is closely confined by containing and sealing substances to prevent venting of vapor from the line during the fusing caused by an electrical fault condition.
    Type: Grant
    Filed: January 25, 1999
    Date of Patent: July 3, 2001
    Inventor: Richard E. Caddock, Jr.
  • Patent number: 6242999
    Abstract: A pair of upper electrode layers 12, connected to resistor layer 14, is formed with a gold system electro-conductive material containing glass frit on the side portion towards the edge of the upper surface of substrate 11. The adhesive strength of which electrode layer to the substrate 11 is strong enough and the electrode layer withstands a thermal stress and a corrosive environment. A resistor thus manufactured maintains its superior electrical characteristics with a high operational reliability even in the harsh operating environment where there is a thermal amplitude lasting for a long term, in a corrosive atmosphere, etc.
    Type: Grant
    Filed: January 20, 1999
    Date of Patent: June 5, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shogo Nakayama, Seiji Tsuda, Akio Fukuoka
  • Patent number: 6232867
    Abstract: A method of fabricating a monolithic chip varistor includes the steps of preparing a varistor body including a plurality of varistor layers and at least one pair of internal electrodes; forming a first layer for each of a pair of external electrodes by applying a metal component and a glass component to an exterior portion of the varistor body, followed by heat treatment; forming a second layer for the external electrode on the first layer by applying a glass component, followed by heat treatment; forming a third layer for the external electrode on the second layer by applying a glass component that is different from the glass component used for forming the second layer, followed by heat treatment; forming a fourth layer for the external electrode on the third layer by applying a metal component that is different from the metal component used for forming the first layer, followed by heat treatment under the same heat treatment conditions as those used for the formation of the first layer; and forming a fifth
    Type: Grant
    Filed: August 22, 2000
    Date of Patent: May 15, 2001
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoshikazu Yoshida, Toru Tominaga, Tadashi Morimoto
  • Publication number: 20010000298
    Abstract: A temperature-dependent measuring resistance with low mass and thereby rapid response time has a conductor path provided with at least two connection contact pads. The conductor path is applied to a metal substrate with an insulation layer (membrane) situated thereon. A portion of the conductor path spans a recess of the substrate in a bridge-like manner. The conductor path is selectively covered by a passivation layer up to its connection contact pads.
    Type: Application
    Filed: December 7, 2000
    Publication date: April 19, 2001
    Inventors: Karlheinz Wienand, Karlheinz Ullrich, Stefan Dietmann
  • Publication number: 20010000215
    Abstract: A chip device and a manufacturing method therefor are disclosed, in which the resistivity of the chip resistor device is constantly maintained even without using silver for lowering the self resistance in portions other than the upper electrode, thereby curtailing the manufacturing cost of the chip resistor. The chip resistor device 1 includes a chip block 10 having an upper face 12 and a pair of mutually oppositely facing side faces 14. An electrode part 20 has an upper electrode 22 formed on the upper face 12 of the chip block 10, and a side electrode 24 formed on the side faces 14 of the chip block 10. A special electrical property layer 30 is connected to the upper electrode 22 of the chip block 10. A protecting layer 40 is formed upon the special electrical property layer 30 to protect it. A terminal electrode layer 50 is formed on the electrode part 20 of the chip block 10, and a terminal connection part S is necessarily provided to form a signal bypassing path.
    Type: Application
    Filed: December 5, 2000
    Publication date: April 12, 2001
    Inventor: Soon Hee Oh
  • Publication number: 20010000122
    Abstract: An integrated circuit containing a resistor and the resistor per se. The circuit includes a substrate (2) , a semiconductor resistor (3) on the substrate and a layer of electrically insulating material (5) disposed over the substrate and the semiconductor resistor having at least one contact (11, 13, 15) extending therethrough to the semiconductor resistor, the contact having an electrical path therein extending to and forming an interface with an end portion of the semiconductor resistor. The semiconductor resistor has a semiconductor resistor body, preferably of doped polysilicon, having one of a positive or negative temperature coefficient of resistance and a resistor head. The resistor head consists essentially of the electrical path which is metal interconnect, the contacts and then interface to and from the resistor body and in contact with the resistor body, the resistor head having the other of a positive or negative temperature coefficient of resistance.
    Type: Application
    Filed: December 6, 2000
    Publication date: April 5, 2001
    Inventors: Greg C. Baldwin, Alwin J. Tsao
  • Patent number: 6211769
    Abstract: An integrated circuit containing a resistor and the resistor per se. The circuit includes a substrate (2), a semiconductor resistor (3) on the substrate and a layer of electrically insulating material (5) disposed over the substrate and the semiconductor resistor having at least one contact (11, 13, 15) extending therethrough to the semiconductor resistor, the contact having an electrical path therein extending to and forming an interface with an end portion of the semiconductor resistor. The semiconductor resistor has a semiconductor resistor body, preferably of doped polysilicon, having one of a positive or negative temperature coefficient of resistance and a resistor head. The resistor head consists essentially of the electrical path which is metal interconnect, the contacts and then interface to and from the resistor body and in contact with the resistor body, the resistor head having the other of a positive or negative temperature coefficient of resistance.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: April 3, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Greg C. Baldwin, Alwin J. Tsao
  • Patent number: 6208234
    Abstract: In thin layer resistors comprising a patch of a layer of resistive material on an insulating substrate and means at spaced apart locations on the patch, the resistive material is formed of 95 to 99.5 wt % of a zero valence metal and between 5 and 0.5 wt % of a dielectric material.
    Type: Grant
    Filed: April 29, 1998
    Date of Patent: March 27, 2001
    Assignee: Morton International
    Inventors: Andrew T. Hunt, Wen-Yi Lin, Shara S. Shoup
  • Patent number: 6172591
    Abstract: A conductive polymer device has three or more conductive polymer layers sandwiched between two external electrodes and two or more internal electrodes. The electrodes are staggered to create a first set of electrodes, in contact with a first terminal, alternating with a second set of electrodes in contact with a second terminal.
    Type: Grant
    Filed: March 5, 1998
    Date of Patent: January 9, 2001
    Assignee: Bourns, Inc.
    Inventor: Andrew Brian Barrett
  • Patent number: 6166620
    Abstract: A resistance wiring board having a cavity disposed on an insulated substrate, a resistance disposed in the cavity, a protective film disposed on a top face of the resistance, and electrodes electrically connected at near both ends of the resistance, wherein surfaces of the electrodes and a surface of the protective film are the same level as or lower than a surface of the wiring board. A method for manufacturing a resistance wiring board comprising the steps of forming a green sheet, forming an electrode pattern on the green sheet, forming a dented pattern on the green sheet, firing the green sheet, forming a resistance by filling a resistance material in the dent of the green sheet, and forming a protective film on a top face of the resistance.
    Type: Grant
    Filed: April 8, 1999
    Date of Patent: December 26, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tsutomu Inuzuka, Satoshi Tomioka, Shigeo Furukawa, Tsuyoshi Himori, Suzushi Kimura
  • Patent number: 6153256
    Abstract: A chip resistor includes a spaced pair of main top electrodes on an insulating substrate, a resistor layer formed on the insulating substrate to bridge between the main top electrodes, an overcoat layer formed over the resistor layer, and a pair of auxiliary top electrodes formed on the main top electrodes in contact with the overcoat layer. Each of the auxiliary top electrodes contains a glass material in addition to a metal material for integration with the overcoat layer.
    Type: Grant
    Filed: August 13, 1999
    Date of Patent: November 28, 2000
    Assignee: Rohm Co., Ltd.
    Inventors: Shigeru Kambara, Kaoru Sakai
  • Patent number: 6150920
    Abstract: The present invention is to offer a resistor which can be mounted exactly on the terminals disposed on a circuit board regardless the sides of the resistor, and to offer its manufacturing method by forming the surface of the side-electrode layer at a height higher than the surface of protection layer, or by forming the surface of the second surface electrode layer at a height higher than the surface of protection layer. By these, the resistor can be mounted exactly on the terminal of circuit board at a high yield. Furthermore, since the first surface electrode layer and the second upper electrode layer are electrically connected together through a window provided on the protection layer, a higher connection reliability can be obtained.
    Type: Grant
    Filed: May 29, 1997
    Date of Patent: November 21, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masato Hashimoto, Shogo Nakayama, Shoji Mori, Naohiro Takashima, Seiji Tsuda, Takumi Shirai
  • Patent number: 6144287
    Abstract: A chip resistor is provided which includes: an insulating substrate (1); a pair of main electrodes (2, 3) formed on a surface of the insulating substrate (1) and spaced from each other; a resistor film (4) formed on the surface of the insulating substrate (1) to bridge between the main electrodes (2, 3), the resistor film (4) being provided with a trimming groove (6) for resistor adjustment; a protective coating (5, 7, 8) formed to cover the resistor film (4); and a metal plating (13, 14) formed in electrical conduction with each of the main electrodes (2, 3). The trimming groove (6) has a width which is no less than 80 .mu.m but smaller than an interval between the main electrodes (2, 3), and is formed at an inclination angle of 20-45 degrees with respect to the substrate. Three glass coat layers are also employed.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: November 7, 2000
    Assignee: Rohm Co., Ltd.
    Inventor: Masayoshi Komeda
  • Patent number: 6140910
    Abstract: A resistor has a resistor body of polycrystalline silicon and electric terminals arranged on and/or in the resistor body. A resistor portion is thus formed between the terminals, which gives the resistor its resistance. The material in the resistor body is doped with for example boron. In order to block unsaturated silicon bonds in grain boundaries to a sufficient extent and thereby give the resistor a good long-time stability, fluorine atoms are added to the material. They are added in such a high concentration that all of the otherwise unsaturated bonds are coupled to fluorine atoms. Further, it is provided in the manufacture of the resistor that the concentration is maintained at the originally high value. When ion implanting dopants and fluorine atoms it can be accomplished by performing an annealing after implanting dopants at a high temperature and then a further annealing operation at a low temperature after the subsequent implantation of fluorine.
    Type: Grant
    Filed: June 17, 1997
    Date of Patent: October 31, 2000
    Assignee: Telefonaktiebolaget LM Ericsson
    Inventors: Ulf Smith, Matts Rydberg
  • Patent number: 6130601
    Abstract: A thick-film resistor and a process for forming the resistor to have accurate dimensions, thereby yielding a precise resistance value. The resistor generally includes an electrically resistive layer and a pair of terminals, a first of which is surrounded by the second terminal, so as to form a region therebetween that surrounds the first terminal and separates the first and second terminals. The terminals are preferably concentric, with the second terminal and the region therebetween being annular-shaped. The resistive layer electrically connects the first and second terminals to complete the resistor. Each of the terminals has a surface that is substantially parallel to an upper and/or lower surface of the resistive layer and contacts the resistive layer. The surfaces of the terminals may be embedded in the resistive layer by printing the resistive material over the terminals, or may contact the upper or lower surface of the resistive layer by locating the terminals above or below the resistive layer.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: October 10, 2000
    Assignee: Motorola, Inc.
    Inventors: Vernon L. Brown, Gregory J. Dunn, Lawrence E. Lach
  • Patent number: 6128199
    Abstract: A resistance element, a capacitor and an intermediate electrode are formed on a substrate. The capacitor and the resistance element are connected with the intermediate electrode interposed. Two terminal electrode portions are connected to each other through the intermediate electrode.
    Type: Grant
    Filed: March 16, 1998
    Date of Patent: October 3, 2000
    Assignee: Rohm Co., Ltd.
    Inventor: Shigeru Kambara
  • Patent number: 6111494
    Abstract: The invention relates to an adjustable voltage divider arrangement produced by hybrid technology, having a first current-carrying ohmic resistance layer arranged between two printed conductors and a second resistance layer, which is electrically connected to the first resistance layer and to which there is connected a third printed conductor as a pick-off electrode. A cut is made in the second resistance layer for adjusting the voltage divider so that a desired level can be picked off at the pick-off electrode.
    Type: Grant
    Filed: September 28, 1998
    Date of Patent: August 29, 2000
    Assignee: Robert Bosch GmbH
    Inventors: Werner Fischer, Friedrich Vogel, Viktor Kahr
  • Patent number: 6104277
    Abstract: A resistor having a diffused impurity region in a semiconductor substrate, an insulated gate surrounding and defining the resistor, and a pair of separated conductive contacts to the diffused region within the boundary of the insulated gate for applying and receiving current passing through the resistor.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: August 15, 2000
    Assignee: PMC-Sierra Ltd.
    Inventors: Kris Iniewski, Brian D. Gerson, Colin Harris, David LeBlanc
  • Patent number: 6097277
    Abstract: A resistor network has a substrate with top and side surfaces. Resistors are located on the side surfaces. Several side conductors are located on the side surface and are electrically connected to the resistors. Several top conductors are located on the top surface and are electrically connected to the side conductors. Each top conductor has a cavity. A solder sphere is partially located in the cavity and is electrically and mechanically connected to the top conductor by reflowed solder paste. A cover coat covers the side conductors and the resistors. The resistor network provides a high density of resistors per unit area.
    Type: Grant
    Filed: November 5, 1998
    Date of Patent: August 1, 2000
    Assignee: CTS
    Inventors: Steven N. Ginn, James N. Hufford, John Zdanys, Jr., Stephen W. Burry, Lewis L. Seffernick, Robert M. VandenBoom