Serial To Parallel Patents (Class 341/100)
  • Patent number: 10617296
    Abstract: Method and apparatus for providing a data stream generator that generates a data stream associated with a monitored analyte level, and a radio frequency logic portion operatively coupled to the data stream generator, the radio frequency logic portion configured to generate a radio frequency data stream based on the data stream generated from the data stream generator, the radio frequency logic portion further including one or more finite state machines and a plurality of discrete digital logic circuits, the one or more finite state machines configured to control the plurality of digital logic circuits to generate the radio frequency data stream for wireless communication are provided. Systems and kits incorporating the same are also provided.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: April 14, 2020
    Assignee: Abbott Diabetes Care Inc.
    Inventors: Mark Kent Sloan, Jeffery Mario Sicurello, Hung Dinh
  • Patent number: 10615549
    Abstract: System, methods, and apparatuses for indicating the configured port width for ganged-style data connectors. An exemplary apparatus comprises a plurality of connectors supporting data connections and a plurality of visual indicators. The plurality of connectors are capable of being configured with two or more of the plurality of connectors ganged together to provide increased data width connections. Each or the visual indicators is associated with one of the plurality of connectors. An electrical circuit drives the plurality of visual indicators and is configured to control the visual indicators to visually indicate a configured port width for each data connection supported by the connectors, including those formed by ganging together two or more of the connectors.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: April 7, 2020
    Assignee: Seagate Technology LLC
    Inventor: Alan John Westbury
  • Patent number: 10591542
    Abstract: Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: March 17, 2020
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10585143
    Abstract: A flip flop includes a data input, a clock input, a test chain input, a test chain output, a monitoring circuit, and an alert transmission circuit. The monitoring circuit is adapted to generate an alert if the time between arrival of a data bit and a clock edge is less than a threshold. The alert transmission circuit is adapted to apply during a monitoring phase an alert level to the test chain output in the event of an alert generated by the monitoring circuit, and to apply the alert level to the test chain output when an alert level is received at the test chain input.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: March 10, 2020
    Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Pascal Urard, Florian Cacho, Vincent Huard, Alok Kumar Tripathi
  • Patent number: 10567358
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: February 18, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Patent number: 10564773
    Abstract: Disclosed are a touch display device, a touch system, a touch master, and a communication method and, more particularly, are a touch display device, a touch system, a touch master, and a communication method which can provide a communication protocol and a communication interface based on a master-slave system in which a touch driving device operates as a touch slave and a touch controller operates as a touch master. Communication between the touch driving device and the touch controller can be accurately and rapidly performed and data transmission efficiency can increase.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: February 18, 2020
    Assignee: LG Display Co., Ltd.
    Inventor: JuneGun Chung
  • Patent number: 10530488
    Abstract: Examples disclosed herein relate to optical driver circuits. In some of the disclosed examples, an optical driver circuit includes a pre-driver circuit and a main driver circuit. The pre-driver circuit may include a pattern generator and at least one serializer to generate a main modulation signal and an inverted delayed modulation signal. The main driver circuit may include a level controller to control amplitudes of pre-emphasis on rising and falling edges of a modulation signal output and an equalization controller to transition the modulation signal output from the pre-emphasis amplitudes to main modulation amplitudes using the inverted delayed modulation signal.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 7, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Cheng Li, Di Liang, Kehan Zhu
  • Patent number: 10469451
    Abstract: Technologies for distributed detection of security anomalies include a computing device to establish a trusted relationship with a security server. The computing device reads one or more packets of at least one of an inter-virtual network function network or an inter-virtual network function component network in response to establishing the trusted relationship and performs a security threat assessment of the one or more packets. The computing device transmits the security threat assessment to the security server.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Kapil Sood, Mesut A. Ergin, John R. Fastabend, Shinae Woo, Jeffrey B. Shaw, Brian J. Skerry
  • Patent number: 10468313
    Abstract: Examples described herein include apparatuses and methods TSV resistance and short measurement in a stacked device. An example apparatus may include a chip comprising semiconductor substrate including a first surface and a second surface opposite to the first surface. The chip may include a first terminal formed above the first surface, a second terminal formed above the second surface, a buffer circuit coupled between the first and second terminals, a first through-substrate via (TSV) penetrating the semiconductor substrate, and a first switch coupled between the first terminal and the first TSV.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: November 5, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Naohisa Nishioka
  • Patent number: 10447298
    Abstract: An integrated circuit includes first and second double data rate (DDR) shift registers. A multiplexor outputs a serialized data burst by selecting between a first output stream of the first DDR shift register and a second output stream of the second DDR shift register based upon a received selector signal. The selector signal is derived from clock doubling circuitry that provides a frequency that is twice a frequency of a first clock driving the first DDR shift register.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Stefan Dietrich
  • Patent number: 10374845
    Abstract: An input signal decoding circuit for a receiver side in a mobile industry processor interface (MIPI) C-Phy is provided, which includes: an equalizer circuit module connected to a transmitter side of an MIPI via three signal wires and configured to sample signals of the signal wires to acquire a first data signal, a second data signal and a third data signal; a clock recovery circuit module configured to acquire an operating clock signal from the three data signals; a decoding circuit module configured to outputs a Flip signal, a Rotation signal and a Polarity signal based on the three data signals and the operating clock signal; and a serial-to-parallel conversion module configured to output 21-bit parallel data based on the Flip signal, the Rotation signal and the Polarity signal.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: August 6, 2019
    Assignee: LONTIUM SEMICONDUCTOR CORPORATION
    Inventors: Xiangyu Ji, Yu Chen, Cheng Tao
  • Patent number: 10313091
    Abstract: Currently, there exists low power Ethernet PHY solutions running at 10 Gbps over twin-ax cables with SFP+ connectors. However, the cost and range of these cables, along with the size of the connectors, do not match the requirements of in-vehicle networks. If the cable is replaced with a single pair of shielded or coaxial cables, a different mechanism is needed to provide bi-directional communication. Time division duplexing (TDD) can be used to emulate full duplex communication over the single pair of cables by taking turns, in time, transmitting data over the pair of cables in each direction.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: June 4, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Ahmad Chini, Mehmet V. Tazebay
  • Patent number: 10291442
    Abstract: Circuits and methods are disclosed for low-skew bonding of a plurality of data channels into a multi-lane data channel. In one embodiment, phase-measuring first-in first-out buffer circuits buffer pre-buffer parallel data signals and generate phase-measurement signals. A channel-bonding control circuit receives the phase-measurement signals and generates bit-slip control signals. Transmission bit-slip circuits slip integer numbers of bits based on the bit-slip control signals. Bypass registers may be used when the integer number of bits is greater or equal to the parallel width of a lane. In another embodiment, the channel-bonding control circuit receives the phase-measurement signals from the phase-measuring FIFO buffer circuits and generates clock-slip control signals. Clock slip circuits controllably slip parallel clock signals by integer numbers of unit intervals of a serial clock signal. Various other aspects, features, and embodiments are also disclosed.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: May 14, 2019
    Assignee: Altera Corporation
    Inventors: David W. Mendel, Han Hua Leong
  • Patent number: 10243570
    Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a charge pump, which can be utilized as a part of a clock data recovery device. Early and late signals are used as differential switching voltage signals in the charge pump. The first switch and a second switch are used for controlling the direction of the current flowing into the loop filter. Input differential voltages to the switches are being generated with an opamp negative feedback loop. The output voltage of the first switch and the second switch is used in conjunction with a resistor to generate a charge pump current. There are other embodiments as well.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: March 26, 2019
    Assignee: INPHI CORPORATION
    Inventors: Simon Forey, Parmanand Mishra, Michael Harwood, Rajasekhar Nagulapalli
  • Patent number: 10212377
    Abstract: In a solid-state image sensing apparatus of an addressing method, a clock-conversion part generates a high-speed clock signal having a frequency two times or more the frequency of a low-speed clock signal. A signal processing part receives 10-bit pixel data through a horizontal signal line, performs predetermined signal processing, and passes parallel-format data to a switching part. The switching part selects each one bit of the parallel-format 10-bit data in a predetermined sequence to output from an output terminal using the high-speed clock signal from the clock-conversion part as a switching command, thus converts the parallel-format data into serial-format data, and passes it to an output buffer. The output buffer externally outputs differential output of normal video data and inverted video data individually from output terminals. Accordingly, the problems in power consumption, noises, and unnecessary radiation are solved, and higher-speed output is achieved.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: February 19, 2019
    Assignee: Sony Corporation
    Inventor: Keiji Mabuchi
  • Patent number: 10171106
    Abstract: An integrated circuit includes first and second double data rate (DDR) shift registers. A multiplexor outputs a serialized data burst by selecting between a first output stream of the first DDR shift register and a second output stream of the second DDR shift register based upon a received selector signal. The selector signal is derived from clock doubling circuitry that provides a frequency that is twice a frequency of a first clock driving the first DDR shift register.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: January 1, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Stefan Dietrich
  • Patent number: 10165692
    Abstract: An electrical device, for example, a converter, includes: a first circuit board, which includes first circuit traces and at least one plated-through hole, a second circuit board, which includes second circuit traces and at least one connection device, a power module, and a plug-connector part. The power module is placed on the first circuit board and is connected in an electrically conductive manner to the plated-through hole with the aid of the first circuit traces, the plug-connector part is placed on the second circuit board and is connected in an electrically conductive manner to the connection device with the aid of the second circuit traces, and the plated-through hole is connected in an electrically conductive manner with the aid of a cable to the connection device.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: December 25, 2018
    Assignee: SEW-EURODRIVE GMBH & CO. KG
    Inventors: Dirk Momann, Alexander Kolbert
  • Patent number: 10142117
    Abstract: A portable information handling system selectively accepts power transferred from an external device through a port, such as USB TYPE C™ port, with one of a first or second power configuration. The first power configuration accepts power regulated by a charger of an external device and routed directly to a system bus and battery of the portable information handling system. The second power configuration accepts power regulated by an internal charger of the portable information handling system, such as a narrow voltage direct current charger.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: November 27, 2018
    Assignee: Dell Products L.P.
    Inventors: Gerald R. Pelissier, Kevin M. Turchin, III, Lawrence E. Knepper
  • Patent number: 10110334
    Abstract: Techniques efficiently serialize multiple data streams using quadrature clocks. Serializer employs first, second, third, and fourth clock signals. Serializer receives multiple data streams via registers, with each of four paths comprising a register, buffer, and switch, with registers of first and fourth paths associated with third clock signal, and registers of second and third paths associated with first clock signal, and with switches of first and fourth paths associated with first clock signal, and switches of second and third paths associated with third clock signal. Switches of first and second paths transfer respective data bits to fifth switch via another buffer, wherein fifth switch is associated with a delayed second clock signal of a time delay component (TDC). Switches of third and fourth paths transfer respective data bits to sixth switch via another buffer, wherein sixth switch is associated with a delayed fourth clock signal of TDC.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: October 23, 2018
    Assignee: MACOM CONNECTIVITY SOLUTIONS, LLC
    Inventors: Vijay Gupta, Tarun Gupta
  • Patent number: 10110237
    Abstract: A detection system and a detection method for detecting the loss of lock between a PLL reference clock signal and a PLL feedback clock signal. The detection system includes a pseudorandom bit sequence generator; a first shift register; a second shift register; a third shift register; a first synchronizer; a second synchronizer; a third synchronizer; a first comparator; a second comparator; and an alarm control unit. The method comprises the steps of, generating an n-bit wide pseudorandom bit sequence; sampling the sequence with PLL reference clock signal, PLL feedback clock signal and inverse of PLL feedback clock signal; re-sampling and re-synchronizing the sampled sequences; comparing re-sampled and re-synchronized sequence, previously sampled with PLL reference clock signal, with re-sampled and re-synchronized sequences, previously sampled PLL feedback clock signal and inverse of PLL feedback clock signal; generating a flag signal if the comparisons give no match.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: October 23, 2018
    Assignee: ASELSAN ELEKTRONIK SANAYI VE TICARET A.S.
    Inventors: Asim Kepkep, Emre Apaydin
  • Patent number: 10069508
    Abstract: Multiplexing circuitry and method for driving multiplexing circuits are provided. A circuit includes a multiplexer circuit having symmetrical data input paths driven by a half-rate clock signal and a first stage multiplexing circuit configured to provide input signals to the multiplexer circuit. The first stage multiplexing circuit is driven by quadrature clocks to generate time-shifted data.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: September 4, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Jiawen Zhang, Adesh Garg, Ali Nazemi, Jun Cao
  • Patent number: 10048949
    Abstract: Methods, devices and systems for providing a user interface in an on-demand software service environment are described. Some implementations involve receiving an indication of a component definition to instantiate. The component definition may be a portion of a component definition data structure. Such implementations may also involve instantiating the provided component, instantiating all remaining attributes of the component definition data structure to produce a component instance data structure and transmitting an intermediate representation of the indicated component to a client device. The intermediate representation may comprise a version of the component instance data structure. The intermediate representation may allow the client device to create an instance of the component in memory.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: August 14, 2018
    Assignee: salesforce.com, inc.
    Inventors: Daniel L. Pletter, Andrew Waite, Doug Chasman, James K. Mooney, James Troup
  • Patent number: 10027713
    Abstract: An information processing apparatus that makes it possible to save time and effort expended by an administrator on distribution of settings compliant with a security policy. Whether or not an application installed in the image processing apparatus to which setting values compliant with a security policy are to be distributed can be set to the settings is determined. When it is determined that the application cannot be set to the settings, whether or not the application can be set to the settings by updating thereof is determined. When the determination result indicates that the settings can be set by updating the application, the application is updated, and the settings are distributed to the image processing apparatus.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: July 17, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Shota Shimizu, Naoki Tsuchitoi, Akari Yasukawa
  • Patent number: 9995789
    Abstract: Techniques for secure remote debugging of SoCs are described. The SoC includes an intellectual property (IP) block, a microcontroller, and a fabric coupled to the IP block and the microcontroller. The IP block transmits, via the fabric, information regarding events within the IP block to the microcontroller. The microcontroller executes firmware including a network stack and a remote debugger program. Using the firmware, the microcontroller provides the event information to a device external to the SoC.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: June 12, 2018
    Assignee: Intel IP Corporation
    Inventors: Prashant Dewan, Siddhartha Chhabra
  • Patent number: 9965435
    Abstract: Aspects disclosed in the detailed description include communicating low-speed and high-speed parallel bit streams over a high-speed serial bus. In one aspect, a data transmitting circuit converts a low-speed parallel bit stream into a high-speed parallel bit stream and then serializes the converted high-speed parallel bit stream based on a high-speed reference frequency. In another aspect, a data receiving circuit recovers the low-speed parallel bit stream from the high-speed parallel bit stream if the low-speed parallel bit stream is determined to exist in the high-speed parallel bit stream.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: May 8, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: William Knox Ladd, Kevin Wayne Spears, Mark Wesley Vilas, Zhi Zhu
  • Patent number: 9959899
    Abstract: A signal conversion device includes a first converting section configured to convert a clock signal input through a first signal line, a data signal input through a second signal line, and a control signal input through a third signal line, into pulse signals including a first pulse train and a second pulse train; and a transmitting section configured to transmit the first pulse train through a fourth signal line and the second pulse train through a fifth signal line, wherein the control signal is a signal that, through a level transition, causes a control target device to switch between an active state and an inactive state, and wherein the first converting section is configured to put successive pulses into at least one of the first pulse train and the second pulse train in response to the level transition of the control signal.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: May 1, 2018
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Yukihiro Kita
  • Patent number: 9927998
    Abstract: Systems and method for reading compressed data from non-volatile storage such as an SSD device are disclosed. A logical section, e.g. page, of data includes a plurality of data blocks that are compressed such that the lengths thereof are different. A header section of the page stores headers for the data blocks and storing a length for each data block. The header section may be a codeword encoding the headers according to an error correction scheme. To read out a data block a hardware decoder requests reading of the page and transfers the header section into a hardware decoder that decodes the headers to obtain an offset for a desired data block. Without instructing reading of the page, the offset is used by the hardware decoder to request transfer of the desired data block that is then decoded and returned to a requesting device.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: March 27, 2018
    Assignee: Tidal Systems, Inc.
    Inventors: Meng Kun Lee, Priyanka Thakore
  • Patent number: 9912896
    Abstract: A latch-based parallel to serial readout circuitry includes latches connected to each other in series and to data inputs in parallel. The latches read in values from the data inputs in parallel, and then output the values serially. A readout control circuitry of the latch-based parallel to serial readout circuitry may cause the latches to read in the values in parallel by switching an active input connection of the latches to the data inputs and enabling the latches simultaneously. The readout control circuitry may cause the latches to readout the values serially by switching an active input connection of the latches to the output of a next latch and sequentially enabling the latches.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: March 6, 2018
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Ariel Ben Shem, Zvika Veig
  • Patent number: 9887707
    Abstract: The invention relates to a invention relates to a method and decoding device for receiving an input bit-stream comprising a sequence of n-bit pattern symbols as well as a unique n-bit comma symbol for synchronization, and for generating therefrom a synchronized output comprising a sequence of m-bit pattern words, with m<n. The comma symbol allows detection of bit-skip in the input bit-stream, so that the output to be synchronized to compensate for the bit-skip. The decoding device and method of decoding are particularly simple and may be applied in devices, e.g. in a beam modulator array comprising a plurality of decoding devices, and/or in a lithography system comprising such a beam modulator array, in which space and computational resources are scarce while still providing a synchronization capability.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 6, 2018
    Assignee: MAPPER LITHOGRAPHY IP B.V.
    Inventor: Marco Jan-Jaco Wieland
  • Patent number: 9882708
    Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include a receiver circuit and one of the provided techniques includes receiving a data stream at the receiver circuit. The receiver circuit may include a detector circuit that is used to determine the data rate of the received data stream. A controller block in the receiver circuit may accordingly configure a deserializer circuit in the receiver circuit based on the data rate of the received data stream. The circuitry may further include a transmitter circuit for transmitting data streams. The transmitter circuit may be configured during runtime based on the data rate of a data stream that is being transmitted. In some instances, irrespective of the data rate of the data stream being transmitted, a constant reference clock may be used in the transmitter circuit.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: January 30, 2018
    Assignee: Altera Corporation
    Inventors: Boon Hong Oh, Chee Wai Yap
  • Patent number: 9847792
    Abstract: A communication apparatus includes a serializer configured to convert parallel data into serial data and output the serial data; and a deserializer configured to convert the serial data output from the serializer into parallel data and output the parallel data. The serializer is configured to add first data used for detecting unique data in the parallel data before the unique data, add second data used for detecting the unique data after the unique data, and add third data whose length is variable to each of the first data and the second data.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: December 19, 2017
    Assignee: RICOH COMPANY, LTD.
    Inventors: Tatsuya Miyadera, Satoshi Ohmiya, Tatsuo Ohyama, Masahiko Oikawa, Yuichiro Shukuya, Makoto Higashiyama, Yasuhiro Abe
  • Patent number: 9805811
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of stacked first chips and a second chip. The second chip outputs a first signal to the first chips. The first chip outputs status information at timing based on the received first signal. The first chip shifts the received first signal and outputs the shifted first signal to the first chip of a next stage in synchronization with the first clock signal. The second chip receives a plurality of status information output in a serial manner from the first chips.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: October 31, 2017
    Inventors: Hiroaki Nakano, Mami Kakoi, Shigeki Nagasaka, Toshiyuki Kouchi, Itaru Yamaguchi
  • Patent number: 9780795
    Abstract: A source-synchronous clocking signal is sampled by an edge sampler triggered by a phase-adjusted version of the clocking signal. The output of the edge sampler is used as a phase-error indicator for a filtered feedback loop that aligns the phase-adjusted clocking signal to minimize, on average, the difference between the received source-synchronous clocking signal and the phase-adjusted version of the clocking signal minus the setup time of the sampler. This forms a delay-locked loop configuration. The phase adjustment information used to produce the aligned phase-adjusted clocking signal is then to produce a receiver clocking signal that is used to sample the source-synchronous data signal.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: October 3, 2017
    Assignee: Rambus Inc.
    Inventor: Reza Navid
  • Patent number: 9760515
    Abstract: Methods and systems for shared control of a phase locked loop (PLL) for a multi-port physical layer (PHY) are disclosed. In one aspect, an arbitration logic circuit is coupled to ports of a multi-port PHY sharing a phase locked loop (PLL). Upon receiving an indication that the shared PLL is to be reset, the arbitration logic circuit commands the ports sharing the PLL to enter a state in which any reset of the shared PLL would have minimal or no effect in their operations. In this manner, an integrated circuit (IC) including a multi-port PHY may be configured with only one PLL and associated clock generating logic to provide a clock signal for some or all of its ports, thus reducing its semiconductor area and power consumption. Furthermore, the ports of the multi-port PHY may operate independently from each other obviating any configuration and/or interoperability problems associated with having a shared PLL.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: September 12, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Chad Everett Winemiller, Dror Barash, Russell Coleman Deans, Mark Wesley Vilas
  • Patent number: 9729170
    Abstract: An integrated circuit (IC) includes a serial-to-parallel converter configured to receive a serial input signal to provide one or more parallel output signals. The serial input signal is an M-level Pulse-Amplitude Modulated (PAM) signal, wherein M is a positive integer. The serial-to-parallel converter includes a data converter configured to receive the serial input signal and provide a data converter output signal. The data converter output signal represents information of the serial input signal with N1 bits, and N1 is a positive integer. An encoder is configured to encode the data converter output signal to provide encoder output signal with N2 bits, wherein N2 is a positive integer less than half of N1. One or more sub-deserializers are configured to receive the encoder output signal and generate the one or more parallel output signals.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: August 8, 2017
    Assignee: XILINX, INC.
    Inventors: Arianne B. Roldan, Hsung Jai Im
  • Patent number: 9722590
    Abstract: A skew adjustment circuit includes: flip flop circuits for taking in an input signal in response to first clock signals; a clock phase adjustment circuit for adjusting phases of second clock signals, based on the second clock signals generated based on a reference clock signal and an output signal from the flip flop circuits; a phase interval detection circuit for detecting a phase interval between the first clock signals, based on a reference value; and a phase interval adjustment circuit for performing adjustment such that phase intervals become equal to each other between the second clock signals adjusted by the clock phase adjustment circuit, based on a skew adjustment signal from the phase interval detection circuit. The reference value is obtained by calibration, and the second clock signals adjusted by the phase interval adjustment circuit are provided as the first clock signals to the flip flop circuits.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: August 1, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Tatsunori Usugi, Kouzaburou Kurita, Takemasa Komori, Junya Nasu
  • Patent number: 9698764
    Abstract: Described is an apparatus of a quadrature divider. The apparatus is independent of a jam latch, and is for generating a quadrature clock. The apparatus comprises: a first selection unit controllable by a clock signal, the first selection unit to directly or indirectly generate a first phase of the quadrature clock; a third selection unit controllable by the clock signal, the third selection unit to receive the first phase of the quadrature clock, the third selection unit to directly or indirectly generate a third phase of the quadrature clock, wherein the first selection unit to receive the third phase of the quadrature clock.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: July 4, 2017
    Assignee: Intel Corporation
    Inventors: Mark L. Neidengard, Qi Wang
  • Patent number: 9692623
    Abstract: A receiver includes a receiver circuit to receive a pulse width modulated signal, which assumes a first signal level, a second signal level and an intermediate signal level between the first signal level and the second signal level. The receiver further includes a quantization circuit to determine a value encoded in the signal based on an intermediate time period between a first transition and an intermediate transition and based on a main time period between the first transition and a second transition. The first transition comprises the first signal level, wherein the intermediate transition includes the intermediate signal level. The second transition includes the second signal level.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: June 27, 2017
    Assignee: Infineon Technologies AG
    Inventor: Dirk Hammerschmidt
  • Patent number: 9672883
    Abstract: A semiconductor circuit may include a control circuit configured to generate a second start signal and a plurality of serialization control signals by synchronizing a first start signal with first and second clock signals.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: June 6, 2017
    Assignee: SK hynix Inc.
    Inventor: Dong Uk Lee
  • Patent number: 9660615
    Abstract: A flip-flop device is provided. The flip-flop device includes a first flip-flop and a clock controller. The first flip-flop receives a first clock signal and a second clock signal for operation. The clock controller receives a clock source signal and generates the first clock signal and the second clock signal according to the clock source signal. Each of the first clock signal and the second clock signal switches between a first voltage level and a second voltage level. For each of the first clock signal and the second clock signal, a period of the first voltage level is shorter than a period of the second voltage level. The period of the first voltage level of the first clock signal and the period of the first voltage level of the second clock signal are non-overlapping.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: May 23, 2017
    Assignee: MEDIATEK INC.
    Inventors: Meng-Cheng Peng, Rei-Fu Huang
  • Patent number: 9658643
    Abstract: A data interface includes a first sampler sampling a first bitset and a second sampler sampling a second bitset. The first bitset includes a first bit which is included in a first image data and a third bit which is included in a second image, and the second bitset includes a second bit which is included in the first image data and is a higher-order bit than the first bit and a fourth bit which is included in the second image data and is a higher-order bit than the third bit. The data interface further includes a clock generator configured to adjust a sampling timing of the first and second bitsets based on a multi-phase clock, and a clock data recovery (CDR) circuit shared by the first sampler, the second sampler and configured to output the multi-phase clock to the clock generator.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: May 23, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Kyun Jeong, Jung-Hoon Chun, June-Hee Lee, Won-Ho Choi
  • Patent number: 9621388
    Abstract: A method and system for serial data transmission are provided. The method includes steps of: bit-synchronously receiving N bit binary code data which is transmitted continuously and repeatedly by a transmitting end, wherein the N bit binary code data is N bit binary code data converted from original data by the transmitting end on the basis of a preset rule; performing cyclic left shift or right shift 0 to N?1 times on each of the received N bit binary code data, which results in a data set, and obtaining an extreme value in the data set; and decoding the extreme value, which results in the original data transmitted by the transmitting end. With the method and system, a start and an end flags are not needed to be added additionally during the serial data transmission, thus improving the efficiency of the serial data transmission.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: April 11, 2017
    Assignee: SHENHEN HUIDING TECHNOLOGY CO., LTD.
    Inventors: Shu Pang, Jinchun Ye
  • Patent number: 9615038
    Abstract: When imaging bright objects, a conventional detector array can saturate, making it difficult to produce an image with a dynamic range that equals the scene's dynamic range. Conversely, a digital focal plane array (DFPA) with one or more m-bit counters can produce an image whose dynamic range is greater than the native dynamic range. In one example, the DFPA acquires a first image over a relatively brief integration period at a relatively low gain setting. The DFPA then acquires a second image over longer integration period and/or a higher gain setting. During this second integration period, counters may roll over, possibly several times, to capture a residue modulus 2m of the number of counts (as opposed to the actual number of counts). A processor in or coupled to the DFPA generates a high-dynamic range image based on the first image and the residues modulus 2m.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: April 4, 2017
    Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Michael W. Kelly, Megan H. Blackwell, Curtis B. Colonero, James Wey, Christopher David, Justin Baker, Joseph Costa
  • Patent number: 9612986
    Abstract: A set of training sequences is generated, each training sequence to include a respective training sequence header, and the training sequence header is to be DC-balanced over the set of training sequences. The set of training sequences can be combined with electric ordered sets to form supersequences for use in such tasks as link adaptation, link state transitions, byte lock, deskew, and other tasks.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Sitaraman Iyer
  • Patent number: 9537505
    Abstract: A data processing apparatus includes an inputting portion; a first retrieving portion; a second retrieving portion; a clock determining portion; a first serial parallel converting portion; a second serial parallel converting portion; and a combining portion. The inputting portion receives a serial data including a clock bit. The first retrieving portion obtains a first retrieved data. The second retrieving portion obtains a second retrieved data. The clock determining portion determines whether the clock bit is included in the first retrieved data or the second retrieved data. The first serial parallel converting portion performs parallel conversion to obtain a first parallel data. The second serial parallel converting portion performs parallel conversion to obtain a second parallel data. The combining portion combines the first parallel data and the second parallel data to output a parallel data.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: January 3, 2017
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Hiroyoshi Ichikura, Kunihiro Harayama, Hideaki Hasegawa
  • Patent number: 9497525
    Abstract: Optical engines and optical cable assemblies incorporating optical engines providing duty cycle correction on multiplexed low-speed signals are disclosed. In one embodiment, an optical engine includes a low-speed Tx line, a low-speed Rx line, an optical transceiver device, and a control circuit. A low-speed Tx signal is transmitted on the low-speed Tx line and a low-speed Rx signal is received on the low-speed Rx line. The optical transceiver device further includes a laser control pin operable to control a laser configured to provide light on an optical Tx lane, and an optical detect pin operable to provide an indication as to light detected at an optical Rx lane. A Tx signal conditioning circuit configured to condition the low-speed Tx signal is coupled to the laser control pin, and/or a Rx signal conditioning circuit configured to condition the low-speed Rx signal is coupled to the optical detect pin.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: November 15, 2016
    Assignee: CORNING OPTICAL COMMUNICATIONS LLC
    Inventors: Mathieu Charbonneau-Lefort, Richard Clayton Walker, Michael John Yadlowsky
  • Patent number: 9479849
    Abstract: A method may include generating, by a device, a set of bit masks associated with locating frame alignment signal (FAS) data. The set of bit masks may be utilized by multiple framer circuits associated with identifying a start of one more frames of multiple lower order Optical channel Data Unit (ODU) flows multiplexed in a higher order ODU flow. The method may include detecting, by the device, the FAS data at a particular byte location in a particular lower order ODU flow, of the multiple lower order ODU flows, based on the set of bit masks. The method may include identifying, by the device, the start of one or more frames of the particular lower order ODU flow based on detecting the FAS data. The one or more frames may be associated with an ITU-T G.709 Optical Transport Network frame based signal.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: October 25, 2016
    Assignee: Infinera Corporation
    Inventors: Ashok Jain, Vishwanathan Paramasivam, Ashok N. Tatineni
  • Patent number: 9455826
    Abstract: On the basis of single-ended signals based on logic levels, and of differential, in particular common-mode-based, signals, a circuit arrangement and a corresponding method are proposed, in which a serialized signal transmission is always performed in an error-free and stable manner.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: September 27, 2016
    Assignee: SILICON LINE GMBH
    Inventors: Thomas Blon, Florian Jansen, Holger Hoeltke
  • Patent number: 9455751
    Abstract: On the basis of single-ended signals based on logic levels, and of differential, in particular common-mode-based, signals, a circuit arrangement and a corresponding method are proposed, in which the power consumption required for the transfer of L[ow]P[ower] data is as low as possible.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: September 27, 2016
    Assignee: SILICON LINE GMBH
    Inventors: Thomas Blon, Holger Hoeltke
  • Patent number: 9455745
    Abstract: A method of encoding a data set including one or more n-bit pre-coded symbols in an encoder of a computing system includes determining a plurality of n+2-bit code words, each of the plurality of n+2-bit code words having two or greater Hamming distance from one another. The method further includes mapping each of the plurality of n+2-bit code words to a corresponding source symbol, receiving the one or more n-bit pre-coded symbols at the encoder, matching each n-bit pre-coded symbol to a corresponding n+2-bit code word based on the mapping to produce encoded data. and outputting the encoded data.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: September 27, 2016
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventor: Andras Tantos