Serial To Parallel Patents (Class 341/100)
  • Patent number: 9455751
    Abstract: On the basis of single-ended signals based on logic levels, and of differential, in particular common-mode-based, signals, a circuit arrangement and a corresponding method are proposed, in which the power consumption required for the transfer of L[ow]P[ower] data is as low as possible.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: September 27, 2016
    Assignee: SILICON LINE GMBH
    Inventors: Thomas Blon, Holger Hoeltke
  • Patent number: 9436211
    Abstract: A clock conversion apparatus comprising, an elastic store memory in which data are written in synchronization with a first clock and from which data are read out in synchronization with a second clock, a phase comparator for detecting phase difference between a third clock obtained by imparting a first variable phase shift to a divided clock of the first clock and a fourth clock obtained by imparting a second variable phase shift to a divided clock of the second clock, and an oscillator for generating a clock having frequency in accordance with the phase difference as the second clock.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: September 6, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Makoto Shimizu, Masato Hori
  • Patent number: 9425913
    Abstract: A media independent interface in an integrated circuit device includes a first plurality of channels, each including a data transmit path and a data receive path, and a second plurality of channels, each including a transmit path to transmit an idle symbol and a receive path to receive the idle symbol. The interface also includes a codec, coupled to the transmit paths of the first and second pluralities of channels, to encode data and symbols on the transmit paths, and a multiplexer, coupled to the codec, to multiplex the data on the transmit paths of the first and second pluralities of channels as encoded by the codec. The interface further includes a Ser Des to serialize the multiplexed data.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: August 23, 2016
    Assignee: QUALCOMM Incorporated
    Inventor: Hongchun Yu
  • Patent number: 9374098
    Abstract: A system and method for transmitting includes a plurality of multiplexers each configured to combine a pseudo random bit sequence (PRBS) with at least one input stream according to the data control clock. At least one storage device is coupled to an output of each of the plurality of multiplexers and is configured to latch data according to the data control clock. An output multiplexer is coupled to each of the at least one storage device and is configured to select between storage paths according to the data serializer clock. A PRBS checker is configured to compare a PRBS pattern on an output of the output multiplexer with a predicted PRBS pattern. A phase rotator is configured to adjust the data serializer clock based upon the comparison of the PRBS checker to reduce latency of the transmitter.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: June 21, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Leonard R. Chieco, Frank R. Keyser, III, Michael A Sorna
  • Patent number: 9362950
    Abstract: A cyclic redundancy check (CRC) can be determined with fewer resources within a communication system. A CRC interface component is configured to receive an array of bits as an input via an N-bit data pathway, and receive a CRC previous output from a feedback component coupled to a CRC output, in which N can comprise an integer greater than one. A parallel CRC component can be configured to generate a CRC current output from a plurality of parallel processing pipelines that are configured to concurrently process at least a part of the array of bits and the CRC previous output with a set of parallel CRC logic operations. The set of CRC logic operations can include a masking operation and a parity operation.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: June 7, 2016
    Assignee: Infineon Technologies AG
    Inventor: Edward Wiley
  • Patent number: 9337996
    Abstract: In a data recovery circuit, the position of an edge is detected from parallel data acquired by oversampling data received through serial communication, the position of a next edge is estimated, the estimated position of the edge is compared with the detected position of the actual edge, and the sampling position of the parallel data is adjusted based on a result of the comparison. As a result, an oversampling clock can be set to a maximum frequency, and accordingly, the precision of the data recovery circuit can be improved.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: May 10, 2016
    Assignee: FANUC CORPORATION
    Inventor: Tomomasa Nakama
  • Patent number: 9305480
    Abstract: A display having a data driving integrated circuit includes N number of output channels (where N is an integer) having at least two regions including a first output channel and an Nth output channel, a data output channel group including M data output channels (where M is an integer less than N), the M data output channels supplying pixel data to a corresponding number of the data lines in accordance with a desired resolution of the display, wherein (N?M) output channels are not supplied with pixel data, and the (N?M) output channels are located between the first output channel and the Nth output channel, and a channel selector selecting the M data output channels.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: April 5, 2016
    Assignee: LG Display Co., Ltd.
    Inventors: Sin Ho Kang, Hong Sung Song, Jin Cheol Hong
  • Patent number: 9286260
    Abstract: A method for converting serial data having a certain word size to parallel data, comprises the steps of: generating segments from the serial data using serially-connected stages, wherein the segments have a predetermined bit size; storing each of the segments into a selectively turned-on flip-flop of a final stage, wherein the final stage is serially connected to the stages, wherein the final stage has a plurality of flip-flops and each of the flip-flops has a bit size equaling to the bit size of the segments; and outputting the stored segments in parallel from the final stage.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: March 15, 2016
    Assignee: SOCTRONICS, INC.
    Inventor: Venkata N. S. N. Rao
  • Patent number: 9288003
    Abstract: A reception circuit includes: a plurality of block circuits that each include a phase control circuit that controls a phase of a first clock, and a plurality of internal circuits that are driven by a second clock generated based on the phase-controlled first clock, wherein the phase control circuit in each of the block circuits is controlled by means of a control signal from an operation phase control circuit in such a way that an error rate for reception data due to the plurality of block circuits decreases.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: March 15, 2016
    Assignee: Fujitsu Limited
    Inventor: Yoshiyasu Doi
  • Patent number: 9268661
    Abstract: A system, apparatus, and method for testing blocks of a system on a chip (SOC) are described herein. An SOC, in accordance with various embodiments, may include a serial communication interface configured to multiplex, serialize, and/or parallelize signals streams from selected blocks of the SOC to an off-chip test unit through an off-chip serial communication interface. Other embodiments may be described and claimed.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: February 23, 2016
    Assignee: Marvell International Ltd.
    Inventors: Roger Longstreet, Vivek Raghunath Khanzode, Hongying Sheng
  • Patent number: 9191194
    Abstract: The present invention provides method and apparatus for adapting a relatively high data rate second order serdes receiver to receive relatively low data rate serial data, the receiver having jog realignment by and having means for receiving the serial data as a plurality of repeated bits at the high data rate; framing the data as frames of repeated bits of the same value; examining the bits of the frame for the presence of bits which are not of the same value; upon detecting such a presence that is indicative of a framing error jogging the serdes receiver for frame realignment; and supplying to an output of the serdes receiver one of the bits of said same value from each frame at the low data rate.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: November 17, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Iain Robertson, Richard Williams
  • Patent number: 9183902
    Abstract: An input data alignment circuit includes a data sampler, a frequency divider, a polarity determination block, and a data alignment block. The data sampler provides a data sequence based on data serially input according to a data strobe signal. The frequency divider generates a data alignment signal based on a divided frequency of the data strobe signal. The polarity determination block determines a polarity of the data alignment signal and provides a control signal based on the determined polarity. The data alignment block aligns the data sequence in parallel according to data alignment signal and control signal and generates output data.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: November 10, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-sik Moon, Seung-jun Bae, Joon-young Park, Yoon-joo Eom
  • Patent number: 9166611
    Abstract: A system can include a first section with an ultra high speed digital sampler configured to sample at a first rate, a scrambler connected to the sampler, and a set of ultra high speed serial data outputs. The system can further include a second section with a set of ultra high speed serial data inputs, a set of serial to parallel converter circuits connected to the inputs and outputting data at a second rate, a descrambler having inputs connected to the reduced speed data outputs, and a set of parallel outputs configured to output the serial data. The set of ultra high speed serial data outputs of the first section are configured to be connected to the set of ultra high speed serial data inputs in the second section by a set of ultra high speed communication pathways clocked at a speed substantially equal to the first rate.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: October 20, 2015
    Assignee: Raytheon Company
    Inventor: Howard K. Luu
  • Patent number: 9154159
    Abstract: A deserializer includes an input interface configured to receive an N-bit serialized stream at a source clock frequency; a modified-tree deserializing architecture that receives the first N?1 bits of the serialized stream from the input interface and generates N?1 parallel outputs corresponding to the first N?1 bits; and a last-bit flip-flop that directly samples the input interface to obtain an Nth bit, such that all N bits are available within one source clock cycle after the Nth bit arrives at the input interface.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: October 6, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Yong Liu
  • Patent number: 9112520
    Abstract: A transmission interface includes a first pin, a second pin, a conversion unit, and a decoding unit. The conversion unit receives a serial input data stream via the first pin and receives a serial clock via the second pin. The conversion unit converts the serial input data stream to parallel input data and converts the serial clock to a parallel clock. The serial input data stream has a full swing form. The decoding unit receives and decodes the parallel input data and generates an input data signal according to the decoded parallel input data.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: August 18, 2015
    Assignee: MEDIATEK INC.
    Inventors: Wei-Cheng Gu, Chung-Hung Tsai, Chun-Nan Li, Yi-Hsi Chen
  • Patent number: 9100044
    Abstract: A method and apparatus for direct digital synthesis (DDS) of signals using Taylor series expansion is provided. The DDS may include a modified phase-to-amplitude converter that includes read-only-memories (ROMs), registers and, a single size, such as a coarse, intermediate, and fine ROM corresponding to respective higher resolution phase angles. The outputs of the ROMs when combined can form a digital output signal in the form of a Taylor series of a sinusoid function.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: August 4, 2015
    Inventors: Dipayan Mazumdar, Govind Rangaswamy Kadambi
  • Patent number: 9071258
    Abstract: A parallel-serial converter circuit has a frequency divider configured to generate a frequency-divided signal by dividing a frequency of a reference clock signal by a dividing ratio depending on a logic of a speed control signal, a timing pulse generator configured to generate a timing pulse signal based on the frequency-divided signal, a load signal generator configured to generate a load signal based on the speed control signal and the timing pulse signal, a bit clock generator configured to generate a bit clock signal based on the speed control signal and the timing pulse signal, and a parallel-serial converter configured to newly load the parallel data in synchronization with the load signal and convert the loaded parallel data into serial data in synchronization with the bit clock signal.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: June 30, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mikio Shiraishi
  • Patent number: 9071256
    Abstract: The present disclosure relates to a method for use with a serializer/deserializer comprising. The method may include grouping one or more lane modules associated with an integrated circuit (IC) together to form a link, wherein each of the one or more lane modules includes a reset state machine and a high speed reset generator. The method may also include providing a common module having a common reset release state machine and a reset release synchronizer and pulse generator, the common module and one or more lane modules being configured to communicate therebetween. The method may further include resetting each link independently using the one or more lane modules.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: June 30, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Loren Blair Reiss, Chris Moscone, Benjamin Louis Heilmann, Randall Smith
  • Patent number: 9069694
    Abstract: A method for operating a memory device is disclosed. The method includes receiving a serial data and a serial cyclic redundancy check (CRC) code transmitted sequentially through a channel, converting the serial data into a parallel data and the serial CRC code into a parallel CRC code, outputting the parallel data at a first time point, outputting the parallel CRC code at a second time point later than the first time point, calculating a CRC code by using the parallel data, comparing the parallel CRC code and the calculated CRC code with each other and detecting an error of the serial data transmitted through the channel according to the result of the comparison, and outputting an error detection signal in response to the result of the comparison.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: June 30, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Byung-Hyun Lee
  • Publication number: 20150145707
    Abstract: A digital serial-to-parallel converter capable of minimizing a malfunction of a circuit by more stably performing an operation of a D flip flop in implementing a GaAs MMIC digital serial-to-parallel converter and a GaAs MMIC using the same are disclosed. The digital serial-to-parallel converter includes: a converter configured to convert a received clock signal, serial data, and load signal of TTL into a DCFL signal; a plurality of D flip flops configured to transmit the serial data received through the converter to a D flip flop of a next stage by the clock signal received through the converter and output the serial data of the D flip flop of the next stage by the load signal received through the converter; and a plurality of buffers configured to receive the serial data from the plurality of D flip flops to generate and output complementary signals.
    Type: Application
    Filed: October 15, 2014
    Publication date: May 28, 2015
    Inventors: Jin-Cheol JEONG, Dong-Hwan SHIN, In-Kwon JU, In-Bok Yom
  • Patent number: 9030339
    Abstract: A transmitting device includes a parallel data generation unit and a transmitting unit. The parallel data generation unit generates first serial data and second serial data from a data packet, converts the first serial data and second serial data respectively into first parallel data and second parallel data, transmits the first parallel data and second parallel data respectively through first and second parallel transmission paths, and performs the transmission of the first parallel data and the transmission of the second parallel data in parallel. The transmitting unit receives the first parallel data and second parallel data respectively through the first and second parallel transmission paths, re-converts the first parallel data and second parallel data respectively into the first serial data and second serial data, and transmits the first serial data and second serial data to a receiving device respectively through first and second serial transmission paths.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: May 12, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yusuke Fujita
  • Patent number: 9013337
    Abstract: A data input/output (I/O) device includes a plurality of data units and an I/O assembly. The plurality of data units is coupled to a global I/O (GIO) line through corresponding local I/O (LIO) lines and configured to receive or transmit a plurality of data groups through the corresponding LIO lines. At least one of the plurality of data units have a different operation speed. The I/O assembly performs serial/parallel conversion operations on the plurality of data groups including a high-speed data group and outputs results of the serial/parallel conversion operations. The high-speed data group is output from the at least one of the plurality of data units having the different operation speed.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: April 21, 2015
    Assignee: SK Hynix Inc.
    Inventor: Seon Kwang Jeon
  • Patent number: 8977884
    Abstract: A bit stream includes playback data having an associated clock rate and a variable reference clock that is synchronized to the bit stream. A playback clock recovery signal and a data recovery signal are generated in response to the received reference clock. A playback clock frequency signal is generated in response to the playback clock recovery signal. A recovered playback clock is generated by using a divide by M divider, wherein the value of M used by the divide by M divider is determined in response to a programmable multiple of the clock rate associated with the playback information.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: March 10, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Sucheendran Sridharan, Bharadwaj Parthasarathy, James Nave, Haydar Bilhan
  • Publication number: 20150048957
    Abstract: A data input/output (I/O) device includes a plurality of data units and an I/O assembly. The plurality of data units is coupled to a global I/O (GIO) line through corresponding local I/O (LIO) lines and configured to receive or transmit a plurality of data groups through the corresponding LIO lines. At least one of the plurality of data units have a different operation speed. The I/O assembly performs serial/parallel conversion operations on the plurality of data groups including a high-speed data group and outputs results of the serial/parallel conversion operations. The high-speed data group is output from the at least one of the plurality of data units having the different operation speed.
    Type: Application
    Filed: January 14, 2014
    Publication date: February 19, 2015
    Applicant: SK HYNIX INC.
    Inventor: Seon Kwang JEON
  • Patent number: 8941516
    Abstract: Provided are a signal processing apparatus and a signal processing method. The signal processing method include receiving a serial signal including an information frame including channel information and data information of a corresponding channel, extracting a clock signal from the serial signal, generating a load signal when a clock count reaches a maximum clock count by calculating the clock signal; converting the serial signal to a parallel signal according to the load signal, and changing the maximum clock count by comparing parallel-converted parallel channel information with a load count indicating the number of local signals.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: January 27, 2015
    Assignee: Korea Research Institute of Standards and Science
    Inventors: Jin Mok Kim, Hyukchan Kwon, Yong Ho Lee, Ki Woong Kim
  • Patent number: 8933833
    Abstract: The disclosed conversion device converts an analog input signal into a digital signal and outputs thereof, wherein the conversion device comprises a feedback signal generator for performing mismatch shaping on the digital signal that has been converted and output, and then performing digital-analog conversion to generate a feedback signal; a subtractor for subtracting the feedback signal from the analog input signal and outputting thereof; a serial-parallel converter for converting the signal output from the subtractor into a plurality of parallel signals and outputting thereof; a vector filter for performing signal processing on the plurality of parallel signals output by the serial-parallel converter and outputting a plurality of signals; a quantizer for quantizing the plurality of signals output by the vector filter and outputting digital signals; and a parallel-serial converter for converting the digital signals output by the quantizer into serial signals and outputting thereof.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: January 13, 2015
    Assignee: Trigence Semiconductor, Inc.
    Inventors: Akira Yasuda, Jun-ichi Okamura
  • Patent number: 8917800
    Abstract: A mechanism is provided for dynamically adjusting DC offset at the time of deviation from DC balance ½ (DC level) in a data pattern including long-period consecutive bits generating DC offset in a section of data. A receiver circuit unit of an LSI having a serializer/deserializer arrangement for performing high-speed serial transmission includes an offset adjusting circuit. The offset adjusting circuit calculates DC balance in an arbitrary section of data by averaging received serial data. Based on comparison between a DC level and the DC balance obtained by averaging the received data, offset is shifted toward the H side when the DC balance exists on the H side from the DC level, and shifted toward the L side when the DC balance exists on the L side.
    Type: Grant
    Filed: August 10, 2013
    Date of Patent: December 23, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Akira Matsumoto, Naoki Mori, Takashi Yagi
  • Patent number: 8902091
    Abstract: A serial-to-parallel converter includes a first register bank having first and second register groups, the first register bank configured to receive a communication signal having at least one bit for each unit interval (UI) of a system clock signal, the first register bank having a number of registers corresponding to a number of parallel processing stages, a second register bank having a plurality of register groups, each register group configured to receive the output of at least one of the first and second register groups after a number of unit intervals corresponding to the number of registers in each of the first and second register groups in the first register bank, and a third register bank configured to receive the output of the second register bank after a number of unit intervals corresponding to a number of registers in the second register bank.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: December 2, 2014
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Darrin C. Miller, Jade Michael Kizer, Peter J. Meier, Gilbert Yoh
  • Publication number: 20140340247
    Abstract: Deserializers are provided. The deserializer includes a data aligner, a selection signal generator and a selection output unit. The data aligner is configured to align data in response to internal clock signals having different phases from each other to generate higher aligned data and lower aligned data. The selection signal generator is configured to detect a phase of one of the internal clock signals in response to a phase detection signal to generate a selection signal. The phase detection signal includes a pulse generated according to a write command signal and a write latency signal. The selection output unit is configured to output the higher aligned data or the lower aligned data as selected alignment data in response to the selection signal.
    Type: Application
    Filed: July 30, 2014
    Publication date: November 20, 2014
    Inventor: Keun Soo SONG
  • Patent number: 8890726
    Abstract: In one embodiment, an apparatus may include a clock generator to generate a first clock signal. The apparatus may also include a serializer to generate serial data based on a transmit clock signal and parallel input data. The apparatus may also include a signal generator to generate at least two differential signals based on the first clock signal and the serial data.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: November 18, 2014
    Assignee: Intel Corporation
    Inventor: Wei-Lien Yang
  • Patent number: 8817929
    Abstract: A transmission circuit includes: a plurality of lane blocks arranged in parallel to each other configured to convert parallel data supplied from a corresponding lane into serial data and output the serial data; and a clock enabler block including at least one clock enabler for outputting a drive clock phase-locked with a reference clock to the plurality of lane blocks after a plurality of cycles of the drive clock in response to an enable signal. Each of the plurality of lane blocks has a divider for dividing the drive clock supplied from the clock enabler block to generate a divide clock and a load signal, and a parallel-to-serial converter for converting parallel data supplied from the corresponding lane into serial data in synchronization with the divide clock and the load signal generated by the divider and the drive clock generated by the clock enabler block.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: August 26, 2014
    Assignee: Sony Corporation
    Inventor: Yukio Shimomura
  • Patent number: 8816885
    Abstract: In one embodiment, an apparatus may include a de-serializer to convert serial data into two parallel data streams, and a control unit to provide a first update signal and a second update signal based on a bit count of the serial data. The apparatus may further include a target component having an input bus, the input bus including a first portion and a second portion. The apparatus may further include a first output unit to provide the first set of parallel data to the first portion of the input bus, and a second output unit to provide the second set of parallel data to the second portion of the input bus.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: August 26, 2014
    Assignee: Intel Corporation
    Inventor: Wei-Lien Yang
  • Patent number: 8803714
    Abstract: A transmitting device includes a parallel data generation unit and a transmitting unit. The parallel data generation unit generates first serial data and second serial data from a data packet, converts the first serial data and second serial data respectively into first parallel data and second parallel data, transmits the first parallel data and second parallel data respectively through first and second parallel transmission paths, and performs the transmission of the first parallel data and the transmission of the second parallel data in parallel. The transmitting unit receives the first parallel data and second parallel data respectively through the first and second parallel transmission paths, re-converts the first parallel data and second parallel data respectively into the first serial data and second serial data, and transmits the first serial data and second serial data to a receiving device respectively through first and second serial transmission paths.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: August 12, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yusuke Fujita
  • Publication number: 20140218221
    Abstract: Receiver circuits in serial lanes each generate a synchronous clock signal that is aligned with a master clock signal to allow synchronous transfer of data onto the master clock domain without corruption. A serial-to-parallel converter circuit in each receiver circuit converts a serial data signal into parallel data signals in response to one of the synchronous clock signals. Phase detection circuitry generates an indication of a phase shift based on a phase offset between the synchronous and master clock signals. A clock signal generation circuit provides an adjustment to a phase of the synchronous clock signal based on the indication of the phase shift. The serial-to-parallel converter circuit adjusts positions of bits indicated by the parallel data signals based on the adjustment to the phase of the synchronous clock signal.
    Type: Application
    Filed: February 5, 2013
    Publication date: August 7, 2014
    Applicant: ALTERA CORPORATION
    Inventor: Altera Corporation
  • Patent number: 8760328
    Abstract: An integrated circuit system may include a first integrated circuit (IC), a second IC, and interface circuitry. The first IC is operable to output a parallel data stream at a first data rate. The second IC is operable to output a serialized data stream at a second date rate. The second data rate may be different than the first data rate. The interface circuitry may be coupled between the first integrated circuit and the second integrated circuit. The interface circuitry may be operable to convert the parallel data stream received from the first IC into a serialized data stream with the second data rate. The interface circuitry may be also operable to convert the serialized data stream received from the second IC to a parallel data stream with the first data rate.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: June 24, 2014
    Assignee: Altera Corporation
    Inventors: Wei Yee Koay, Chin Ghee Ch'ng, Ket Chiew Sia, Tony Ngai, Sean Woei Voon
  • Patent number: 8755236
    Abstract: A latch system applied to a plurality of banks of a memory circuit includes a front latch circuit and a plurality of rear latch circuit. The front latch circuit is used for receiving a datum and a front latch enabling signal, and generating and outputting an intermediate signal according to the datum and the front latch enabling signal. Each rear latch circuit of the plurality of rear latch circuits is coupled to an output terminal of the front latch circuit for receiving the intermediate signal, and generating and outputting a rear latch datum to a corresponding bank of the plurality of banks according to the intermediate signal and a corresponding rear latch enabling signal, where only one rear latch enabling signal is enabled at any time.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: June 17, 2014
    Assignee: Etron Technology, Inc.
    Inventors: Chun Shiah, Shi-Huei Liu, Cheng-Nan Chang
  • Patent number: 8750430
    Abstract: A data receiver circuit for converting received serial data into parallel data in accordance with a data rate signal and for outputting the converted parallel data, the data receiver circuit includes a clock generator for generating a reference clock based on an input clock, a data latch for latching the received serial data and outputting first latched serial data in accordance with the reference clock, a first data output section for converting the first latched serial data into first parallel data with a first reference clock, in case that the data rate signal indicates a first data rate same as a data rate of the reference clock, and a second data output section for converting the first latched serial data into second parallel data with a second reference clock, in case that the data rate signal indicates a second data rate slower than the data rate of the reference clock.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: June 10, 2014
    Assignee: Fujitsu Limited
    Inventor: Yoichi Koyanagi
  • Patent number: 8730069
    Abstract: A double data rate serial encoder is provided. The serial encoder comprises a mux having a plurality of inputs, a plurality of latches coupled to the inputs of the mux, an enabler to enable the latches to update their data inputs, and a counter to select one of the plurality of inputs of the mux for output. In another aspect, the mux provides a glitch-less output during input transitions. The mux includes an output selection algorithm optimized based on a priori knowledge of an input selection sequence provided by the counter.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: May 20, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: George A. Wiley, Brian Steele, Curtis D. Musfeldt
  • Patent number: 8723705
    Abstract: A Double Data Rate (DDR) serial encoder is provided. In one aspect, the DDR serial encoder includes a non-glitchless multiplexer and digital logic for ensuring a glitch-free encoder output. By using a non-glitchless multiplexer, the size and complexity of the encoder is significantly reduced. In another aspect, the DDR serial encoder has a single layer of logic between the final register stage and the encoder output and a reduced number of paths from the final register stage to the encoder output, thereby resulting in reduced output skew and increased link rate.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: May 13, 2014
    Assignee: Qualcomm Incorporated
    Inventor: Curtis Drew Musfeldt
  • Patent number: 8711017
    Abstract: A transmitter apparatus is provided for converting parallel data of natural number n×12 bits into n pieces of serial data, and transmitting n transmission signals each of natural number m bits. In the transmitter apparatus, a dividing buffer divides inputted parallel data into n pieces of 12-bit parallel data, and an encoder circuit 12B14B-converts the n pieces of 12-bit parallel data into n pieces of 14-bit parallel data, respectively, and outputs resulting data. A parallel-to-serial converter circuit parallel-to-serial converts the n pieces of 14-bit parallel data into n pieces of 1-bit serial data, respectively, and outputs resulting data, and an m-bit driver circuit amplifies and transmits the n pieces of 1-bit serial data, as n transmission signals each of m bits, respectively, to n transmission paths.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: April 29, 2014
    Assignee: Panasonic Corporation
    Inventor: Osamu Shibata
  • Patent number: 8711018
    Abstract: In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: April 29, 2014
    Assignee: Intel Corporation
    Inventors: Ehud Shoor, Dror Lazar, Assaf Benhamou
  • Publication number: 20140111360
    Abstract: A transmission interface includes a first pin, a second pin, a conversion unit, and a decoding unit. The conversion unit receives a serial input data stream via the first pin and receives a serial clock via the second pin. The conversion unit converts the serial input data stream to parallel input data and converts the serial clock to a parallel clock. The serial input data stream has a full swing form. The decoding unit receives and decodes the parallel input data and generates an input data signal according to the decoded parallel input data.
    Type: Application
    Filed: December 31, 2013
    Publication date: April 24, 2014
    Applicant: MEDIATEK INC.
    Inventors: Wei-Cheng GU, Chung-Hung TSAI, Chun-Nan LI, Yi-Hsi CHEN
  • Patent number: 8692699
    Abstract: In one embodiment, an apparatus may include a clock generator to generate a format clock signal. The apparatus may also include a serializer to generate serial data based on a transmit clock signal and parallel input data. The apparatus may also include a signal generator to generate at least two differential signals based on the format clock signal and the serial data.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: April 8, 2014
    Assignee: Intel Corporation
    Inventor: Wei-Lien Yang
  • Patent number: 8692698
    Abstract: The invention relates to a method and a system for external, digital coding of a baseband or intermediate-frequency signal. Initially, a digital datastream is converted in a coding device into a digital-baseband signal in the time domain or into a digital intermediate-frequency signal in the time domain. The digitally generated signal is output via an asynchronous-serial interface of the coding device to another device. Such a device also provides an asynchronous-serial interface, which is connected to the asynchronous-serial interface of the coding device. The device reads in the output digital-baseband signal or intermediate-frequency signal for further processing.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: April 8, 2014
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Manfred Reitmeier, Cornelius Heinemann
  • Patent number: 8686882
    Abstract: A high-frequency semiconductor switch includes a serial-parallel conversion circuit, a power supply circuit, and a drive circuit. In the serial-parallel conversion circuit, a parallel data signal is formed from a serial data signal input thereto. In the power supply circuit, a first positive voltage, a second positive voltage, and a negative voltage are formed from a high-potential power source supplied thereto. The drive circuit is supplied with the first positive voltage, the second positive voltage, and the negative voltage, and includes an inverter to which the parallel data signal is input and a differential type of level shifter to which the parallel data signal and the output signal of the inverter is provided. The drive circuit outputs the second positive voltage as a high level signal, and the negative voltage as a low level signal, to a switching circuit, and the switching circuit performs selective switching based thereon.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: April 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiki Seshita
  • Patent number: 8648739
    Abstract: A transmission interface includes a first pin, a second pin, a conversion unit, and a decoding unit. The conversion unit receives a serial input data stream via the first pin and receives a serial clock via the second pin. The conversion unit converts the serial input data stream to parallel input data and converts the serial clock to a parallel clock. The serial input data stream has a full swing form. The decoding unit receives and decodes the parallel input data and generates an input data signal according to the decoded parallel input data.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: February 11, 2014
    Assignee: Mediatek Inc.
    Inventors: Wei-Cheng Ku, Chung-Hung Tsai, Chun-Nan Li, Yi-Hsi Chen
  • Patent number: 8643516
    Abstract: A method for converting parallel data having a certain word size to serial data, comprises the steps of: loading a first segment of a word of the parallel data into a shift register having a first size, and inputting remaining segments of the word into two or more multiplexers connected in series for selecting a next segment of the word; selecting the next segment of the word to load into the shift register; shifting out the loaded segment of the word in the shift register as serial data output; loading the selected next segment of the word into the shift register; and repeating the selecting, shifting, and loading the next segment steps until all the remaining segments of the word have been shifted as serial data output.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: February 4, 2014
    Assignee: Kool Chip, Inc.
    Inventor: Venkata N. S. N. Rao
  • Patent number: 8624762
    Abstract: The present invention refers to a signal concentrator comprising: a parallel to serial conversion device comprising a plurality of parallel inputs and a serial output, a control unit comprising detection means adapted for detecting the activity of said plurality of parallel inputs of said parallel to serial conversion device, indication means adapted for indicating the active parallel inputs to the parallel to serial conversion device and controlling means adapted for setting an operating bitrate of the serial output in function of said activity of said plurality of parallel inputs.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: January 7, 2014
    Assignee: Alcatel Lucent
    Inventors: Olivier Rival, Annalisa Morea
  • Patent number: 8624761
    Abstract: The present disclosure is directed to a system and method for serializing data streams. In some implementations, a device includes a sapphire substrate and an integrated circuit formed on the sapphire substrate. The integrated circuit is configured to receive a plurality of digital signals from a detector and successively multiplex the plurality of digital signals to generate a serialized signal with a data rate approximately 4 Gb/s or greater, the integrated circuit having a feature size of approximately 0.10 ?m or greater.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: January 7, 2014
    Assignee: Southern Methodist University
    Inventors: Datao Gong, Tiankuan Liu, Jingbo Ye
  • Publication number: 20140002283
    Abstract: In one embodiment, an apparatus may include a de-serializer to convert serial data into two parallel data streams, and a control unit to provide a first update signal and a second update signal based on a bit count of the serial data. The apparatus may further include a target component having an input bus, the input bus including a first portion and a second portion. The apparatus may further include a first output unit to provide the first set of parallel data to the first portion of the input bus, and a second output unit to provide the second set of parallel data to the second portion of the input bus.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Inventor: WEI-LIEN YANG