Abstract: A pseudo-orthogonal code generator is provided. The pseudo-orthogonal code generator simplifies overall configuration and provides a more efficient operating speed by implementing a pseudo-orthogonal code generator using combined circuits instead of using a read only memory (ROM) circuit. The pseudo-orthogonal code generator reduces its overall size by reducing gate area.

Abstract: Passive signal combiners are employed to transform at least one signal from one domain to another. In some aspects the transformation comprises an NFL an IFFT, a DFT, or an IDFT. In some implementations the passive signal combiners comprise a set of planar waveguides (e.g., which may be referred to as beamformers or Rotman lenses) that have multiple inputs and outputs and are configured to provide orthogonal output signals. In some implementations an electrical signal (e.g., received via an antenna element) is coupled to passive beamformers that transform the electrical signal from one domain to another domain. Here, a transformation of the electrical signal by a given passive beamformer may have a first resolution, and outputs from the passive beamformers may correspond to orthogonal groups. A combiner circuit may be used to combine the outputs from the passive beamformers and produce a combined output having a second resolution and an associated error.

Abstract: The present invention is to provide a method for encoding and decoding serial signals formed by a plurality of color lights, which is applied to an encoding/decoding system comprising an encoding device and a decoding device, and comprises steps of generating a driving signal corresponding to at least one first serial code set by the encoding device, so as to drive a multi-color LED to generate a plurality of color lights having different wavelengths and interval time of flash intervals; and receiving the color lights by the decoding device, decoding the color lights according to a decoding procedure of the decoding device for obtaining the first serial code set, and sending an actuation signal when determining that the first serial code set is identical to a second serial code set, so as to provide a variety of more sophisticated, safer and uneasy interfered encoding/decoding functions to various wireless control procedures.

Abstract: A dual purpose serializer/de-serializer (SerDes) for point-to-point and point-to-multipoint communication. A configurable SerDes can be designed to operate in one of a plurality of operating modes. Selection between the plurality of operating modes can be based on information received via a management interface. In one example, the various operating modes can be defined with different locking times and jitter characteristics.

Abstract: A multi-speed burst mode serializer/de-serializer (SerDes) is configurable and can operate in one of a plurality of operating modes. The plurality of operating modes correspond to the reception of signals from optical network units that operate at different nominal speeds. These various modes of operation can enable a single SerDes design to apply to a variety of speeds and network configurations (e.g., point-to-point or point-to-multipoint). In one example, the design can be initially configured for operation with a single ONT or a network of ONTs at a single speed, or can be dynamically configured during operation for use with a network of ONTs operating at different speeds.

Abstract: A shift register SR configured to successively take in and hold input serial data on the basis of a first clock signal, a pattern detection section configured to detect a predetermined pattern contained in the serial data taken in the shift resister and a second clock generation section configured to determine timing of output of the serial data held in the shift register on the basis of a result of this detection are provided to detect the desired pattern contained in the serial data in the course of transferring the serial data for conversion from the serial data to parallel data to the shift resister, and to determine timing of conversion to the parallel data on the basis of a result of this detection, thus reducing the latency and achieving an improvement in communication speed and a reduction in circuit area.

Abstract: An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and a channel of high-speed serial data signal interface (e.g., transceiver) circuitry. To facilitate enabling the integrated circuit to support any of many possible different high-speed serial communication protocols, the channel is hard-wired to include a parallel data bus of fixed width for exchanging parallel data with the programmable circuitry. Regardless of the protocol being implemented, the full width of this bus is always used. A portion of the programmable circuitry is programmed to convert data between the block width and a group width, which can be different from the block width and which is used for the data elsewhere in the integrated circuit.

Abstract: A serial signal receiving device, includes: a serial-parallel converter that converts a transmitted serial signal into a parallel signal, wherein the serialized signal is obtained by the plural signal; a storage unit that stores phase difference information indicating a phase difference among the plural signals; and a correcting unit that corrects a phase relation among the plural signals of the parallel signal output from the serial-parallel converter based on the phase difference information stored by the storage unit.

Abstract: In a stacked semiconductor device in which a plurality of through silicon vias used for data transfer are shared among a plurality of semiconductor chips, a first semiconductor chip included in the semiconductor chips holds through silicon via switching information for specifying a through silicon via among the through silicon vias to be used for data transfer, and transfers the through silicon via switching information to a second semiconductor chip included in the semiconductor chips. According to the present invention, because the through silicon via switching information is transferred from the first semiconductor chip to the second semiconductor chip, a circuit for storing the through silicon via switching information in a nonvolatile manner is not required in the second semiconductor chip. With this arrangement, a chip area of the second semiconductor chip can be reduced.

Abstract: A waveform memory 66 stores data streams with each data stream having M-bit parallel data. A sequence memory 60 stores sequence information and data discard information on the amount of data to discard from the last data in each data stream. A sequencer 62 and a waveform memory controller 64 access the waveform memory 66 to provide the data streams using the sequence information. A barrel shifter 68 shifts data in the data stream according to the number of effective data of the last parallel data in the previous data stream if the number of the effective data is less than M. A data shift controller 100 generates data enables indicating whether the data in the data stream are effective or not based on the data discard information. A combiner 72 combines the effective data in the data stream using the data enables.

Abstract: A parallel-to-serial converting circuit includes a first alignment unit configured to receive and serially align parallel data included in a first group selected from a plurality of parallel data and to output serially aligned parallel data. The parallel-to-serial converting circuit also includes a second alignment unit configured to receive and serially align parallel data included in a second group selected from a plurality of parallel data and to output serially aligned parallel data. The parallel-to-serial converting circuit further includes a third alignment unit configured to serially align and output the serially aligned parallel data that is output from the first alignment unit and the second alignment unit. The first alignment unit and the second alignment unit drive an output node in response to activated data of received parallel data.

Abstract: The invention relates to a method and circuit for aligning a serial bit stream with a parallel output. The method comprises latching Q bits from the serial bit stream into a register, locating a position P of a first bit of a start of frame delimiter (SFD) in the register and discarding P-1 bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output. The circuit comprises a latch, a fault tolerant analysis logic (FTAL) for locating a position P of a first bit of a start of frame delimiter (SFD) in the register and a shift register for discarding P-1 bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output.

Abstract: In one embodiment, a semiconductor integrated device includes a plurality of semiconductor chips each having a first internal circuit and a second internal circuit and being stacked while displaced from each other. The first internal circuit processes a data signal in accordance with a predetermined process. The second internal circuit receives a request signal from a transmission source and determines whether the request signal is a request to itself or not. When the request signal is the request to the second internal circuit itself, the second internal circuit receives a data signal from a transmission source and outputs the data signal to the first internal circuit. When the request signal is not the request to the second internal circuit itself, the second internal circuit transfers the request signal to a transfer destination, receives the data signal from the transmission source and transfers the data signal to the transfer destination.

Abstract: A deserializer for converting serial data into at least one parallel data includes a first flip-flop group, a second flip-flop group and a programmable frequency divider. The first flip-flop group includes a plurality of flip-flops connected in series, where the first flip-flop group is controlled by a first clock signal. The second flip-flop group includes a plurality of flip-flops, where the second flip-flop group is controlled by a second clock signal, and the flip-flops of the second flip-flop group are respectively connected to output nodes of the flip-flops of the first flip-flop group. The programmable frequency divider is coupled to each of the flip-flops of the second flip-flop group, and is utilized for receiving a control signal and generating the second clock signal by performing a frequency-dividing operation according to a frequency-dividing factor set by the control signal.

Abstract: A serializer includes a first stage configured to convert m-bit-wide parallel data into n-bit-wide parallel data, where n is 2x, m?2x+y, x is an integer of at least 1, and y is an integer of at least 1, where the first stage includes a memory unit configured to store the m-bit-wide parallel in response to a timing signal and a first multiplexer configured to output the n-bit-wide parallel data in response to a frequency-multiplied derivative of the timing signal, and a current mode logic (CML) multiplexer stage configured to convert the n-bit-wide parallel data into serial data on successive transitions of n phase-shifted versions of the frequency-multiplied derivative of the timing signal.

Abstract: Serial-to-parallel and parallel-to-serial conversion devices may provide for efficient conversion of serial bit streams into parallel data units (and vice versa). In one implementation, a device may include delay circuits, each of which being configured to receive a serial data stream. A rotator circuit may receive the delayed serial data streams and rearrange bits in the serial data streams. Register circuits may receive the output of the rotator circuit and collectively output, in parallel, a number of bits of one of the serial bit streams.

Abstract: An apparatus and a method for providing serialized HDMI data from an HDMI source to an HDMI sink. An HDMI transmitter may include inputs including control inputs, a deserializer, and a parser. The inputs may receive serialized HDMI data from an HDMI data source. A deserializer may deserialize the serialized HDMI data received on each of the respective inputs and outputting parallel data for each of the inputs. A parser may parse the parallel data output from the deserializer from each of the respective inputs into serial video data at a first clock rate and audio data at a second clock rate. Control inputs of the transmitter may be set to a first mode in which from the deserializer is caused to bypass the parser, and the parallel data is output from the HDMI transmitter.

Abstract: An adaptor for a memory card includes a printed circuit board (PCB) conversion board, a memory card connector, a serial interface connector, a signal convertor, and a parallel interface connector. When a motherboard is connected to the serial interface connector, serial signals output from the motherboard are transmitted to the signal convertor via the serial interface connector. The signal convertor converts the serial signals into parallel signals and transmits the parallel signals to the memory card. When the motherboard is connected to the parallel interface connector, parallel signals output from the motherboard are transmitted to the memory card via the PCB conversion board without any parallel-to-serial signal conversion.

Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Abstract: The invention relates to a method and circuit for aligning a serial bit stream with a parallel output. The method comprises latching Q bits from the serial bit stream into a register, locating a position P of a first bit of a start of frame delimiter (SFD) in the register and discarding P-1 bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output. The circuit comprises a latch, a fault tolerant analysis logic (FTAL) for locating a position P of a first bit of a start of frame delimiter (SFD) in the register and a shift register for discarding P-1 bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output.

Abstract: A digital signal receiver for a high-bitrate digital signal has a serial signal input (20, 20?) and a number of N parallel digital signal outputs (26) with N>1. The receiver contains at least N+1 digital sampling channels (31-35), a Q-monitor (37, 38) for comparing the output signal of at least two of the sampling channels (31-35), and a switch fabric (36) for controllably connecting N of the sampling channels (31-35) to the outputs (26) and at least two of the sampling channels (31-35) to the Q-monitor (37, 38). This allows to use N of the sampling channels to provide the N output signals while at the same time, the at least one remaining sampling channel can be used by the Q-monitor to scan an eye diagram.

Abstract: A unit timing signal synchronized with a high-order transmission frame is used for measuring a difference between the number of data pieces of a client signal mapped to the high-frequency frame and the number of data pieces of the output client signal by integrating the difference therebetween for each unit timing signal. Then stuffing and de-stuffing operations are performed so that a integration result is zero.

Abstract: Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

Abstract: A semiconductor device includes a plurality of synchronization blocks configured to sequentially synchronize a plurality of input signals swinging in a complementary metal oxide semiconductor (CMOS) region with multi-phase clock signals to output a plurality of output signals swinging in a current mode logic (CML) region, a plurality of first swing region converting blocks configured to convert the plurality of output signals to a plurality of converted output signals swinging in the CMOS region, a serialization block configured to serialize a plurality of converted output signals, thereby outputting a serialized signal swinging in the CML region, and a second swing region converting block configured to convert the serialized signal to a serialized output signal swinging in the CMOS region.

Abstract: An integrated circuit comprises a first microcontroller unit for executing instructions in accordance with a first clock frequency. The microcontroller located on a first die and includes a first processing core for providing a parallel stream of data in accordance with the first clock frequency. A second microcontroller unit executes instructions in accordance with the first clock frequency. The second microcontroller is located on a second die and includes a second processing core for receiving the parallel stream of data in accordance with the first clock frequency. Capacitive isolation circuitry connected with the first microcontroller unit and the second microcontroller unit provides a high voltage isolation link between the first and the second microcontroller units.

Abstract: Embodiments of the present invention provide a bus architecture utilizing multiple-pumped serial links, and a combination of encoding and serialization to two data streams to transmit and receive a serialized data stream over a bus. The order in which encoding and serialization takes place depends upon the anticipated activity factors of the two data streams, and is chosen to reduce average energy dissipation. Other embodiments are described and claimed.

Abstract: Aspects of the disclosure provide a circuit using digital techniques to generate a differential signal with a low skew. The circuit can include a first switching element configured to receive at least a first logic value and a second logic value, and output a first signal of the differential signal, the second logic value being different from the first logic value. Further, the circuit can include a second switching element configured to receive at least the first logic value and the second logic value, and output a second signal of the differential signal.

Abstract: A system and method for data transmission between an intelligent electronic device (IED) and a device, such as a remote display or input/output (I/O) device, are provided. Each data line of the IED is input into a serializer and transmitted over a serial link to a deserializer and then provided to the inputs of remote device, such as a remote display or input/output (I/O) device. The serial link can be made of any media such as copper, fiber optics, etc. The serial link can be formed as one, two or more channels.

Abstract: A signal transmission system in which a serializer IC connected to first parallel signal wirings and a deserializer IC connected to second parallel signal wirings are connected by a transmission line. Among input terminals of the serializer IC, redundant input terminals which are not connected to the first parallel signal wirings are connected to one wiring obtained by branching off the first parallel signal wirings. When parallel signals are converted into a serial signal, their bit data is arranged into the serial signal which is temporally continuous. Thus, the number of transition times of the serial signal is reduced and radiation noises can be suppressed.

Abstract: A transmission circuit includes a serial clock generator, a serializer and a transmission clock generator. The serial clock generator generates a serial clock. The serializer serializes N-bit parallel data to N-bit serial data in synchronization with the serial clock. The transmission clock generator receives the serial clock to generate a transmission clock that has a same delay as the N-bit serial data, and the data transmission circuit simultaneously transmits the N-bit serial data and the serial clock.

Abstract: A physical layer (PHY) device includes a first encoder that receives a first data stream at a first data rate, that encodes the first data stream using a first type of encoding, and that outputs first encoded data. A second encoder receives a second data stream at a second data rate different than the first data rate, encodes the second data stream using a second type of encoding different than the first type of encoding, and outputs second encoded data. An output selector outputs the first encoded data to a serializer of the PHY when the PHY transmits at the first data rate, and outputs the second encoded data to the serializer when the PHY transmits at the second data rate.

Abstract: A system and method for using one or more clock signals is disclosed. The system includes a clock translator that has a first input to receive a first reference clock signal and a second input to receive a second reference clock signal. The clock translator also includes an output to provide a bit rate clock signal having a clock frequency in a first ratio with respect to the frequency of the first reference clock but having a resolution based on at least a portion of the second reference clock signal. The second reference clock has a faster rate than the first reference clock.

Abstract: A data sort device for converting parallel data to serial data is disclosed and provided. The data sort device may include a plurality of switches for receiving parallel data, each of which are controlled by a respective control signal and configured to alternatingly transmit data bits received via first and second input terminals.

Abstract: A CPU outputs digital data from a built-in RAM to a buffer in response to a request from the buffer. The buffer has a FIFO configured of a plurality of stages, each stage of the FIFO is capable of storing one unit (10 bits) of digital data, the buffer as a whole is capable of storing digital data in number of units equivalent to the number of configured stages. A register captures digital data stored inside the buffer by each unit in synchronous with an output control clock. The digital data stored in the register is outputted to a parallel DAC as data for D/A conversion. A WR signal output timer generates a writing control signal having one shot pulse of “L” in synchronous with the output control clock.

Abstract: A serializer/deserializer is disclosed with a flexible design that allows for sending data streams between computer systems where the power dissipation is markedly reduced by placing the serializer/deserializer in a standby, low power mode between the sending of data. Word data bits are framed and sent along with clock pulses that define when the bits may be reliably received. High speed, typically, CML logic is used for the transmission line drivers and together with the clock pulse, a data word is sent faster than the computer system can send the next word to the serializer/deserializer. The disclosure frames the word and detects the word end, whereupon the system is placed into the standby mode. In addition the serializer/deserializers may be placed in a master/slave arrangement where the slave can be arranged to use the master's clock to send word data bits back to the master.

Abstract: A method, system, and apparatus of a balanced rotator conversion of serialized data are disclosed. In one embodiment, a method to convert serialized data includes acquiring a rotator module output, and generating a balancing signal with a reference module, which operates with a reference frequency. The method further includes processing the rotator module output and the balancing signal in an interpolation module to generate a balanced rotator output. The method may include a rotator module output that is generated by an analog phase rotator when a control voltage is received by the analog phase rotator. The reference module may include an other analog phase rotator to generate a balancing signal. The interpolation module may interpolate the balancing signal and the rotator module output to modulate a phase of the balanced rotator output. The balanced rotator output may include an orthogonal output.

Abstract: There is provided a PLL circuit 15, a voltage follower 19, and an output terminal 23, and a control voltage V1 of a voltage controlled oscillator circuit in the PLL circuit 15 is outputted to the output terminal 23 via the voltage follower 19.

Abstract: A Serializer/Deserializer apparatus comprises a serializer adapted to take N parallel bits of data and shifts them out serially at N times a clock speed to a transmitter, a transmitter enable block adapted to start the serializer means, and a count block. The serializer comprises flip-flops and muxes, and is adapted to N parallel bits of data and shifts them out serially at N times a clock speed to a transmitter. The transmitter enable block comprises an inverter and flip-flops, and is adapted to start the serializer. The transmitter enable block comprises an inverter, flip-flops, and a NOR gate, and is adapted to create a waveform which programs data loading in the serializer.

Abstract: A parallel-serial conversion circuit in which clock frequency and data width can be flexibly configured. The parallel-serial conversion circuit converts m×n bit parallel data (m and n being natural numbers), of clock frequency f, into 1-bit serial data of clock frequency f×m×n. The first converter converts m×n bit parallel data into m-bit parallel data (Dp) of clock frequency f×n. A second converter converts the m-bit parallel data (Dp) of clock frequency f×n, outputted from the first converter, into 1-bit serial data (bout) of clock frequency f×n×m. A clock signal generation circuit respectively supplies a clock signal (CK1), of frequency f×n, to the first converter, and a clock signal (CK2), of frequency f×m×n, to the second converter.

Abstract: An integrated circuit comprises a first microcontroller unit located on a first die. The first microcontroller unit includes a first processing core for providing a parallel stream of data. A second microcontroller unit is located on a second die and includes a second processing core for receiving the parallel stream of data. Voltage isolation circuitry transmits data from the parallel data stream between the first microcontroller and the second microcontroller in a serial data stream and provides galvanic isolation between the first microcontroller unit and the second microcontroller unit.

Abstract: A system and process for receiving a variable pulse width signal and measuring and serially sending the measurements to a receiver that deserializes and regenerates the variable pulse width signal. Data bits may be embedded with the variable pulse width clock measurements and serially sent out. The measurements are illustratively accomplished using a reference clock and a phase locked loop.

Abstract: A memory system includes a memory controller that issues command signals and a reference-clock signal to a memory device. The edge rate of the reference-clock signal is lower than the bit rate of the command signals, so the memory device multiplies the reference clock signal to develop a command-recovery clock signal with which to sample the incoming command signals. The memory controller issues the command signals as a series of multi-bit command words aligned with edges of the reference-clock signal so that the memory device can use edges of the reference clock signal for command-word alignment.

Abstract: A system for receiving Joint Task Action Group (JTAG) data bits from a device under test includes a deserializer that receives serial messages from the device under test and forms data frames based on the serial messages. A frame sync module communicates with the deserializer and forms JTAG data bits based on the data frames. N virtual JTAG test access ports (VTAPs), each having an input and an output. The N VTAPs are connected in a daisy chain and the input of a first VTAP receives the JTAG data bits from the frame sync module.

Abstract: A system including a serializer/deserializer (SERDES) block including a first SERDES lane, a second SERDES lane, a third SERDES lane, and a fourth SERDES lane; a physical coding sublayer (PCS) block including a layout select tag, a first PCS lane connected to the fourth SERDES lane, a second PCS lane connected to the third SERDES lane, a third PCS lane connected to the second SERDES lane, and a fourth PCS lane connected to the first SERDES lane; and a media access control (MAC) layer block including a first plurality of pins connected to the first PCS lane, a second plurality of pins connected to the second PCS lane, a third plurality of pins connected to the third PCS lane, and a fourth plurality of pins connected to the fourth PCS lane, wherein the PCS block is configured to map the first SERDES lane to the first plurality of pins, the second SERDES lane to the second plurality of pins, the third SERDES lane to the third plurality of pins, and the fourth SERDES lane to the fourth plurality of pins based on

Abstract: A device for parallel-serial conversion of several evaluation parameters determined respectively by a detector from detected signal values. The device includes a primary buffer memory for the synchronized buffering of each determined evaluation parameter, a synchronization unit for the generation of a synchronization signal for the synchronized buffering and a unit for the serial readout of the evaluation parameters stored in a synchronized manner in the primary buffer memory. A synchronization signal generated by the synchronization unit is derived from a release signal which provides the highest data rate of all the release signals associated respectively with the determined evaluation parameters.

Abstract: A high-speed serial interface circuit includes a data receiver circuit, a clock signal receiver circuit, a logic circuit block that includes at least a serial/parallel conversion circuit, a free-running clock signal generation circuit, a clock signal detection circuit, and an output mask circuit. The clock signal detection circuit compares a received clock signal from the clock signal receiver circuit with a free-running clock signal from the free-running clock signal generation circuit to detect whether or not clock signals are transferred through differential clock signal lines. When the clock signal detection circuit has detected that the clock signals are not transferred through the differential clock signal lines, the output mask circuit masks an output signal from the logic circuit block so that the output signal is not transmitted to a circuit in the subsequent stage.

Abstract: A physical layer device (PLD) includes a first serializer-deserializer (SERDES) device and a second SERDES device. Each SERDES device includes an analog portion with a serial port that is configured to communicate serial data with various network devices, and a digital portion that is configured to communicate parallel data with other various network devices. The PLD includes a first signal path that is configured to route serial data signals between the analog portions of the SERDES devices, bypassing the digital portions of the SERDES devices. Therefore, the SERDES devices can directly communicate serial data without performing parallel data conversion. A second signal path is configured to route recovered clock and data signals between the analog portions of the SERDES devices, but still bypassing the digital portions of the SERDES devices. The recovered clock and data signals are then regenerated before being transmitted over a network device.

Abstract: A serial signal receiving device, includes: a serial-parallel converter that converts a transmitted serial signal into a parallel signal, wherein the serialized signal is obtained by the plural signal; a storage unit that stores phase difference information indicating a phase difference among the plural signals; and a correcting unit that corrects a phase relation among the plural signals of the parallel signal output from the serial-parallel converter based on the phase difference information stored by the storage unit.

Abstract: An electronic device is described. The electronic device includes a first integrated circuit (IC) and a second integrated circuit (IC). The electronic device also includes a multiplexer configured to multiplex a parallel data signal into a serial data signal, and a transmitter configured to transmit the serial data signal from the first IC to the second IC. The electronic device further includes a receiver configured to receive the serial data signal. The receiver includes a clamp circuit configured to clamp the voltage swing of an analog node within a determined range. The clamp also helps to extend the bandwidth of the receiver.

Abstract: The invention eliminates a race condition without restricting reception speed. The invention provides a method of designing a serial-to-parallel conversion circuit, the method including determining a rule for data and a strobe when a first-stage memory device in a shift register latches data and when the memory device holds the data; providing a logical circuit for generating an output conforming to the rule at a data input side of the shift register; and shifting a data latch timing of the memory device by a half-period.