Serial To Parallel Patents (Class 341/100)
  • Patent number: 7847712
    Abstract: An adaptor for a memory card includes a printed circuit board (PCB) conversion board, a memory card connector, a serial interface connector, a signal convertor, and a parallel interface connector. When a motherboard is connected to the serial interface connector, serial signals output from the motherboard are transmitted to the signal convertor via the serial interface connector. The signal convertor converts the serial signals into parallel signals and transmits the parallel signals to the memory card. When the motherboard is connected to the parallel interface connector, parallel signals output from the motherboard are transmitted to the memory card via the PCB conversion board without any parallel-to-serial signal conversion.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: December 7, 2010
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Xiao-Zhu Chen, Zhen-Xing Ye
  • Patent number: 7848318
    Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: December 7, 2010
    Assignee: Altera Corporation
    Inventors: Toan Thanh Nguyen, Thungoc Tran, Sergey Yuryevich Shumarayev, Arch Zaliznyak, Shoujun Wang, Ramanand Venkata, Chong Lee
  • Publication number: 20100302079
    Abstract: The invention relates to a method and circuit for aligning a serial bit stream with a parallel output. The method comprises latching Q bits from the serial bit stream into a register, locating a position P of a first bit of a start of frame delimiter (SFD) in the register and discarding P-1 bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output. The circuit comprises a latch, a fault tolerant analysis logic (FTAL) for locating a position P of a first bit of a start of frame delimiter (SFD) in the register and a shift register for discarding P-1 bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output.
    Type: Application
    Filed: May 29, 2009
    Publication date: December 2, 2010
    Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
    Inventors: Robert Brunner, David Gordon, Martin Julien, Ludovic Beliveau
  • Patent number: 7835464
    Abstract: A digital signal receiver for a high-bitrate digital signal has a serial signal input (20, 20?) and a number of N parallel digital signal outputs (26) with N>1. The receiver contains at least N+1 digital sampling channels (31-35), a Q-monitor (37, 38) for comparing the output signal of at least two of the sampling channels (31-35), and a switch fabric (36) for controllably connecting N of the sampling channels (31-35) to the outputs (26) and at least two of the sampling channels (31-35) to the Q-monitor (37, 38). This allows to use N of the sampling channels to provide the N output signals while at the same time, the at least one remaining sampling channel can be used by the Q-monitor to scan an eye diagram.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: November 16, 2010
    Assignee: Alcatel Lucent
    Inventor: Helmut Preisach
  • Patent number: 7830280
    Abstract: Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: November 9, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Jun Bae, Seong-Jin Jang, Kwang-Il Park, Woo-Jin Lee
  • Patent number: 7830282
    Abstract: A semiconductor device includes a plurality of synchronization blocks configured to sequentially synchronize a plurality of input signals swinging in a complementary metal oxide semiconductor (CMOS) region with multi-phase clock signals to output a plurality of output signals swinging in a current mode logic (CML) region, a plurality of first swing region converting blocks configured to convert the plurality of output signals to a plurality of converted output signals swinging in the CMOS region, a serialization block configured to serialize a plurality of converted output signals, thereby outputting a serialized signal swinging in the CML region, and a second swing region converting block configured to convert the serialized signal to a serialized output signal swinging in the CMOS region.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: November 9, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jun-Woo Lee, Taek-Sang Song
  • Patent number: 7830924
    Abstract: A unit timing signal synchronized with a high-order transmission frame is used for measuring a difference between the number of data pieces of a client signal mapped to the high-frequency frame and the number of data pieces of the output client signal by integrating the difference therebetween for each unit timing signal. Then stuffing and de-stuffing operations are performed so that a integration result is zero.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: November 9, 2010
    Assignee: Hitachi Communication Technologies, Ltd.
    Inventors: Kenji Kawamura, Takashi Funada, Masatoshi Shibasaki, Yoshimasa Kusano, Yusuke Honda, Hiromi Murakami
  • Patent number: 7821428
    Abstract: An integrated circuit comprises a first microcontroller unit for executing instructions in accordance with a first clock frequency. The microcontroller located on a first die and includes a first processing core for providing a parallel stream of data in accordance with the first clock frequency. A second microcontroller unit executes instructions in accordance with the first clock frequency. The second microcontroller is located on a second die and includes a second processing core for receiving the parallel stream of data in accordance with the first clock frequency. Capacitive isolation circuitry connected with the first microcontroller unit and the second microcontroller unit provides a high voltage isolation link between the first and the second microcontroller units.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: October 26, 2010
    Assignee: Silicon Laboratories Inc.
    Inventors: Ka Y. Leung, Donald E. Alfano, David P. Bresemann
  • Patent number: 7817068
    Abstract: Embodiments of the present invention provide a bus architecture utilizing multiple-pumped serial links, and a combination of encoding and serialization to two data streams to transmit and receive a serialized data stream over a bus. The order in which encoding and serialization takes place depends upon the anticipated activity factors of the two data streams, and is chosen to reduce average energy dissipation. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: October 19, 2010
    Assignee: Intel Corporation
    Inventors: Maged Ghoneima, Muhammad M. Khellah, Vivek K. De
  • Patent number: 7804431
    Abstract: Aspects of the disclosure provide a circuit using digital techniques to generate a differential signal with a low skew. The circuit can include a first switching element configured to receive at least a first logic value and a second logic value, and output a first signal of the differential signal, the second logic value being different from the first logic value. Further, the circuit can include a second switching element configured to receive at least the first logic value and the second logic value, and output a second signal of the differential signal.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: September 28, 2010
    Assignee: Marvell Israel (MISL) Ltd.
    Inventors: Ido Bourstein, Reuven Ecker
  • Publication number: 20100238983
    Abstract: A system and method for data transmission between an intelligent electronic device (IED) and a device, such as a remote display or input/output (I/O) device, are provided. Each data line of the IED is input into a serializer and transmitted over a serial link to a deserializer and then provided to the inputs of remote device, such as a remote display or input/output (I/O) device. The serial link can be made of any media such as copper, fiber optics, etc. The serial link can be formed as one, two or more channels.
    Type: Application
    Filed: June 1, 2010
    Publication date: September 23, 2010
    Applicant: ELECTRO INDUSTRIES/GAUGE TECH.
    Inventor: Tibor Banhegyesi
  • Publication number: 20100238055
    Abstract: A signal transmission system in which a serializer IC connected to first parallel signal wirings and a deserializer IC connected to second parallel signal wirings are connected by a transmission line. Among input terminals of the serializer IC, redundant input terminals which are not connected to the first parallel signal wirings are connected to one wiring obtained by branching off the first parallel signal wirings. When parallel signals are converted into a serial signal, their bit data is arranged into the serial signal which is temporally continuous. Thus, the number of transition times of the serial signal is reduced and radiation noises can be suppressed.
    Type: Application
    Filed: December 9, 2008
    Publication date: September 23, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Shinichi Nishimura
  • Patent number: 7796063
    Abstract: A transmission circuit includes a serial clock generator, a serializer and a transmission clock generator. The serial clock generator generates a serial clock. The serializer serializes N-bit parallel data to N-bit serial data in synchronization with the serial clock. The transmission clock generator receives the serial clock to generate a transmission clock that has a same delay as the N-bit serial data, and the data transmission circuit simultaneously transmits the N-bit serial data and the serial clock.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: September 14, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Seok Kim, Nam-Hyun Kim, Cheon-Oh Lee, Han-Kyul Lim
  • Patent number: 7791512
    Abstract: A physical layer (PHY) device includes a first encoder that receives a first data stream at a first data rate, that encodes the first data stream using a first type of encoding, and that outputs first encoded data. A second encoder receives a second data stream at a second data rate different than the first data rate, encodes the second data stream using a second type of encoding different than the first type of encoding, and outputs second encoded data. An output selector outputs the first encoded data to a serializer of the PHY when the PHY transmits at the first data rate, and outputs the second encoded data to the serializer when the PHY transmits at the second data rate.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: September 7, 2010
    Assignee: Marvell International Ltd.
    Inventors: William Lo, Calvin Fang
  • Patent number: 7773006
    Abstract: A system and method for using one or more clock signals is disclosed. The system includes a clock translator that has a first input to receive a first reference clock signal and a second input to receive a second reference clock signal. The clock translator also includes an output to provide a bit rate clock signal having a clock frequency in a first ratio with respect to the frequency of the first reference clock but having a resolution based on at least a portion of the second reference clock signal. The second reference clock has a faster rate than the first reference clock.
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: August 10, 2010
    Assignee: Sigmatel, Inc.
    Inventor: Darrell Eugene Tinker
  • Patent number: 7764209
    Abstract: A CPU outputs digital data from a built-in RAM to a buffer in response to a request from the buffer. The buffer has a FIFO configured of a plurality of stages, each stage of the FIFO is capable of storing one unit (10 bits) of digital data, the buffer as a whole is capable of storing digital data in number of units equivalent to the number of configured stages. A register captures digital data stored inside the buffer by each unit in synchronous with an output control clock. The digital data stored in the register is outputted to a parallel DAC as data for D/A conversion. A WR signal output timer generates a writing control signal having one shot pulse of “L” in synchronous with the output control clock.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: July 27, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Isao Tottori, Masaru Hagiwara
  • Patent number: 7764206
    Abstract: A data sort device for converting parallel data to serial data is disclosed and provided. The data sort device may include a plurality of switches for receiving parallel data, each of which are controlled by a respective control signal and configured to alternatingly transmit data bits received via first and second input terminals.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: July 27, 2010
    Assignee: Round Rock Research, LLC
    Inventors: Christopher K. Morzano, Wen Li
  • Patent number: 7760116
    Abstract: A method, system, and apparatus of a balanced rotator conversion of serialized data are disclosed. In one embodiment, a method to convert serialized data includes acquiring a rotator module output, and generating a balancing signal with a reference module, which operates with a reference frequency. The method further includes processing the rotator module output and the balancing signal in an interpolation module to generate a balanced rotator output. The method may include a rotator module output that is generated by an analog phase rotator when a control voltage is received by the analog phase rotator. The reference module may include an other analog phase rotator to generate a balancing signal. The interpolation module may interpolate the balancing signal and the rotator module output to modulate a phase of the balanced rotator output. The balanced rotator output may include an orthogonal output.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: July 20, 2010
    Assignee: Chrontel, Inc
    Inventors: Yin Liu, Guangyong Zhao, Huaming Chong
  • Patent number: 7760115
    Abstract: A serializer/deserializer is disclosed with a flexible design that allows for sending data streams between computer systems where the power dissipation is markedly reduced by placing the serializer/deserializer in a standby, low power mode between the sending of data. Word data bits are framed and sent along with clock pulses that define when the bits may be reliably received. High speed, typically, CML logic is used for the transmission line drivers and together with the clock pulse, a data word is sent faster than the computer system can send the next word to the serializer/deserializer. The disclosure frames the word and detects the word end, whereupon the system is placed into the standby mode. In addition the serializer/deserializers may be placed in a master/slave arrangement where the slave can be arranged to use the master's clock to send word data bits back to the master.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: July 20, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James B. Boomer, Michael L. Fowler, Steven Mark Macaluso
  • Patent number: 7755438
    Abstract: There is provided a PLL circuit 15, a voltage follower 19, and an output terminal 23, and a control voltage V1 of a voltage controlled oscillator circuit in the PLL circuit 15 is outputted to the output terminal 23 via the voltage follower 19.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: July 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Nobuyuki Morikoshi
  • Patent number: 7746251
    Abstract: A Serializer/Deserializer apparatus comprises a serializer adapted to take N parallel bits of data and shifts them out serially at N times a clock speed to a transmitter, a transmitter enable block adapted to start the serializer means, and a count block. The serializer comprises flip-flops and muxes, and is adapted to N parallel bits of data and shifts them out serially at N times a clock speed to a transmitter. The transmitter enable block comprises an inverter and flip-flops, and is adapted to start the serializer. The transmitter enable block comprises an inverter, flip-flops, and a NOR gate, and is adapted to create a waveform which programs data loading in the serializer.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: June 29, 2010
    Assignee: Qualcomm Incorporated
    Inventor: Jason Gonzalez
  • Publication number: 20100149137
    Abstract: A parallel-serial conversion circuit in which clock frequency and data width can be flexibly configured. The parallel-serial conversion circuit converts m×n bit parallel data (m and n being natural numbers), of clock frequency f, into 1-bit serial data of clock frequency f×m×n. The first converter converts m×n bit parallel data into m-bit parallel data (Dp) of clock frequency f×n. A second converter converts the m-bit parallel data (Dp) of clock frequency f×n, outputted from the first converter, into 1-bit serial data (bout) of clock frequency f×n×m. A clock signal generation circuit respectively supplies a clock signal (CK1), of frequency f×n, to the first converter, and a clock signal (CK2), of frequency f×m×n, to the second converter.
    Type: Application
    Filed: September 14, 2006
    Publication date: June 17, 2010
    Applicant: ROHM CO., LTD.
    Inventor: Shinichi Saito
  • Patent number: 7737871
    Abstract: An integrated circuit comprises a first microcontroller unit located on a first die. The first microcontroller unit includes a first processing core for providing a parallel stream of data. A second microcontroller unit is located on a second die and includes a second processing core for receiving the parallel stream of data. Voltage isolation circuitry transmits data from the parallel data stream between the first microcontroller and the second microcontroller in a serial data stream and provides galvanic isolation between the first microcontroller unit and the second microcontroller unit.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: June 15, 2010
    Assignee: Silicon Laboratories Inc.
    Inventors: Ka Y. Leung, Donald E. Alfano, David P. Bresemann
  • Patent number: 7733248
    Abstract: A system and process for receiving a variable pulse width signal and measuring and serially sending the measurements to a receiver that deserializes and regenerates the variable pulse width signal. Data bits may be embedded with the variable pulse width clock measurements and serially sent out. The measurements are illustratively accomplished using a reference clock and a phase locked loop.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: June 8, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Seth Prentice
  • Publication number: 20100128542
    Abstract: A memory system includes a memory controller that issues command signals and a reference-clock signal to a memory device. The edge rate of the reference-clock signal is lower than the bit rate of the command signals, so the memory device multiplies the reference clock signal to develop a command-recovery clock signal with which to sample the incoming command signals. The memory controller issues the command signals as a series of multi-bit command words aligned with edges of the reference-clock signal so that the memory device can use edges of the reference clock signal for command-word alignment.
    Type: Application
    Filed: May 8, 2008
    Publication date: May 27, 2010
    Applicant: Rambus Inc.
    Inventors: Jade M. Kizer, Richard E. Perego
  • Patent number: 7719450
    Abstract: A device for parallel-serial conversion of several evaluation parameters determined respectively by a detector from detected signal values. The device includes a primary buffer memory for the synchronized buffering of each determined evaluation parameter, a synchronization unit for the generation of a synchronization signal for the synchronized buffering and a unit for the serial readout of the evaluation parameters stored in a synchronized manner in the primary buffer memory. A synchronization signal generated by the synchronization unit is derived from a release signal which provides the highest data rate of all the release signals associated respectively with the determined evaluation parameters.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: May 18, 2010
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Johann Huber, Michael Reinhold
  • Patent number: 7721167
    Abstract: A system for receiving Joint Task Action Group (JTAG) data bits from a device under test includes a deserializer that receives serial messages from the device under test and forms data frames based on the serial messages. A frame sync module communicates with the deserializer and forms JTAG data bits based on the data frames. N virtual JTAG test access ports (VTAPs), each having an input and an output. The N VTAPs are connected in a daisy chain and the input of a first VTAP receives the JTAG data bits from the frame sync module.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: May 18, 2010
    Assignee: Marvell International Ltd.
    Inventors: Saeed Azimi, Son Ho, Daniel Smathers
  • Patent number: 7719449
    Abstract: A system including a serializer/deserializer (SERDES) block including a first SERDES lane, a second SERDES lane, a third SERDES lane, and a fourth SERDES lane; a physical coding sublayer (PCS) block including a layout select tag, a first PCS lane connected to the fourth SERDES lane, a second PCS lane connected to the third SERDES lane, a third PCS lane connected to the second SERDES lane, and a fourth PCS lane connected to the first SERDES lane; and a media access control (MAC) layer block including a first plurality of pins connected to the first PCS lane, a second plurality of pins connected to the second PCS lane, a third plurality of pins connected to the third PCS lane, and a fourth plurality of pins connected to the fourth PCS lane, wherein the PCS block is configured to map the first SERDES lane to the first plurality of pins, the second SERDES lane to the second plurality of pins, the third SERDES lane to the third plurality of pins, and the fourth SERDES lane to the fourth plurality of pins based on
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: May 18, 2010
    Assignee: Agate Logic, Inc.
    Inventors: Nadeem Fahmi, Jason Alexander Jones
  • Publication number: 20100103002
    Abstract: A high-speed serial interface circuit includes a data receiver circuit, a clock signal receiver circuit, a logic circuit block that includes at least a serial/parallel conversion circuit, a free-running clock signal generation circuit, a clock signal detection circuit, and an output mask circuit. The clock signal detection circuit compares a received clock signal from the clock signal receiver circuit with a free-running clock signal from the free-running clock signal generation circuit to detect whether or not clock signals are transferred through differential clock signal lines. When the clock signal detection circuit has detected that the clock signals are not transferred through the differential clock signal lines, the output mask circuit masks an output signal from the logic circuit block so that the output signal is not transmitted to a circuit in the subsequent stage.
    Type: Application
    Filed: December 30, 2009
    Publication date: April 29, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Takemi YONEZAWA, Kenichi OE
  • Patent number: 7706433
    Abstract: A physical layer device (PLD) includes a first serializer-deserializer (SERDES) device and a second SERDES device. Each SERDES device includes an analog portion with a serial port that is configured to communicate serial data with various network devices, and a digital portion that is configured to communicate parallel data with other various network devices. The PLD includes a first signal path that is configured to route serial data signals between the analog portions of the SERDES devices, bypassing the digital portions of the SERDES devices. Therefore, the SERDES devices can directly communicate serial data without performing parallel data conversion. A second signal path is configured to route recovered clock and data signals between the analog portions of the SERDES devices, but still bypassing the digital portions of the SERDES devices. The recovered clock and data signals are then regenerated before being transmitted over a network device.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: April 27, 2010
    Assignee: Broadcom Corporation
    Inventors: Kevin T. Chan, Michael Q. Le
  • Publication number: 20100097249
    Abstract: A serial signal receiving device, includes: a serial-parallel converter that converts a transmitted serial signal into a parallel signal, wherein the serialized signal is obtained by the plural signal; a storage unit that stores phase difference information indicating a phase difference among the plural signals; and a correcting unit that corrects a phase relation among the plural signals of the parallel signal output from the serial-parallel converter based on the phase difference information stored by the storage unit.
    Type: Application
    Filed: April 30, 2009
    Publication date: April 22, 2010
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Hirokazu TSUBOTA, Toshio HISAMURA, Atsushi UGAJIN
  • Patent number: 7692565
    Abstract: An electronic device is described. The electronic device includes a first integrated circuit (IC) and a second integrated circuit (IC). The electronic device also includes a multiplexer configured to multiplex a parallel data signal into a serial data signal, and a transmitter configured to transmit the serial data signal from the first IC to the second IC. The electronic device further includes a receiver configured to receive the serial data signal. The receiver includes a clamp circuit configured to clamp the voltage swing of an analog node within a determined range. The clamp also helps to extend the bandwidth of the receiver.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: April 6, 2010
    Assignee: QUALCOMM Incorporated
    Inventors: Vivek Mohan, Abhay Dixit
  • Patent number: 7692564
    Abstract: The invention eliminates a race condition without restricting reception speed. The invention provides a method of designing a serial-to-parallel conversion circuit, the method including determining a rule for data and a strobe when a first-stage memory device in a shift register latches data and when the memory device holds the data; providing a logical circuit for generating an output conforming to the rule at a data input side of the shift register; and shifting a data latch timing of the memory device by a half-period.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: April 6, 2010
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Shigeru Ishii, Masaharu Nomachi
  • Publication number: 20100079316
    Abstract: A digital signal transmitting apparatus includes an encoder which converts parallel input signals of multiple channels into serial data in a manner synchronized with a first clock signal, and a decoder which converts the serial data into parallel output signals of the multiple channels in a manner synchronized with a second clock signal operating in a manner asynchronous with the first clock signal. The serial data has a different period and a different duty factor corresponding to each combination of the logical values of the parallel input signals of the multiple channels.
    Type: Application
    Filed: September 30, 2009
    Publication date: April 1, 2010
    Applicant: TDK CORPORATION
    Inventors: Reiji Okuno, Takakazu Imai, Takeo Gokita
  • Patent number: 7683812
    Abstract: This invention relates to a pattern recognition correlator implemented entirely in the electronic domain. The correlator has a serial to parallel conversion means to convert input serial binary data into at least one input parallel binary electrical signal and a comparator to compare the or each input parallel data signal with a reference parallel binary data signal. The serial to parallel conversion means may comprises a demultiplexer to effectively slow the data update rate and a series of latch circuits to provide the parallel data signal. The comparator may be arranged to perform bit addition and may be arranged such that a zero total sum is an indication of correlation. The bit addition may be performed b an array of logic gates.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: March 23, 2010
    Assignee: QinetiQ Limited
    Inventor: Andrew Charles Lewin
  • Patent number: 7675439
    Abstract: A serial/parallel data conversion apparatus and a method thereof are used to convert serial data into parallel data by a delay pulse and three stage registers, wherein the device includes a first data register, a second data register, a third data register, a frequency divider and a delay controller. Moreover, the first data register converts the serial data into the parallel data according to a first working clock signal. The frequency divider performs a frequency division for the first working clock signal for producing a second working clock signal. The second data register acquires the parallel data from the first register according to the second working clock signal. The delay controller delays the second working clock signal to produce a third working clock signal. Finally, the third data register obtains the parallel data from the second register according to the third working clock signal.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: March 9, 2010
    Assignee: Altek Corporation
    Inventors: Ching Yen Chang, Wen-Bin Wang
  • Patent number: 7675438
    Abstract: A method and a system for transmitting/receiving serial data efficiently by minimizing the transitions of bits in a serial communication system, as well as a serial communication system for the same, are provided. The method for converting coded parallel data into serial data and transmitting the serial data in a serial communication system includes determining a position, in which an information bit of the coded parallel data is found first, the information bit being defined as a bit having a predetermined bit value so that the information bit is not compressed; and serially transmitting the information bit found first and at least one bit following the information bit found first as compressed serial data until the determined position is reached.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: March 9, 2010
    Assignee: Samsung Electronics Co., Ltd
    Inventor: Kang-Min Lee
  • Publication number: 20100045493
    Abstract: A system including a serializer/deserializer (SERDES) block including a first SERDES lane, a second SERDES lane, a third SERDES lane, and a fourth SERDES lane; a physical coding sublayer (PCS) block including a layout select tag, a first PCS lane connected to the fourth SERDES lane, a second PCS lane connected to the third SERDES lane, a third PCS lane connected to the second SERDES lane, and a fourth PCS lane connected to the first SERDES lane; and a media access control (MAC) layer block including a first plurality of pins connected to the first PCS lane, a second plurality of pins connected to the second PCS lane, a third plurality of pins connected to the third PCS lane, and a fourth plurality of pins connected to the fourth PCS lane, wherein the PCS block is configured to map the first SERDES lane to the first plurality of pins, the second SERDES lane to the second plurality of pins, the third SERDES lane to the third plurality of pins, and the fourth SERDES lane to the fourth plurality of pins based on
    Type: Application
    Filed: August 21, 2008
    Publication date: February 25, 2010
    Applicant: CSWITCH CORPORATION
    Inventors: Nadeem Fahmi, Jason Alexander Jones
  • Patent number: 7663515
    Abstract: A high-speed serial interface circuit includes a data receiver circuit, a clock signal receiver circuit, a logic circuit block that includes at least a serial/parallel conversion circuit, a free-running clock signal generation circuit, a clock signal detection circuit, and an output mask circuit. The clock signal detection circuit compares a received clock signal from the clock signal receiver circuit with a free-running clock signal from the free-running clock signal generation circuit to detect whether or not clock signals are transferred through differential clock signal lines. When the clock signal detection circuit has detected that the clock signals are not transferred through the differential clock signal lines, the output mask circuit masks an output signal from the logic circuit block so that the output signal is not transmitted to a circuit in the subsequent stage.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: February 16, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Takemi Yonezawa, Kenichi Oe
  • Patent number: 7659838
    Abstract: Deserializer circuitry for high-speed serial data receiver circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting serial data to parallel data having any of several data widths. The circuitry can also operate at any frequency in a wide range of frequencies. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: February 9, 2010
    Assignee: Altera Corporation
    Inventors: Toan Thanh Nguyen, Thungoc Tran, Sergey Yuryevich Shumarayev, Arch Zaliznyak, Tim Tri Hoang, Ramanand Venkata, Chong Lee
  • Patent number: 7656324
    Abstract: An interface control circuit including a physical layer receiver, a lane receiver, a bridge circuit, a transmitter command encoder, a lane transmitter and a physical layer transmitter is provided. The physical layer receiver receives and converts serial data into parallel data, and determines to transmit the parallel data in a high speed transmission mode or a low power transmission mode according to the serial data. The lane receiver receives and decodes the parallel data. The bridge circuit outputs the decoded parallel data. If the serial data includes a read command, the transmitter command encoder encodes the parallel data. The lane transmitter receives target parallel data from the bridge circuit, and transmits the target parallel data in the low power transmission mode according to the encoded parallel data. The physical layer transmitter converts the target parallel data into target serial data and outputs the target serial data.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: February 2, 2010
    Assignee: Novatek Microelectronics Corp.
    Inventor: Ching-Hsiung Lin
  • Patent number: 7657676
    Abstract: Some interface signals are selected from among signals of a plurality of different parallel interfaces, then being multiplexed onto a serial connection. A transmitter of a signal transmission system includes an interface-signal selector IFS, and a transfer programmer TP for issuing a control signal to instruct the selection from among the parallel interfaces. The transfer programmer TP implements the multiplexing of the selected interface signals in such a manner that the specification of the parallel interfaces is satisfied. Also, the transfer programmer TP changes, as occasion requires, the control signal to instruct which interfaces to select. This change allows the interface signals to be multiplexed onto the serial connection while dynamically changing the interface signals to be multiplexed.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: February 2, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Kato, Yasuhiko Sasaki
  • Patent number: 7656325
    Abstract: A serializer-deserializer and a method of deserializing data. In one embodiment, the serializer-deserializer includes: (1) an analog-to-digital converter configured to receive a serial data stream and provide a digital output based thereon, (2) a digital comparator coupled to the analog-to-digital converter and configured to compare the digital output to an output table to yield candidate output bits, (3) a digital feedback equalizer coupled to the digital comparator and configured to generate the output table based on the candidate output bits and (4) a multiplexer coupled to the digital comparator and configured to select output bits from among the candidate output bits to form a discrete bit sequence.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: February 2, 2010
    Assignee: LSI Corporation
    Inventor: Alexander E. Andreev
  • Patent number: 7656323
    Abstract: An all-digital serializer-de-serializer includes an all-digital clock multiplier unit (CMU) circuit, an all-digital clock and data recovery (CDR) circuit, a multiplexer (MUX), and a demultiplexer (DeMUX). The all-digital clock and data recovery (CDR) circuit couples to the all-digital clock multiplier unit (CMU) circuit. The multiplexer (MUX), couples to all-digital clock multiplier unit (CMU) circuit, and serializes data. The demultiplexer (DeMUX), couples to the all-digital clock and data recovery (CDR) circuit, and de-serializes data.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: February 2, 2010
    Assignee: Altera Corporation
    Inventors: William W. Bereza, Tad Kwasniewski, Rakesh H. Patel
  • Patent number: 7652598
    Abstract: A method for improving performance and flexibility of serial data analysis in test instruments, is independent of data bit rate, encoding scheme or communication protocol embodied in the serial data. The serial data is input to a transmitter section, where it is demultiplexed into a plurality of multi-bit lanes, such as n bits for each of N lanes. The N lanes are then encoded into characters, the encoded N lanes having m bits per lane where m>n. Bit stuffing is used to adjust the data rate and/or to insert qualifiers. The stuffed, encoded N lanes are then multiplexed into N serial lanes, which are output from the transmitter section for input to a receiver section at a data rate that is optimal for the receiver section. In the receiver section the N lanes are deserialized, decoded and input to a word recognizer to generate a trigger event signal.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: January 26, 2010
    Assignee: Tektronix, Inc.
    Inventors: Shane A. Hazzard, Que Thuy Tran, Kayla R. Klingman, David L. Kelly, Patrick A. Smith, Daniel G. Knierim
  • Patent number: 7646320
    Abstract: A first data path is coupled between a data input and a data output of a circuit. A second data path is coupled between the data input and the data output. The first data path includes a parallelization circuit coupled to the data input to receive a serial data signal and configured to generate a parallelized data signal from the serial data signal, a first sampling circuit coupled to the parallelization circuit and configured to sample the parallelized data signal, and a serialization circuit coupled to the first sampling circuit and configured to serialize the sampled parallelized data signal. The second data path includes a second sampling circuit coupled to the data input and configured to sample the serial data signal. A selection circuit is configured to select between the first data path and the second data path.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: January 12, 2010
    Assignee: Qimonda AG
    Inventors: Johannes Reichart, Peter Gregorius, Manfred Berroth, Markus Groezing
  • Patent number: 7626523
    Abstract: A deserializer and method for deserializing data are disclosed. The method includes converting data from a serial data domain to a parallel data domain, detecting a comma related to the parallel data while the data is in the serial data domain, wherein conversion of the data from the serial data domain to the parallel data domain is made in relation to detection of the comma.
    Type: Grant
    Filed: January 10, 2008
    Date of Patent: December 1, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Bo Shin, Hitoshi Okamura, Sang-Jun Hwang
  • Patent number: 7619547
    Abstract: A serial-to-parallel converter circuit comprising: an m-bit serial data holding unit to be input with serial data whose input bit number is set to m or n (<m) bits within a transfer period and a serial clock synchronized therewith, and to shift and hold the serial data by one bit based on the serial clock; an input mode identifying unit to identify whether the input bit number is m or n bits, based on a count value obtained by counting the number of generation of the serial clock during the transfer period; and a parallel data generating unit to output the held m-bit data as first parallel data when the input bit number is identified as m bits, and to output m-bit data obtained by adding predetermined (m?n)-bit data to the held n-bit data as second parallel data when the input bit number is identified as n bits.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: November 17, 2009
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Yoshiyuki Yamagata, Tetsuya Tokunaga, Yasuo Osawa, Kensuke Goto
  • Publication number: 20090261997
    Abstract: A multi-speed burst mode serializer/de-serializer (SerDes) is configurable and can operate in one of a plurality of operating modes. The plurality of operating modes correspond to the reception of signals from optical network units that operate at different nominal speeds. These various modes of operation can enable a single SerDes design to apply to a variety of speeds and network configurations (e.g., point-to-point or point-to-multipoint). In one example, the design can be initially configured for operation with a single ONT or a network of ONTs at a single speed, or can be dynamically configured during operation for use with a network of ONTs operating at different speeds.
    Type: Application
    Filed: June 22, 2009
    Publication date: October 22, 2009
    Applicant: Broadcom Corporation
    Inventor: Wael William Diab
  • Patent number: 7605726
    Abstract: A circuit for data alignment includes a first latch unit and a second latch unit. The first latch unit latches serial input data by using a plurality of first clocks with different phases and the same frequency to output latched data. The second latch unit latches the data from the first latch unit by using a plurality of second clocks with a lower frequency than the first clocks and more diverse phases to thereby output parallel data.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: October 20, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang-Yeon Byeon