Abstract: A receiving device oversamples incoming serial data using multiple phases of its system clock. The device detects an initial edge in the set of samples and selects a sample based on the location of the initial edge. A first bit is set to the value of the selected sample. A portion of the set of samples following the initial edge. If an edge is detected, then a sample is selected based upon the location of the detected edge and the next bit is set to the value of the selected sample. If an edge is not detected within this portion, then the position of the next edge is estimated. A sample is selected based upon the location of the estimated edge and the next bit is set to the value of the selected sample. The analysis is repeated for another portion of the set of samples following the newest edge.

Abstract: A system for presenting serial drive signals for effecting communication of parallel data signals includes: a controller; a serializer coupled with the controller; and a tri-state logic device coupled with the serializer. The controller provides parallel logic state signals to the serializer. The serializer treats the parallel data signals to present a serial data signal representing the parallel data signals at a first output locus, and treats the parallel logic state signals to present a serial logic state signal representing the parallel logic state signals at a second output locus. The tri-state logic device receives the serial data signal and the serial logic state signal for logical evaluation. The tri-state logic device presents the serial drive signals at a third output locus. Each respective drive signal has a respective drive state. Each respective drive state is determined by the logical evaluation.

Abstract: A triggered data generator reduces timing jitter at the start of serial data output from arrival of a trigger signal. A trigger detecting circuit 8 produces trigger phase information indicating the phase relationship between the trigger signal and a reference clock. A data pattern generating circuit 10 generates parallel data bits according to the reference clock in response to the trigger signal. A data shifting circuit 11 rearranges the parallel data bits in a predetermined order to produce shifted parallel data bits in which data bit order is shifted relative to the reference clock as a function of the trigger phase information. A parallel to serial converter 16 converts the shifted parallel data bits into serial data bits.

Abstract: An appliance includes a physical interface for communication according to a broad protocol and two functional components. The first functional component communicates via the physical interface. The second functional component includes a functional module adapted to communicate according to a narrow protocol and an emulation module that transforms between the two protocols so that the two functional components can communicate with each other using the physical interface.

Abstract: A physical layer device includes a deserializer that deserializes one of first and second data streams. The first data stream includes successive N-bit sequences having one of all ones and all zeros. A converter oversamples the first data stream, identifies edge transitions in the first data stream to locate N adjacent bits that substantially align with the N-bit sequences, and samples at least one bit of the N adjacent bits.

Abstract: Systems and methods are provided for providing a filtered, thermometer coded output signal from an N bit digital input, where N is an integer greater than one. A truncated lookup table provides a corresponding truncated thermometer code in response an address related to the N bit digital input. A code recovery assembly transforms the truncated thermometer code into a thermometer coded output according to a recovery bit associated with the N bit digital input.

Abstract: A serializer including a pull-up unit configured to pull up an output node, and a plurality of data select units configured to receive a plurality of input data signals. Each data select unit includes a pull-up device configured to pull up the output node in response to a corresponding input data signal, and a pull-down device configured to pull down the output node in response to the corresponding input data signal.

Abstract: The present invention provides a memory device including a serial-parallel conversion section that converts serial data into parallel data, a parallel-serial conversion section that converts parallel data into serial data, and a parallel-parallel conversion section that changes a bit width of the parallel data. This memory device connects one external terminal to the serial-parallel conversion section and another external terminal to the parallel-serial conversion section when access using a serial interface is performed. On the other hand, the memory device connects a plurality of external terminals to the parallel-parallel conversion section when access using a parallel interface is performed, thereby enabling the memory device to occasionally realize parallel transfer of data while using a conventional package.

Abstract: A data form converter allowing parallel-to-serial or serial-to-parallel conversion at various conversion ratios is disclosed. A frequency divider divides an input clock in frequency at a variable frequency division ratio to produce a single frequency-divided clock. A data shift circuit shifts serial input data according to the input clock to output n-bit parallel data, where n is determined depending on the variable frequency division ratio. A retiring section synchronizes the n-bit parallel data with the single frequency-divided clock to output parallel output data.

Abstract: Queuing and ordering data is described. Data is stored or queued in concatenated memories where each of the memories has a respective set of data out ports. An aligner having multiplexers arranged in a lane sequence are coupled to each set of the data out ports. A virtual-to-physical address translator is configured to translate a virtual address to provide physical addresses and select signals, where the physical addresses are locations of at least a portion of data words of a cell stored in the concatenated memories in successive order. The multiplexers are coupled to receive the select signals as control select signaling to align the at least one data word obtained from each of the concatenated memories for lane aligned output from the aligner.

Abstract: An apparatus for transmitting a position detection signal of a multi-shaft motor whereby a parallel-form detection signal that is output from position-detecting devices disposed on each of a plurality of motors and used for indicating a motor rotation position can be transmitted to motor drivers for controlling the driving of the motors via a group of a small number of wires. In the apparatus for transmitting a position detection signal of a multi-shaft motor, a transmission-side converter converts a parallel-form detection signal from rotary encoders to a serial signal and presents the resulting signal to a reception-side converter via a serial signal transmission path. The reception-side converter returns the received serial-form detection signal to a parallel-form signal and presents the signal to motor drivers.

Abstract: A synchronous parallel/serial converter is disclosed. In one embodiment, the a synchronous parallel/serial converter that receives a parallel n-bit input signal and comprising a first shift register that receives an odd-numbered part of the input signal with a first load signal in synchronism with a clock signal having a clock rate half the clock rate of a system clock, and provides a serial output as a first one-bit signal sequence; a second shift register that receives an even-numbered part of the input signal with a second load signal synchronism with the clock signal and provides a serial output as a second one-bit signal sequence; and a fusion unit that fuses the first serial one-bit signal sequence synchronously with the clock signal and the second serial one-bit signal sequence in synchronism the clock signal to form a serial one-bit output signal.

Abstract: Integrated circuit serializer circuitry is provided that converts parallel data to serial data on an integrated circuit. A two-phase global serializer master clock generator uses a four-phase internal clock to generate a two-phase global serializer master clock. The two-phase global serializer master clock is distributed globally on the integrated circuit using a distribution path. The integrated circuit has multiple serial communications channels each of which has an associated serializer. Each serializer contains circuitry that derives a number of clock signals from the two phases of the global serializer master clock. Each serializer uses the derived clocks in converting parallel data to serial data for transmission over its associated serial communications channel. The serializers each contain two smaller serializers that convert first and second sets of parallel data to first and second serial outputs. A 2:1 serializer in each serializer merges the first and second serial outputs.

Abstract: A programmable multi-cycle signaling scheme provides synchronous communications over relatively large distances. An input digital data stream is de-multiplexed onto multiple conductors. The digital data stream is recreated at the far end of the conductors.

Abstract: A PCI Express device is provided. The PCI Express device includes a symbol lock module that includes a state machine for detecting a special character in a serial bit stream received from a serial/de-serializer, wherein the state machine receives a first special character and verifies alignment of the special character by comparing with a previously stored alignment value and the state machine declares a symbol lock if at least more than one special character alignment matches with a same stored alignment value. The special character is a comma sequence. After a symbol lock is declared, the state machine continues to monitor incoming bit stream data and compares each new special character alignment with the previously stored alignment value. During the monitoring if a misaligned special character is detected, then the state machine waits to receive another special character before declaring a loss of synchronization.

Abstract: A method for transmitting a digital data word, and an apparatus for carrying out the method, include the following processing steps: First, the data word is converted into a first serial differential data sequence which contains the information in at least one initialization bit and in the data bits of the data word in time with a clock signal. The data word is also converted into a second serial differential data sequence which contains the information in at least one initialization bit and in the data bits of an inverted data word, obtained by inverting the data word, in time with the clock signal. Next, the first differential data sequence is transmitted via a first data channel, and the second differential data sequence is transmitted via a second data channel.

Abstract: A high speed serializer-deserializer (SerDes) that passes significantly more data through a channel for a given analog bandwidth and signal-to-noise ratio. This SerDes technique involves converting a plurality of bits to be transferred to positions of edges of a waveform that is transmitted over at least one transmission wire from a source to a destination. The plurality of bits are converted to edges in order to position edges such that more than k inter-edge spacings are possible over a range of spacings between T and kT, where k is a real number greater than 1 and T is the minimum spacing between consecutive edges. An edge position translation scheme that maps patterns in a stream of input bits to a corresponding spacing between a rising edge and a falling edge of the waveform, or between a falling edge and a rising edge of the waveform.

Abstract: The invention relates to a parallel-serial converter for converting parallel data into serial data, in particular for or in a DDR semiconductor memory, having at least n input terminals at which n data signals are present in parallel, an output terminal for outputting a serial data signal, a controllable latch connected to the input terminals on the input side, a common storage node, which is connected to outputs of the latch and which holds a data signal of the controllable latch present last, a controllable bypass device, which has an input, which is coupled to the storage node on the output side and which has a control terminal, via which a predeterminable state present at the input of the bypass device can be switched onto the storage node. The invention furthermore relates to a semiconductor memory having such a parallel-serial converter and to a method for operating such a parallel-serial converter.

Abstract: An Infiniband device can be provided. The device can comprise an input port having a serialiser/deserialiser. The serialiser/deserialiser can comprise: a data buffer for storing data from a received serial data stream and for outputting the stored data in parallel groups and a code detector for detecting a predetermined code pattern in the serial data stream and generating a code detection output in response thereto. The serialiser/deserialiser can also comprise a transition detector for detecting transitions in the serial data stream and reconstructing a serial data clock therefrom, and for generating a plurality of parallel data clocks from the serial data clock, each parallel data clock having a different phase. The data buffer can be responsive to the code detection output to adjust a parallel data group start position within the serial data stream and to cause a selection of one of the reduced frequency clocks having a phase corresponding to the adjusted parallel data group start position.

Abstract: A data communication system comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a set of codewords representing data in the input data stream, and the members of the set are substantially DC balanced, such as a Manchester encoded symbol set. An integrating circuit on the second integrated circuit integrates codewords by integrating for a first interval with a positive polarity within a particular symbol cell, and integrating for a second interval with a negative polarity within the particular symbol cell, to produce output representing the codewords. A sense circuit produces an output data stream.

Abstract: An information-processing apparatus includes a controller for sending a first parallel digital signal having a plurality of bits, a first converter for time-dividing the first parallel digital signal as to convert the first parallel digital signal into a serial signal, a first case for accommodating the controller and the first converter, a second converter for converting the serial signal into a second parallel digital signal having a plurality of bits, a wireless communication device for receiving the second parallel digital signal to producing a high frequency signal based on the second parallel digital signal, an antenna for transmitting the high frequency signal, a second case for accommodating the second converter and the wireless communication device and for having the antenna mounted thereto, a hinge unit coupling the second case rotatably with the first case, and a signal line provided at the hinge unit and transmitting the serial signal between the first converter and the second converter.

Abstract: One or more configurable transceivers can be fabricated on an integrated circuit. The transceivers contain various components having options that can be configured by turning configuration memory cells on or off. The integrated circuit may also contain programmable fabric. Other components in the transceivers can have options that are controlled by the programmable fabric. The integrated circuit may also contain one or more processor cores. The processor core and the transceivers can be connected by a plurality of signal paths that pass through the programmable fabric.

Abstract: In an LVDS system for converting N types (for example N=3) of parallel signals into serial signals and sending/receiving the converted serial signals between a driver and a receiver through M (M?N) signal lines, a sequencer 11 for selecting drivers 10a to 10c to be used in accordance with the number of signal lines used for transmission/reception and a reception-side sequencer for selecting a receiver to be used in accordance with the number of signal lines M used for transmission/reception are included to perform transmission/reception by using the driver and receiver selected by the both sequencers. Thus, it is possible to select the number of channels and a data rate optimum for the impedance of a signal line without fixing the number of signal lines used for transmission/reception.

Abstract: A data input circuit converts input serial data to n-bit parallel data, and outputs the n-bit parallel data by following an address signal. The data input circuit includes a data shifting unit including a plurality of columns, and sequentially shifting the input serial data through the plurality of columns; and a selection unit selecting a column among the plurality of columns as an input column by following the address signal, wherein the input serial data is inputted to the data shifting unit through the input column. Thus, the data input device can speed up its processing speed with a simplified circuit structure whose circuit size is reduced.

Abstract: A method of exchanging data through a serial port includes transmitting data as an output stream of frames defined by edges of a frame clock signal, a first data bit of a current frame transmitted during a time period starting in a preceding frame and extending after an edge of the frame clock signal defining the start of the current frame.

Abstract: A circuit and method for processing digitized analog signals (“input signals”) containing noise as well as maxima and minima of input signal, whereby local peaks and valleys of the input signal are detected and captured in the presence of the noise, and whereby peak detection attributable only to noise is suppressed.

Abstract: A programmable serial data path includes a programmable timing circuit and a parallel to serial module. The programmable timing circuit is operably coupled to generate a first plurality of timing signals when width of parallel input data is of a first multiple and to generate a second plurality of timing signals when the width of the parallel input data is of a second multiple. The parallel to serial module is operably coupled to convert the parallel input data into serial output data based on the first or second plurality of timing signals.

Abstract: A hybrid serial/parallel bus interface method and apparatus for a base station has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block. The method/apparatus is adaptable for either bidirectional or unidirectional applications.

Abstract: A decision feedback equalization (“DFE”) technique is suitable for use in a serializer-deserializer (“SERDES”) receiver in an integrated circuit (IC). The IC has a summing node coupled to a return-to-zero (“RTZ”) data latch register. The RTZ data latch register has a first (“even”) series of RTZ data latches and a second (“odd”) series of RTZ data latches. A first even tap is coupled to the first even RTZ data latch and provides a feedback signal to the summing node on a first portion of a local clock cycle. A first odd tap is coupled to the first odd RTZ data latch and provides an odd feedback signal to the summing node on a second portion of the local clock cycle.

Abstract: A signal transmission method and a signal transmission device capable of easily transmitting a signal with a small number of signal lines. A data signal of time slot count N+? with bit count N is longitudinal-lateral converted into a data signal of time slot count N with bit count N+?. so as to create a null time ? and a control signal is inserted into the null time ?, thereby converting the parallel signal containing the data signal and the control signal into a serial signal for transmission.

Abstract: A serializer-deserializer instantiated in configurable logic of an integrated circuit is described. The serializer-deserializer includes an input deserializer and an output serializer, which may be commonly coupled via an input/output pad. Each of the serializer and deserializer may be configured for an operating mode selected from a Single Data Rate mode and a Double Data Rate mode. The serializer-deserializer may be used as part of a synchronous interface.

Abstract: A transceiver can be used to send and receive data at a lower data rate than the data rate its SERDES is designed to operate. It contains a transmitter interface that receives a first set of data at a lower data rate and delivers a second set of data to the SERDES at a higher data rate. The transceiver also contains a receiver interface that receives a third set of data from the SERDES at the higher data rate and delivers a fourth set of data at the lower data rate. To reduce the minimum transmission serial data rate, one embodiment of the present invention derives a half-speed clock for the transmitter interface. Using the half-speed clock, the transmitter interface supplies data to be transmitted at half the normal rate with respect to a reference clock. As a result, the data rate is reduced. The opposite operation is used for the receiver interface.

Abstract: In a method of communicating a plurality of parallel data packets from a first data parallel bus to a second parallel data bus, each of the plurality of parallel data packets is separated into a first portion and a second portion. Each first portion is converted into a first serial data stream and each second portion is converted into a second serial data stream. The first serial data stream is transmitted over a first serial data channel and the second serial data stream is transmitted over a second serial data channel. The first serial data stream is converted into a plurality of first received portions and the second serial data stream is converted into a plurality of second received portions. Selected first received portions are combined with corresponding selected second received portions so as to regenerate the plurality of parallel data packets.

Abstract: A serializer for multiplexing 2N data streams, each data stream having a frequency of f/(2N), N being a positive integer. The serializer comprises 2N?1 instances of a dual-edge multiplexer flip-flop circuit, N frequency domains including a first frequency domain having the frequency f/2N and a last frequency domain having a frequency f/2, and an output providing serialized data at frequency f clocked at half that rate. Thus, the highest clock signal frequency input into the serializer is f/2.

Abstract: A serializer and a deserializer are disclosed and shown operating singly or as a pair. The invention operates independently from any outside system reference clock. The inventive system provides an internal bit clock that serializes the data when sending and de-serializes the data when receiving. A bit clock or pulse travels with the data word bits to define when a bit is stable. The system uses word boundary bits operating with a bit clock to distinguish different data words, as described in the parent application. The system operates either synchronously or asynchronously with the base computer or other such digital system, including I/O devices. The invention finds use where new data to be sent is strobed into the serializer, but also where a change in the data bit content itself will cause the changed data to be loaded into the serializer and sent bit by bit. The system operates where new data is strobed or loaded by the serializer (not the base computer system) when the last data word has been sent.

Abstract: A transceiver includes a receiver section and a transmitter section. The receiver section includes a clocking circuit, a serial-to-parallel module, and compensation. The transmitter section includes a clocking circuit, parallel-to-serial module, and compensation. The compensation within the receiver section and transmitter section compensates for integrated circuit (IC) processing limits and/or integrated circuit (IC) fabrication limits within the clocking circuits, serial-to-parallel module, and parallel-to-serial module that would otherwise limit the speed at which the transceiver could transport data.

Abstract: In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the highest, ½ of the frequency of the input digital data are employed for operating the SPC circuit, whereby the SPC circuit is improved in power dissipation, stability and reliability.

Abstract: A data transfer control device and an electronic instrument which can implement a process to be made on data transmitted and received through a high speed bus on a circuit operating at a low frequency. The data transfer control device has a conversion circuit which converts K-bit width data transferred at a frequency FC1 (in USB 2.0 HS mode) through a bus into data having an L-bit width (L>K) by rearranging, and a processing circuit which receives the L-bit width data from the conversion circuit and carries out a K-bit based process on an L-bit basis at a frequency FC2 lower than FC1. This enables to perform the K-bit based process at the low frequency FC2. Configuration on a transmission end can be implemented in the same manner. The transfer data in the USB 2.0 HS mode is processed on the L-bit basis while the transfer data in the FS mode is processed on the K-bit basis. The present invention is applicable also to the process on data transferred through a bus under the IEEE1394 or SCSI.

Abstract: A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.

Abstract: A data register which outputs an input data as is when the input data fulfills a set data width for outputting, and holds the input data until a bit width of the input data is equal to or more than the set data width, in response to a first enable signal. A first selector which selects an n-bit byte lane from a (2n?1)-bit byte lane of the data register in response to a first select signal, and a second selector which selects an n-bit byte lane out of a (2n?1)-bit byte lane and outputs a valid data in response to a second select signal. A data buffer which receives and stores the valid data in response to a second enable signals.

Abstract: A programmable serial data path includes a programmable timing circuit and a parallel to serial module. The programmable timing circuit is operably coupled to generate a first plurality of timing signals when width of parallel input data is of a first multiple and to generate a second plurality of timing signals when the width of the parallel input data is of a second multiple. The parallel to serial module is operably coupled to convert the parallel input data into serial output data based on the first or second plurality of timing signals.

Abstract: A serializer within, for example, a transceiver is provided having multiple stages of pipelined multiplexing cells. Each multiplexing cell may be substantially the same and each comprises no more than one latch. In some embodiments, each multiplexing cell includes a multiplexer comprising a pair of inputs and a single latch, which is coupled to one input of the multiplexer. No latches are coupled to the other input of the multiplexer. The serializer generally includes a plurality of stages. Each successive stage includes one-half the number of multiplexing cells included in the previous stage, and each successive stage is clocked by a clocking signal that transitions at twice the frequency of the previous stage clock signal.

Abstract: A fully digital pulse width modulator substantially doubles resolution in a laser printer by outputting data to the laser on both the rising and falling edges of the clock cycle. A counter and the clock itself are used to select input to a multiplexer, and consequently, the data output to the laser from the multiplexer. A data selector code, generated by concatenating the binary value of the counter and the inverted clock bitwise, selects which of the 16 bits representing a pixel to place onto the data line, so that all 16 bits are output to the laser serially and sequentially in eight clock cycles. By using both the rising and falling edges of a clock cycle, the clock speed of the device is effectively doubled, without increasing actual clock speed. Device resolution is improved simply and inexpensively without major modification of printed circuit boards.

Abstract: Method and apparatus for a bimodal serial to parallel converter is provided. A first stage of registers is clocked responsive to a clock signal, such as a forwarded clock signal of a synchronous interface. The first stage of registers is configurable in either a single serial shift chain or two serial shift chains. The former configuration is for Single Data Rate (“SDR”) data, and the latter configuration is for Double Data Rate (“DDR”) data. A bitslip controller is configured to provide a control select signal to selection circuitry. For DDR operation, the control signal is for selecting respective portions of outputs from the two serial shift chains for providing to a second stage of registers. For DDR operation, the second stage of registers is alternatively clocked responsive to a divided down version of the clock signal and another divided down version of the clock signal which is periodically stopped.

Abstract: A zero stripper (10) accepts individual bit sequences marked off by a break codes in a bit stream, deletes any leading “0” bits from such bit sequences so as to form a zero-stripped datum segment, counts the number of bits in each resultant datum segment, and then concatenates each such datum segment with the bit count of that datum segment into the code form nnnndddddd . . . , where the “n's” are the bit count and the “d's”are the successive bits. Substantial bit space in transmission in thus saved. A “type code” “tt” can also be added if defined in the original data. The zero-stripped data can be reconstituted at the receiving end if needed, i.e., if the receiving device accepts only fixed length bytes. Also included are new and simple arithmetic routines.

Abstract: A system and method are provided for synchronizing a frame of related bits output from a deserializer to the related bits serially fed to the deserializer. Synchronization is achieved by overcoming a slip bit problem by selectively increasing the frame clock cycle during times in which the slip bit occurs. The deserializer is controlled by a clock generator that can include a counter which generates the frame clock. The counter can be asynchronously or synchronously reset, without any glitches occurring within the deserializer and, thus, avoiding any invalid bits output from the deserializer. The asynchronous reset forces the counter to a deterministic state, and the synchronous reset sets the counter to a valid state. In each instance, however, resets do not impart glitches to the deserializer and the deserializer output frame is maintained synchronous to related bits serially fed to the deserializer.

Abstract: A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.

Abstract: Input and output sections of an analog-to-digital converter are joined by an interface. In the input section, an analog input signal is converted to a multi-bit digital signal before being converted, by a noise-shaping converter such as a sigma-delta modulator, to a lower bit signal. The lower bit signal is carried across the interface before being converted, by a digital filter to recover the original multi-bit signal. The same principle is applied to the input and output sections of a digital-to-analog converter.

Abstract: When a data processing circuit is formed on an insulating substrate by using TFTs, it is difficult to process a data signal having a high data rate, such as digital display data, at a high speed. In a data processing circuit formed on an insulating substrate by using TFTs, a data signal having a small voltage amplitude input in series is increased in level to a data signal having a large voltage amplitude by a level shift circuit (11), the serial data signal having the large voltage amplitude is converted to parallel data signals by a serial-parallel conversion circuit (12), and then, the parallel data signals are reduced in level to data signals having a small voltage amplitude by level shift circuits (13A and 13B). Therefore, high-speed processing can be applied to digital data signals at a low power consumption.

Abstract: A nonvolatile memory with a memory array arranged in rows and columns of memory cells in NOR configuration, the memory cells arranged on a same column being connected to one of a plurality of bit lines and a column decoder. The column decoder comprises a plurality of selection stages, each of which is connected to respective bit lines and receives first bit line addressing signals. The selection stages comprise word programming selectors controlled by the first bit line addressing signals and supplying a programming voltage to only one of the bit lines of each selection stage. Each selection stage moreover comprises a string programming selection circuit controlled by second bit line addressing signals thereby simultaneously supplying the programming voltage to a plurality of the bit lines of each selection stage.