Abstract: A digital-to-analog converter for use in a timing control loop. The converter includes a plurality of cells, each activated in response to a timing loop control signal. The converter also includes a resistive current mirror, with a first resistance R1, providing a reference curent which is mirrored in each cell by a current source FET. Each cell is constructed to switch the current from its current source FET through an output FET when a respective control bit provided to the cell is positive. Otherwise, the current is diverted through a sink FET. All of the cell output FETs are tied to a single resistance R2 which collects the currents of the active cells and provides the AC output of the converter. The converter's output is related only to the ratio R2/R1, thereby decoupling process, temperature, and voltage effects from the output of the converter.

Abstract: An analog-to-digital converter includes a constant current source that alternately charges and discharges the capacitor between predetermined levels. The difference between the rate of charging and the rate of discharging of the capacitor provide information permitting a digital representation of the input signal. The single current source operates without change during the charging and discharging of the capacitor and has temperature compensation that eliminates potential errors due to instabilities in the ambient temperature.

Abstract: An analog to digital interface circuit includes two matched, symmetrical, differential amplifiers which in response to an analog signal having a rising edge and a falling edge produce first and second output signals which are identical but 180.degree. out of phase; whereby the rising edge of the analog signal corresponds to the rising edge of the first output signal, the falling edge of the analog signal corresponds to the rising edge of the second output signal and the time interval between the rising edges of the two output signals is equal to the time interval between the rising and falling edges of the analog signal. The outputs of the differential amplifiers are further processed by two matched, symmetrical buffers which produce first and second digital signals having like falling edges corresponding to the rising and falling edges of the analog signal, respectively.

Abstract: A compensation system for a position encoder which automatically compensates for scale and other similar errors along the entire path of relative motion. The phase of the encoder signals is altered by a small amount for each small increment of relative motion to provide encoder signals compensated for the scale error. The phase correction is added to or substracted from the phase of the encoder signals depending upon the sense of relative motion.

Abstract: A current-source ladder digital-to-analog converter is compensated for temperature changes by making the total current running through the converter proportional to absolute temperature and by terminating the parallel transistor chain forming the current source ladder with a transistor whose emitter voltage is greater than the emitter voltage of the least significant bit current source transistor by 2(KT/q)ln 2 volts. The aformentioned voltage difference is achieved by making the emitter area of the termination transistor at least eight times the emitter area of the least significant bit transistor.

Abstract: A fast-in, slow-out sampling system that operates at a very high sampling frequency at high accuracy. The system includes a parallel processing sampling structure controlled by a precision pulse generation system.

Abstract: A CMOS digital-to-analog converter includes a modified R-2R resistive ladder network connected to 16 pairs of bit switches responsive to the various digital inputs to produce an internal analog voltage representative of the digital input. Each pair of bit switches includes an N-channel MOSFET and a P-channel MOSFET. The on resistance of the P-channel MOSFET is adjusted to precisely match that of the N-channel MOSFET by driving the gate of each P-channel MOSFET with the output of a CMOS inverter referenced between V.sub.CC and a reference voltage that is adjusted to cause the on resistances of a P-channel "monitor" MOSFET and an N-channel "monitor" MOSFET to be equal. A reference voltage is generated by a circuit that generates a temperature-invariant source current from a V.sub.BE difference between first and second transistors, causes part of it to flow through first, second, and third resistors, the third resistor having a voltage across it established by the V.sub.