Abstract: An audio codec and a BIST method adapted for the audio codec are provided. The BIST method includes the following steps. A first channel digital-to-analog converter (DAC) of the audio codec converts a test signal into an analog signal. A first channel analog-to-digital converter (ADC) of the audio codec converts the analog signal into a digital signal. Use a second channel DAC of the audio codec and a second channel ADC of the audio codec to calculate the magnitudes of a plurality of spectral components of the DFT of the digital signal. Determine whether the audio codec passes the test according to the magnitudes of the spectral components.

Abstract: An apparatus for adjusting a first signal with respect to a second signal includes: (a) A first converter receiving the first signal and employing n first converting elements for digitally converting the first signal to at least one first signal element. (b) A second converter coupled with an output, receiving the second signal and employing n second converting elements for digitally converting the second signal to a second representative signal presented at the output. (c) An adjusting element coupled with each of selected of the first converting elements. Each adjusting element is coupled with the output and cooperates with the connected selected element to present a corrected signal element to the output. The output presents an aggregate output signal including contributions from the second representative signal and each corrected signal element. Adjusting is effected by altering at least one corrected first signal element presented to the output.

Abstract: A precision digital to analog conversion circuit and method are provided. A regulated direct current (DC) voltage having a DC voltage magnitude is supplied to a device, such as a processor. The processor generates a pulse width modulation (PWM) output signal based, at least in part, on the regulated DC voltage. An analog output signal is generated from the PWM output signal. The regulated DC voltage is compared to a precision reference DC voltage, the DC voltage magnitude is selectively adjusted based on the comparison.

Abstract: A single-pass method of trimming a network, and a network manufactured according to the method, uses the assumption that the peak INL value is minimized by trimming all the structures in the network to a same target value based upon the boundary conditions of the discretely adjustable elements that make up the structures. Using this assumption, the number of targets that need to be simulated, can be greatly reduced making estimation of peak INL possible in a reasonable amount of testing or manufacturing time. The trim algorithm produces results that are optimum or substantially close to optimum and is guaranteed not to deteriorate the Peak INL compared to the untrimmed Peak INL. An auto-calibration system using the trim method is also provided so that the method can be used in a product in real time if desired.

Abstract: A sigma-delta converter suitable for measuring a photocurrent comprises an input node adapted to receive a current to be measured (Imeas), a capacitor connected to the input node, a clocked comparator coupled to the input node and to a reference voltage Vref at respective inputs, and a switchable current source connected to the input node which conducts a reference current Iref when switched on. The converter is arranged in a sigma-delta configuration, with the current source switched on to pull down the voltage (VCMP) at the input node when the comparator output toggles due to VCMP increasing above Vref, and to be switched off when the comparator output toggles due to VCMP falling below Vref, such that the comparator output comprises a digital bitstream which varies with Imeas.

Abstract: A calibration circuit and method suitable for black level calibration in image processing, the circuit comprising an analogue gain amplifier, an analogue to digital converter; a correction circuit for receiving a digital signal and providing a digital offset signal; and a digital to analogue converter for receiving said digital offset signal and feeding a corresponding analogue offset signal back to the input of said gain amplifier. The calibration circuit is arranged such that the correction circuit and said digital to analogue converter form a feedback loop applying an offset to said input signal and said correction circuit includes an inverse gain circuit for applying an inverse gain to a signal within said correction circuit prior to said digital to analogue converter. Preferably the inverse gain applied is such that the total loop gain does not deviate too far from unity.

Abstract: A switch signal generator circuit that may form part of a digital to analog converter is provided. The switch signal generator circuit may include a first switch that controls a high reference gate voltage. The high reference gate voltage may provide the ON state voltage for a plurality of switches that control the coupling of a high reference voltage to the digital to analog converter. The switch signal generator circuit may include a second switch that controls a low reference gate voltage. The low reference gate voltage may provide the ON state voltage for a plurality of switches that control the coupling of a low reference voltage to the digital to analog converter. The switch signal generator circuit may also include a resistor. In one embodiment of the invention, a current conducted by the first switch and/or a current conducted by the second switch may each be proportional to a current conducted by the resistor. One of the switches in the switch generator circuit may be a P channel switch.

Abstract: A circuit and a method for calibrating the direct-current offset in the signal output from a signal processing unit are provided. The calibration circuit includes a 1-bit quantizer, a control logic unit and a digital-to-analog converter. The 1-bit quantizer is coupled to the output end of the signal processing unit for receiving and detecting a direct-current offset component in the output signal so as to obtain quantization information. The control logic unit is coupled to the 1-bit quantizer for sequentially setting one of a plurality of bits of a compensation value and updating the set bit according to the quantization information. The digital-to-analog converter is coupled to the control logic unit for compensating the direct-current offset component in the signal output from the signal processing unit according to the compensation value.

Abstract: To avoid the measurement disturbances occurring in a conventional, multi-channel measurement data acquisition apparatus there is proposed a multi-channel measurement data acquisition apparatus which includes at least one analog input assembly having a plurality of analog inputs, a controllable electronic analog signal switch device (12) and a central controllable analog-digital converter, wherein the channels of the analog inputs can be successively switched through by means of the analog signal switch device so that the analog signals at the inputs of the individual channels are successively applied as input signals to the central analog-digital converter, and wherein the electronic analog signal switch device and/or the analog-digital converter have control inputs connected to associated control lines.

Abstract: An optical receiving device of the present invention receives optical signals from an optical transmitting device which uses a modulation format wherein an optical intensity waveform of each symbol is return-to-zero (RZ) pulse, and converts the received optical signals into digital signals by a conversion process of an analog to digital (AD) converter. A control-value calculating unit subsequent to the AD converter digitally processes the digital signals, retrieves an absolute value of the digital signals or a value corresponding one-to-one with the absolute value of the digital signals, estimates errors from an appropriate timing of a sampling timing in the AD converter based on the absolute value of the digital signals or the value corresponding one-to-one with the absolute value of the digital signals, and calculates a control value controlling the sampling timing based on the estimated errors.

Abstract: A method is provided to produce an error corrected digital output from a temperature measurement system that generates digital outputs representative of the output of one or more temperature sensors. In an embodiment of the invention the method comprises: storing in a plurality of memory locations corresponding error correction data, with each memory location having a correlation to a corresponding range of the digital outputs; utilizing each digital output to identify a corresponding one of the memory locations; accessing the corresponding one memory location to obtain error correction data specific to the digital output; and utilizing the error correction data specific to the digital output to correct the digital output, whereby an error corrected digital output is generated.

Abstract: A device for the safe threshold-detection of state information from an analog signal including a decision component and at least two acquisition diversity channels including in series a safe adaptation circuit, an electronic analog-to-digital conversion circuit, and a unit for comparing the digital output signal of the analog-to-digital conversion circuit with a reference signal is provided. The device comprises a fault detection circuit for the mutual comparison of digital output signals from the conversion circuits and supplies a consistency result. The output of the decision component is a function of the consistency result supplied by the fault detection unit and of the comparison results from the comparison units associated with the respective acquisition channels.

Abstract: Apparatuses, methods, and systems for compensating baseline offset in a read channel of an analog storage device. The apparatus generally includes an AC-coupling circuit configured to transfer an analog signal from an analog storage device to the read channel, a configurable current device coupled to the AC-coupling circuit, comparator coupled to the AC-coupling circuit, and logic coupled to the configurable current device and the comparator, wherein the logic is adapted to configure said current device in response to an output of at least one of the AC-coupling circuit and the comparator.

Abstract: A D/A converter has a reference comparison current generator configured to generate a reference comparison current, a first reference current generator configured to generate a first reference current capable of correcting a current level, a first D/A converting part capable of outputting a first full-scale current having a predetermined proportional relationship with the first reference current and capable of generating a first D/A converting voltage in accordance with first input digital data, and a current comparator configured to generate a difference current between the first full-scale current and the reference comparison current to determine a magnitude of the difference current. The first reference current generator corrects the first reference current based on a result determined by the current comparator.

Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.

Abstract: An Inverter system includes a comparator unit compares an analog input voltage with at least one voltage threshold to judge a voltage range for the input voltage. A DC-offset unit determines a DC-offset value to limit the input voltage within a predetermined bound. The input voltage is level-shifted and amplified by a non-inverting adder unit according to the DC-offset value and a fixed gain, and then processed by an analog to digital converter (ADC) to obtain a digital count value. A microcontroller unit calculates an original value for the input analog voltage according to the voltage range and the digital count value. When the analog input voltage could be negative value, a full-wave rectifier unit and a polarity judgment unit are used to find an absolute value and a polarity of the analog input voltage for further processing.

Abstract: The sensor has only a first contact (1) and a second contact (2). In the first step of the method, current is passed through the sensor element (3) while simultaneously measuring the measured variable using a closed switch (4). In a second step, the measured value is then converted into a digital signal in an analogue/digital converter (5) and the digital signal is transformed into a digital output value in a digital switching mechanism (6) which is connected downstream of the analogue/digital converter (5). In a third step, the digital output value is serially sent via the first contact (1) and the second contact (2) with the switch (4) open or closed depending on the binary structure of the digital output value.

Abstract: A technique for reducing errors in a PTIC (parallel, time-interleaved analog-to-digital converter) consisting of M ADCs involves sampling an input signal with the PTIC and performing M different DFTs, one for each ADC. Elements of the M DFTs are grouped together according to frequency and multiplied by correction matrices to yield a corrected, reconstructed power spectrum for the PTIC. The technique is especially effective at removing gain and phase errors introduced by individual ADCs of the PTIC, including gain and phase errors that vary with frequency.

Abstract: A method for determining a gain compensation value for multiple ADCs sums an absolute value of a number of ADC output samples from each of the ADCs that may be collected while the ADCs are in normal operation. In one embodiment, the ratio of the sums of the absolute values of ADC output samples may reflect the difference in gains between the ADCs, and may be used to determine the ADC gain compensation value. A method for determining an offset compensation value between for multiple ADCs averages of a number of ADC output samples from each ADC collected while the ADCs are in normal operation. In one embodiment, a difference between the ADC sample averages may reflect the difference in magnitudes of the ADC offsets for each ADC, and may be used to determine the ADC offset compensation value.

Abstract: An over-sampling analog-to-digital converter (ADC) uses a chopper stabilized voltage reference with improved reference voltage offset cancellation and reduced source induced 1/f noise. The chopper stabilized voltage reference receives chopper clocks that have been correlated with the serial bitstream produced by the sigma-delta modulator of the ADC. The chopper clocks are generated so that the reference voltage produces for each distinct bitstream level an independent sequence of voltages that comprise alternatively positive and negative voltage reference offset contributions. After integration (averaging) is performed within the sigma-delta modulator, these equal and opposite reference offset contributions cancel out regardless of the bit pattern comprising the bitstream.

Abstract: A technique for reducing errors in a PTIC (parallel, time-interleaved analog-to-digital converter) consisting of M ADCs involves sampling an input signal with the PTIC and performing M different DFTs, one for each ADC. Elements of the M DFTs are grouped together according to bin number. If all elements corresponding to the same bin number exceed a predetermined threshold, the elements are multiplied by correction matrices to yield corrected, DFT terms for a reconstructed power spectrum. If they do not exceed the threshold, DFT elements are processed to produce uncorrected DFT terms for the reconstructed power spectrum.

Abstract: A network for generating a set of intermediate voltages comprising two input ports for feeding two reference voltages. The intermediate voltages are generated by a number of self calibration units that correspond to the number of intermediate voltages to be generated. Each self calibration unit receives the voltages of the neighboring calibration units or the voltage of one neighboring calibration unit and one of the reference voltages.

Abstract: A comparator compares an input voltage and a reference voltage and generates an output based on the comparison. The comparator may receive the input voltage in a normal mode of operation. Voltage band circuitry provides first and second test voltages to the comparator. The test voltages define a band around the reference voltage. An integrator adjusts an offset correction signal provided to the comparator based on outputs of the comparator that are generated using the test voltages. The output of the comparator that is generated using the first test voltage could be generated during a first auto-zeroing cycle. The output of the comparator that is generated using the second test voltage could be generated during a second auto-zeroing cycle. This technique helps to maintain the offset of the comparator with the band around the reference voltage.

Abstract: The semiconductor device includes: an A/D conversion circuit for A/D-converting an analog input signal and outputting a resultant conversion result; and a computation circuit for performing, in synchronization with the A/D conversion circuit, computation for an updated conversion result without storing the updated conversion result every time the conversion result from the A/D conversion circuit is updated, to determine one computation result from a plurality of conversion results from the A/D conversion circuit and output the computation result.

Abstract: A technique for removing vertical stripe artifacts generated in a Liquid Crystal Display (LCD) panel, more particularly a technique for compensating for and removing an inter-channel offset voltage of a column driver, which causes the vertical stripe artifacts, is disclosed. An offset voltage generated in each channel for driving each pixel of the LCD panel is detected for a whole signal path and offset voltages detected for all channels are compared and extracted according to a given timing sequence by a common signal comparator, thereby preventing the offset of the detection comparator and reducing a chip size of the column driver in contrary to the prior art. Moreover, an inter-channel offset voltage is detected in a digital circuit mode, thereby compensating for process variations in a semiconductor chip manufacturing process in circuit terms.

Abstract: In a precisely self-calibrating high-speed analog to digital converter the aspect ratios of tri-state inverters are adjusted to fine-tune threshold voltage as comparators. And the multiplexers composed of tri-state inverters amplify the signal from the output of comparators. Their switches of tri-state inverters may be properly controlled to select the optimal channels and reduce unnecessary power consumption. The calibration circuitry utilizes under-sampling to calculate the duty cycles of comparators, selecting the optimal comparators and channels. By the way, the invention may avoid process variation.

Abstract: A system and method are disclosed for monitoring environmental conditions of a perishable product. The system includes an environmental sensor configured to sense one or more environmental conditions of the perishable product and an analog integrator in communication with the environmental sensor, the analog integrator being formed on a polymer substrate and including one or more tunable components. The system also includes a comparator in communication with the analog integrator and configured to change state when an output of the analog integrator reaches a selected threshold level, and a control module in communication with the comparator and the analog integrator. The control module is configured to control the operation of the analog integrator based on an output of the comparator.

Abstract: A sampling rate converter able to obtain an amplitude characteristic that passes any frequency and able to achieve a high precision conversion without depending upon a cutoff frequency, having an up sampler 103 for inserting (U-1) zero points between signals and raising a sampling frequency Fsi U-fold, a convolution processing unit 104 including an FIR filter and interpolating a value by convolution with respect to output signals of the up sampler, and a linear interpolation block 105 for selecting two points of samples from the output signal of the convolution processing unit 104 having a sampling frequency UFsi and finding the value at a required position from the linear interpolation, wherein the FIR filter has an impulse response becoming a filter coefficient, having a transmission function H(z) associated with a transmission function Z(z) of a pre-filter, and having a filter coefficient set by performing weighted approximation with respect to a desired characteristic associated with the frequency respons

Abstract: A system for correcting a DC offset includes a digital-to-analog (D/A) converter module (30), a summing circuit (40), an inphase-to-quadrature (I/Q) modulator (50), a spectrum analyzer module (60) and a DC offset correction module (70). The D/A converter module converts digital control signals to analog control signals, and outputs DC offset regulating signals. The summing circuit respectively sums up the DC offset regulating signals and corresponding vectors of a base band signal. The I/Q modulator receives the summed base band signal, and converts the summed base band signal to a radio frequency (RF) signal. The spectrum analyzer module analyzes an energy variation according to a DC offset contained in the RF signal. The DC offset correction module outputs the digital control signals to adjust the DC offset regulating signals, thereby obtaining the lowest energy variation.

Abstract: A distortion compensator updating and selecting a distortion compensation coefficient applied to a digital transmission signal so as to reduce the difference between the digital transmission signal and a digital feedback signal is disclosed. The distortion compensator includes a control part that controls the level of an input signal to an analog-to-digital conversion part outputting the digital feedback signal in accordance with the magnitude of the amplitude of the digital transmission signal.

Abstract: An object of the present invention is to provide a receiver, a digital-analog converter and a tuning circuit in which temperature compensating components can be formed on a semiconductor substrate while reducing component costs. An FM receiver 100 is constituted by including an antenna 1, a high frequency receiving circuit 2, a local oscillator 3, two digital-analog converters (DACs) 4, 6, a control section 8, a mixing circuit 9, an intermediate frequency amplification circuit 10, a detection circuit 11, a low frequency amplification circuit 12 and the speaker 13. The DACs 4, 6 have a predetermined temperature coefficient, of which output voltage is changed in accordance with ambient temperature. When a characteristic of VCO 31 is changed with variations of ambient temperature so as to cause a control voltage applied to the VCO 31 to be changed, output voltages of the DACs 4, 6 are also changed similarly.

Abstract: A method of converting an input analog signal to a compensated digital signal comprises converting the input analog signal to an uncompensated digital signal, inputting the uncompensated digital signal to a distortion model, generating a modeled distortion signal based on the uncompensated digital signal, and subtracting the modeled distortion signal from the uncompensated digital signal to generate the compensated digital signal. A distortion compensating analog to digital converter (ADC) comprises an uncompensated ADC configured to convert an input analog signal to an uncompensated digital signal, and a compensation module coupled to the uncompensated ADC, configured to receive the uncompensated digital signal, generate a modeled distortion signal based on the uncompensated digital signal and subtract the modeled distortion signal from the uncompensated digital signal to generate the compensated digital signal.

Abstract: An integrated circuit (IC) adapted to (i) measure a voltage differential between a ground potential external to the IC and a ground potential internal to the IC and (ii) based on the measurement result(s), adjust a signal referenced to the internal ground potential to reduce signal error associated with the voltage differential. In one embodiment, the IC is adapted to monitor the voltage differential in real time and use the presently measured voltage differential to perform signal adjustment. In another embodiment, the IC has a plurality of registers, each register adapted to store a voltage-differential value corresponding to a particular configuration of the IC, which values are written into the registers during an initialization procedure. During normal operation, the IC controllably selects from the stored values one corresponding to the current IC configuration.

Abstract: A Root Mean Square (RMS) detector circuit includes a first differential pair circuit arranged to operate in a common mode. The detector circuit also includes a compensation circuit unit having a second differential pair circuit to duplicate an unwanted base current drawn by the first differential pair circuit. The compensation circuit unit is arranged to generate an offset voltage using the duplicated base current. The compensation circuit unit also has an operational amplifier coupled to an NMOS transistor so as to generate a corrective current corresponding to the offset voltage, the corrective current being mirrored by a current mirror and provided as a compensatory current to an input of the first differential pair circuit.

Abstract: A method and apparatus of converting a data signal in a digital rate converter including upsampling the input data signal at an input sampling rate to an intermediate data signal at an intermediate sampling rate, where the intermediate data signal sample values are stored in a buffer. A plurality of buffer position values are provided from a subset of buffer positions of the buffer to an interpolator, the subset of buffer positions being dependent upon a position indicator. An output data signal is provided by the interpolator at an output sampling rate, where the value of the output data signal is dependent upon a fractional indicator provided to the interpolator. The input sampling rate is based on a first clock signal and the output sampling rate is based on a second clock signal, wherein the first and second clock signal are independent of each other.

Abstract: A circuit for testing an analog-digital converter includes: a subtracter which receives a converted value having a plurality of bits outputted from the analog-digital converter and an expected value having a plurality of bits, the subtracter calculating a difference value having a plurality of bits between the converted value and the expected value; and a logical operation circuit which receives the difference value, the logical operation circuit performing an exclusive-NOR operation between adjacent bits in the plurality of bits constituting the difference value, thereby outputting an exclusive-NOR value having a plurality of bits.

Abstract: A semiconductor device includes a reference voltage generating section configured to generate a first reference voltage and a second reference voltage based on a voltage supplied from an external power supply, and an AD (analog/digital) conversion circuit operating based on the first reference voltage to generate an AD conversion signal corresponding to an output signal supplied from an external device. The second reference voltage is supplied to the external device, and a ratio of the first reference voltage and the second reference voltage is kept to a constant value regardless of a temperature of the semiconductor device.

Abstract: An interpolation apparatus in an encoder includes an analog-to-digital converter for digitizing a sine wave signal and a cosine wave signal, respectively. An amplitude level detecting circuit detects each amplitude level of the digitized sine wave signal and cosine wave signal. A computing circuit multiplies the amplitude level of one of the signal by an interpolation position parameter according to a tangent value at an interpolation position. A comparing circuit compares an output from the computing circuit to an output from the amplitude level detecting circuit. The comparison is made at every the interpolation position. A region detecting circuit identifies a region sectionalized by the interpolation positions adjacent to each other based on an output from the comparing circuit corresponding to each the interpolation position. The phase angle of the sine wave signal and the cosine wave signal exists in the region.

Abstract: Methods and structures are provided to enhance the linearity of amplifiers such as those which include a complementary common-collector amplifier stage. The methods and structures configure this stage so that each transistor of the stage drives an output port through a linearizing resistance. The methods and structures then control a bias current through the stage to substantially be the thermal voltage VT divided by twice the linearizing resistance.

Abstract: In some embodiments, apparatus and systems, as well as methods, may include providing an analog temperature output responsive to a combination signal comprising a combination of an analog compensation output and a reference signal, and converting the analog temperature output to a digital temperature output responsive to an analog reference signal output, perhaps according to a polynomial function. Providing a digital compensation output corresponding to the digital temperature output, and converting the digital compensation output to the analog compensation output responsive to the analog reference signal output may also be included.

Abstract: Systems and methods for canceling static and dynamic DC offsets by combining a digital DC offset correction scheme with an analog DC offset correction scheme. A feedback-based digital DC offset correction scheme provides different adjustment levels for a plurality of discrete gain states and the analog DC offset correction scheme operates in different cancellation modes dependent on a frame structure. A digital DC offset correction scheme collects DC offset control information and provides adjustment levels. In addition, a negative-feedback based switchable high pass filter has a plurality modes of operation, where one mode of operation includes an all-pass filter.

Abstract: A method for improving resolution of a current mode driver. The current mode driver is operable to provide an output that falls within a predetermined range. An embodiment of the method includes sensing a condition, such as a process condition, a voltage condition and a temperature condition. A full scale current of a digital-to-analog converter is adjusted in accordance with the condition. A current control signal is set based on an output of the digital-to-analog converter. The sensing step may include measuring a process, voltage or temperature sensitive DC parameter. Alternatively, the sensing step may include sensing a process, voltage or temperature sensitive AC parameter.

Abstract: A DC offset correction apparatus and method of a receiver in a multiband-hopping communication system is provided. The DC offset correction apparatus of the receiver in the communication system which hops to a plurality of bands, includes a controller for generating and outputting a plurality of DC offset correction signals different from each other for the respective bands; a plurality of digital-to-analog converters (DACs) for receiving, digital-to-analog converting and outputting the plurality of the DC offset correction signals from the controller; an analog multiplexer (MUX) for switching to output one of the plurality of the DC offset correction signals output from the plurality of the DACs, respectively; and an adder for adding and outputting an input signal with the output signal of the analog MUX. Accordingly, the DC offset correction apparatus can be implemented by low-speed DACs and the fast analog MUX that are relatively small-sized and low-cost elements.

Abstract: An analog-to-digital converter (ADC) circuit that converts an analog input signal into a digital output circuit includes a noise shaping first stage cascaded with a pipelined second stage. The first stage includes a sample-and-hold circuit and a first order modulator, where the first order modulator includes a noise shaping filter, a FLASH ADC and a feedback DAC. A digital dither generator is used to provide a dither signal to the ADC circuit. The second stage includes a switching circuit and an ADC. A calibration filter connected to the second stage calibrates the ADC circuit. A first reconstruction filter and a second reconstruction filter are used to recombine outputs of the first stage and the second stage of the ADC circuit. The ADC circuit allows high resolution analog-to-digital conversion at a low over-sampling rate and low power dissipation levels.

Abstract: A logarithmic analog-to-digital converter system is disclosed. The system includes a transconductor for receiving an input signal and for producing a transconductor output signal at a transconductor output, a logarithmic circuit unit that is coupled to an input of the transconductor, a comparator amplifier for receiving the transconductor output signal and for producing a comparator amplifier output signal at a comparator amplifier output, and an integrating capacitor coupled to the transconductor output signal.

Abstract: A circuit for temperature sensing receives a differential voltage that corresponds to the voltage across a forward-biased PN junction. The circuit for temperature sensing provides a first current to the PN junction, and subsequently provides a second current. Also, the temperature of the PN junction is determined based on the difference between the differential voltage when the first current is applied and the differential voltage when the second current is applied. Further, the circuit for temperature sensing self-biases half of the differential signal. The other half of the differential signal is level-shifted by an amount that is fixed and predetermined based on the self-biasing to provide a sub-ranging voltage. A sub-ranging analog-to-digital conversion is performed on the differential voltage in which the sub-ranging voltage is subtracted from the differential voltage during the conversion.

Abstract: Various embodiments of a method and apparatus for simulating temperature characteristics of a diode are disclosed. The output of a diode simulator may not depend upon its ambient temperature. Therefore, it may be used to calibrate a temperature measurement unit at any ambient temperature within its operational range regardless of the temperature to which the temperature measurement unit is to be calibrated. Even if the ambient temperature of the facility in which the calibration is performed varies during the calibration procedure, the output of the diode simulator may remain constant. These characteristics of the diode simulator may allow for calibration of a temperature measurement unit in significantly less time than by using prior art methods, which include the requirement to tightly control the temperature of one or more system components.

Abstract: An automatic gain control device (110) includes a peak detector (202) configured to receive a current output of an ADC (108) and to compare it to a previous output to produce a peak value. The automatic gain control device (110) also includes an out-of-range indicator (204) configured to receive an out-of-range signal if an input to the ADC exceeds the dynamic range of the ADC. The out-of-range indicator (204) increases the peak value if the out-of-range indicator (204) receives the out-of range signal. An error detector (206) is coupled to the out-of-range indicator (204) and the peak detector (202) and produces an error level that is the difference of an output of the out-of-range indicator (204) and a pre-selected target value. The pre-selected target value is chosen to attenuate interference signals that exceed the dynamic range of the ADC (108) but minimizes the attenuation of communication signals.

Abstract: A digital-to-analog converter is disclosed, comprising an input/output circuit, a bistable circuit connected with the input/output circuit, a clock circuit connected with the input/output circuit and the bistable circuit, and a current generator circuit connected with the clock circuit. The clock circuit acts as a switch, providing current from the current generator either to the input/output circuit or to the bistable circuit. The digital input signal switches when the current generator provides current to the bistable circuit, and switching of the input signal is asserted at the output of the converter when the current generator provides current to the input/output circuit. Therefore, switching of a clock circuit signal, rather than switching of the digital input signal determines switching of the output signal, in order to reduce intersymbol interference of the converter associated with thermal hysteresis of some of the components of the converter.

Abstract: A temperature compensation device for an automatic gain control loop in a receiver of a mobile communication terminal is disclosed. The temperature compensation device comprises a thermistor having a resistance varying with temperature to vary its output voltage, an analog/digital converter for converting the output voltage from the thermistor into a digital signal, and a temperature compensator for outputting a temperature compensation value in response to a digital signal based on a specific temperature variation from the analog/digital converter.