Abstract: A capacitance mismatch calibrating method for a successive approximation register ADC which includes at least one array of capacitors is provided. The method includes the following steps: firstly, at least two compensating capacitors are configured. A capacitor from the array of capacitors is selected as a capacitor-under-test. Then, the terminal voltages on the terminals of the array of capacitors and on the terminals of the compensating capacitors are determined. A first comparison voltage is outputted based on the determined terminal voltages. Afterwards, a sequence of comparisons is controlled based on the first comparison voltage and a second comparison voltage to output a sequence of corresponding digital bits. Finally, a calibration value is calculated to calibrate the value of a capacitor-under-test according to the digital bits.

Abstract: An analog-to-digital converter system that includes a pipeline including N successively-cascaded signal converters, each converting, according to a first clock signal, a respective portion of an input signal of the pipeline into digital codes, a code aligner for receiving and aligning the digital codes from the signal converters in the pipeline into a digital output of the system, an error extractor coupled to an amplifier input node of a selected one signal converter via a first switch for extracting an error signal, and a load system coupled to the amplifier input node of the selected one signal converter via a second switch.

Abstract: Various embodiments of methods and devices for reducing capacitor mismatch errors in a pipeline analog-to-digital converter (ADC) are disclosed. A plurality of pipeline element circuits are provided, where each pipeline element circuit corresponds to a given bit of the pipeline ADC. A first pipeline element circuit is configured to digitize analog A and B capacitor mismatch error calibration voltages generated by all the pipeline element circuits of the ADC when the pipeline ADC is operating in a capacitor mismatch calibration phase. According to one embodiment, digital representations corresponding to A and B capacitor mismatch error calibration voltages for each of the pipeline element circuits are provided to an output shift register and summing circuit, which generates capacitor mismatch error correction codes corresponding to each bit and pipeline element circuit.

Abstract: According to one embodiment, a digital signal generator includes an amplifying unit, a reference voltage generator and a modulator. The amplifying unit amplifies an analog input signal having a signal level linearly depending on a temperature. The reference voltage generator generates a reference voltage linearly depending on the temperature. The modulator converts the analog input signal amplified by the amplifying unit into a digital output signal based on the reference voltage.

Abstract: A detecting device has: a detecting element to which a first constant voltage is applied; a resistance element connected to the detecting element; a switching element having a first terminal to the resistance element, a second terminal controlled to a second constant voltage lower than the first constant voltage, and a control terminal sets the first terminal and the second terminal in a conducting state; a control unit, according to a conducting/non-conducting state, controls voltage to the control terminal to maintain a potential difference between the detecting element and the resistance element; and an AD converter converting, into a digital value, a potential of a potential difference between the first constant voltage and the first terminal being voltage-divided at the detecting element and the resistance element to the detecting element, a first reference potential is the first constant voltage, and a second reference potential is voltage to the first terminal.

Abstract: In one embodiment, an analog-to-digital conversion in an integrated circuit is evaluated by an on-die testing circuit. For example, the on-die test circuit 370 can characterize one or both of the linearity and monotonicity of the digital-to-analog conversion. The value of a conversion output for a digital input code may be compared to the value of a prior conversion output of a prior step to provide digital difference values for each step of a sweep of digital input codes. Digital difference values may be compared to one or more predetermined limits to provide one or more pass/fail tests on-board the die. Other embodiments are described and claimed.

Abstract: A system has a corrected unit, and a correction unit that performs binary search of a correction value with which an output of the corrected unit gets close to a reference value and feeds back the correction value to the corrected unit. The correction unit performs the additional comparison for comparing a first output of the corrected unit corresponding to a first correction value searched by the binary search and a second output, which is an output of the corrected unit corresponding to a second correction value that is adjacent to the first correction value and is an output that the voltage relationship to the reference value is opposite to the first output, and for selecting the first or second correction value corresponding to the first or second output closer to the reference value, and feeds back the selected correction value to the corrected unit.

Abstract: A method for compensating a linearity error of a dual digital-to-analog converter, including the steps of receiving a digital data signal which include a plurality of bits, the digital data signal indicating a voltage signal to be generated, the plurality of bits representing a set of consecutive bits being confined within a highest bit and a lowest bit, applying a high-bit-array to a first digital-to-analog converter, the high-bit-array being composed of a consecutive sub-set of the plurality of bits of the digital data signal, the sub-set including the highest bit of the digital data signal, using at least a part of a correction data of a look-up-table for manipulating at least a part of a low-bit-array, being composed of a consecutive sub-set of the plurality of bits of the digital data signal, where the sub-set includes the lowest bit of the digital data signal.

Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.

Abstract: An analog-to-digital conversion method using an RC time constant calibrator is provided. The method includes the operations of comparing a crossing time point at which a first reference signal and a second reference signal cross each other with a target time point and calibrating an RC time constant according to a result of the comparison. A length of time until the crossing time point at which a first analog signal and a second analog signal cross each other is counted based on a calibrated RC time constant. The counted value is output.

Abstract: Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.

Abstract: An electronic device includes a frequency variable circuit, a filter, and an output voltage decision circuit. The frequency variable circuit changes the sampling frequency of an analog-digital converter. The filter limits a pass band of an output signal of the analog-digital converter. The output voltage decision circuit determines the noise level of the output signal of the analog-digital converter after the output signal passes through the filter. The electronic device performs a self-diagnosis as follows. The frequency variable circuit changes the sampling frequency of the analog-digital converter to a frequency outside of the pass band of the filter so as to change the quantization noise level of the analog-digital converter. Then, the output voltage decision circuit determines whether the integral of the quantization noise level is within a predetermined range.

Abstract: An analog to digital converting device has a first converter nonlinearly converting an analog level into a first digital value every first sampling period, shorter than a second sampling period, with low precision, a second converter linearly converting the analog level into a second digital value every second sampling period with high precision, and a controller determining a correction equation by using the second digital value having a high precision in each second sampling period so as to renew the equation every second sampling period, and correcting the first digital values, obtained in each second sampling period, to corrected digital values according to the corresponding correction equation to output the corrected digital value as a digital value, obtained by substantially linearly converting the analog level, every first sampling period.

Abstract: A video signal processing system including a digital signal processing (DSP) module, a digital offset module coupled to the DSP module, a gain module, and a digital to analog converter (DAC) coupled to the DSP module and to the gain module, wherein the DAC is configured to cause the gain module to provide multiple gain signals having predetermined first values to the DAC, cause, for each of the multiple gain signals, a digital input signal value to the DAC to be ramped up, determine, for each of the multiple gain signals, a lowest digital input signal value that causes an output voltage of the DAC to be at least as high as a reference voltage, and determine a second gain value that will cause the DAC to provide a desired DAC output voltage in response to the DAC receiving a reference DAC input value.

Abstract: A system for the calibration of a programmable system-on-a-chip is described. More specifically, embodiments of the present invention relate to a system that calibrates a programmable analog block in a system-on-a-chip without the use of external components.

Abstract: An approach for calibrating a signal reconstruction system. A signal may be input to a low-pass filter. An output of the filter may be converted to a digital signal which goes to a processor which outputs a reconstruction of the signal to the filter. The reconstruction may be based on an expression that maintains the accuracy of the reconstruction. The expression may include information about samples of the input signal and a low value of the reconstruction. The expression may permit initial calibration and then maintenance of the calibration. The calibration may include compensating for inexpensive components of the filter which have values significantly different than indicated values and/or have large drifts over temperature changes.

Abstract: A photodetector includes a photoelectric conversion circuit that generates a first voltage by converting a first current generated in accordance with the illuminance of incident light into log-compressed voltage; a temperature compensation circuit that generates a second voltage by performing temperature compensation for the first voltage and generate a second current by converting the second voltage into current; and a digital signal generation circuit that generates a clock signal having an oscillation frequency depending on the second current, counts pulses of the clock signal for a certain period, and generates a digital signal using the count value for the certain period as data.

Abstract: In the digital calibration technique of the conventional time-interleaved analog/digital converter, it is impossible to perform highly-accurate calibration that supports a high-speed sampling rate of the next-generation application and achieves a high resolution. For its solution, a reference A/D conversion unit is connected in parallel to an input common to a time-interleaved A/D converter to be a calibration target, and the output of each unitary A/D conversion unit which makes up the time-interleaved A/D converter is calibrated in a digital region by using a low-speed high-resolution A/D conversion result output from the reference A/D conversion unit. Also, fCLK/N (fCLK represents an overall sampling rate of the time-interleaved A/D converter, and N is relatively prime to the number of unitary A/D conversion units connected in parallel M) is set as the operation clock frequency of the reference A/D conversion unit.

Abstract: There is provided a correction circuit for a D/A converter, comprising: a constant current source to be connected between high- and low-potential power source lines for supplying a power source voltage to the D/A converter; and a current controller which is adapted to control a current flowing to the constant current source in accordance with an input digital signal to the D/A converter, so as to reduce a variation of a sum of currents which, when the input digital signal to the D/A converter is changed, flows to the low-potential power source line from the high-potential power source line through the D/A converter and the constant current source, respectively.

Abstract: A sigma-delta converter suitable for measuring a photocurrent comprises an input node adapted to receive a current to be measured (Imeas), a capacitor connected to the input node, a clocked comparator coupled to the input node and to a reference voltage Vref at respective inputs, and a switchable current source connected to the input node which conducts a reference current Iref when switched on. The converter is arranged in a sigma-delta configuration, with the current source switched on to pull down the voltage (VCMP) at the input node when the comparator output toggles due to VCMP increasing above Vref, and to be switched off when the comparator output toggles due to VCMP falling below Vref, such that the comparator output comprises a digital bitstream which varies with Imeas.

Abstract: A signal processing device, even when a steep difference in DC level is included in a signal read from a disc such as a DVD-RAM format, cuts off the DC level and pulls the read signal into an appropriate A/D input level. A steep difference in DC level between a data section and a CAPA section is absorbed by a first offset unit, and an asymmetry which occurs due to variations in the disc manufacturing stage is corrected by a second offset unit. Further, a control signal for operating the two offset units exclusively is generated by a controller, thereby controlling both offset units.

Abstract: Methods and systems for mitigating latency in a data detector feedback loop are included. For example, a method for reducing latency in an error corrected data retrieval system is included. The method includes performing an analog to digital conversion at a sampling instant to create a digital sample, and performing a data detection on the digital sample to create a detected output. The detected output is compared with the digital sample to determine a phase error. During an interim period, the digital sample is adjusted to reflect the phase error to create an adjusted digital sample. After the interim period, the sampling instant is adjusted to reflect the phase error.

Abstract: Predictive Analog-to-Digital Converter system in one embodiment includes a sampling section producing a sampled analog input signal with a first summer section combining the sampled analog input signal and an analog prediction signal to produce an analog prediction error signal. There is at least one error analog-to-digital convertor digitizing the analog prediction error signal, wherein a digital error signal output from the error analog-to-digital convertor is one of a full bitwidth error signal during an over-range condition else a lower bitwidth error signal. A second summer is coupled to the digital error signal output and a digital prediction signal, and generates a full bitwidth digital output signal. A feedback section is coupled to the digital output signal and providing the digital prediction signal and the analog prediction signal.

Abstract: An apparatus for compensating for an error of a time-to-digital converter (TDC) is disclosed to receive a delay phase from a phase detector including the TDC and a phase error including a TDC error and compensate for the TDC error to have a time resolution higher by N times (N is a natural number). The apparatus includes: a fragmenting and multiplying unit fragmenting the delay phase by N times (N is a natural number) to generate first to (N?1)th fragmented delay phases; an adding unit adding each of the first to the (N?1)th fragmented delay phases to the phase error to generate first to (N?1)th phase errors; and a comparison unit acquiring a phase error compensation value nearest to an actual phase error from the phase error and the first to (N?1)th phase errors.

Abstract: A system for sensing, sampling and processing an input signal includes an encoding subsystem for sensing and sampling the input signal into a plurality of distinct data paths using a sub-Nyquist sampling rate. The system architecture is designed to induce encoded variations between the plurality of data paths, such as channel differences in amplitude or phase. The system additionally includes a decoding subsystem for reconstructing the encoded signal back to its original bandwidth. Preferably, the decoding subsystem exploits mismatch effects between the plurality of data paths as a form of signal diversity to resolve ambiguities introduced from sub-Nyquist signal sampling during signal reconstruction.

Abstract: A receiver has an offset application circuit for applying a known offset to an input signal, and a decision circuit for comparing the offset-applied input signal with a reference voltage. The level of the input signal is determined based on the known offset and on the result output from the decision circuit. With this configuration, a large common mode voltage can be eliminated in a circuit used for signal transmission.

Abstract: Methods, and other embodiments associated with signal filtering are described. According to one embodiment, an apparatus includes an analog-to-digital converter that generates a first digital component and a second digital component from an analog signal. A filter filters the first digital component and the second digital component to substantially align the phase of the first digital component and the phase of the second digital component.

Abstract: An integrated circuit device includes a plurality of data line driver circuits, a first correction D/A conversion circuit, and a plurality of D/A conversion circuits. Each of the data line driver circuits includes an operational amplifier, an input capacitor, and a first correction capacitor. Each of the D/A conversion circuits outputs an output signal to the input capacitor. The first correction D/A conversion circuit outputs a correction output voltage to the first correction capacitors to correct data signals output from the data line driver circuits.

Abstract: Techniques are disclosed for improving the dynamic performance of digital-to-analog converters (DAC), by compensating for the unique delay characteristics of each bit in the DAC summing junction to equalize the delays. In one example case, a DAC device is provided that includes a plurality of current sources and a plurality of switches, each switch operatively coupled between a corresponding one of the current sources and a summing junction that is operatively coupled to an analog output. The device further includes a plurality of switch control lines configured to receive a digital input, each switch control line for controlling a corresponding one of the switches. The device further includes a plurality of compensation delay elements, each associated with a corresponding one of the switch control lines and providing a different delay value.

Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.

Abstract: Imbalance and distortion cancellation for composite analog to digital converter (ADC). Such an ‘ADC’ is implemented using two or more ADCs may be employed for sampling (e.g., quantizing, digitizing, etc.) of an analog (e.g., continuous time) signal in accordance with generating a digital (e.g., discrete time) signal. Using at least two ADCs allows for the accommodation and sampling of various signals having a much broader dynamic range without suffering degradation in signal to noise ratio (SNR). Generally, the signal provided via at least one of the paths corresponding to at least one of the respective ADCs is scaled (e.g., attenuated), so that the various ADCs effectively sample signals of different magnitudes. The ADCs may respectively correspond to different magnitude and/or power levels (e.g., high power, lower power, any intermediary power level, etc.). Various implementations of compensation may be performed along the various paths corresponding to the respective ADCs.

Abstract: A demodulator capable of compensating for an offset voltage of a radio frequency (RF) signal, and a method of compensating for the offset voltage of the RF signal are provided. The demodulator includes an analog-to-digital conversion (ADC) unit for converting a first analog signal corresponding to a difference between the RF signal comprising the offset voltage and an analog reference signal into a first digital signal, and a compensation voltage generation unit for converting the first digital signal into an offset compensation voltage. The ADC unit converts a second analog signal corresponding to a difference between the RF signal comprising the offset voltage and the offset compensation voltage into a second digital signal. Accordingly, the offset voltage included in the RF signal is compensated for, and thus distortion and a signal-to-noise ratio (SNR) of the RF signal are reduced. This leads to an improvement of the reception sensitivity of an RF receiver.

Abstract: An analog-to-digital converter includes a first preamplifier receiving a first reference voltage and an input signal, a second preamplifier receiving a second reference voltage and the input signal, a first preamplifier calibrator placed for the first preamplifier and adjusting an input offset of the first preamplifier, a second preamplifier calibrator placed for the second preamplifier and adjusting an input offset of the second preamplifier, an interpolator placed between output terminals of the first and second preamplifiers and generating an interpolation signal having a voltage value between a first output signal from the first preamplifier and a second output signal from the second preamplifier, comparators receiving the first output signal, the second output signal or the interpolation signal and outputting a digital value based on the received signal, and comparator calibrators placed for at least comparators receiving the interpolation signal among the comparators and adjusting input offsets of the c

Abstract: An analog to digital converting device has a first converter nonlinearly converting an analog level into a first digital value every first sampling period, shorter than a second sampling period, with low precision, a second converter linearly converting the analog level into a second digital value every second sampling period with high precision, and a controller determining a correction equation by using the second digital value having a high precision in each second sampling period so as to renew the equation every second sampling period, and correcting the first digital values, obtained in each second sampling period, to corrected digital values according to the corresponding correction equation to output the corrected digital value as a digital value, obtained by substantially linearly converting the analog level, every first sampling period.

Abstract: An AD converting apparatus converts an analog input signal into a digital output signal. The apparatus includes a plurality of AD converters that are supplied with sampling clocks differing from each other by a prescribed phase and that each output an individual signal obtained by digitizing the input signal according to the sampling clock supplied thereto, a common compensating section that commonly compensates for prescribed common non-linear distortion in the individual signals, and a plurality of individual compensating sections that each individually compensate for individual non-linear distortion in a corresponding one of the individual signals. The individual non-linear distortion is obtained as a ratio between the non-linear distortion and the common non-linear distortion in each individual signal. The apparatus further includes a combining section that combines the individual signals to generate the output signal.

Abstract: The present invention discloses an FFT-based ADC calibration system able to solve the problems of capacitor mismatch and finite Op-Amp open loop gain, which result in that the radix of the gain of each stage is not exactly equal to 2. The present invention uses an FFT processor to calculate the real radix of each stage and uses a digital method to generate new digital outputs. As the present invention can compensate the finite gain of Op-Amp, the specification of Op-Amp is not so critical in designing ADC. Therefore, the low-gain Op-Amp can be used to reduce the power consumption of ADC. Further, the FFT-based calibration technology can considerably promote the performance of ADC.

Abstract: In an A/D converting apparatus, a converting unit has an input terminal and an input-output characteristic. The input-output characteristic has temperature dependence, and the converting unit carries out a process of converting an input voltage signal to digital data. A temperature determining unit has information representing a relationship between a variable of an output of the converting unit and a variable of a temperature around the converting unit according to the temperature dependence of the input-output characteristic of the converting unit. When the specified voltage is applied to the input terminal of the converting unit, the temperature determining unit determines a value of the temperature around the converting unit based on the information and the specified voltage. A reducing unit reduces temperature dependence of the process of converting an input voltage signal to digital data based on the determined value of the temperature around the converting unit.

Abstract: A D/A converter includes a D/A converter base part having a first D/A converter unit performing D/A conversion of high order bits and a second D/A converter unit performing D/A conversion of low order bits and including an auxiliary bit assigned an identical weight to a least significant bit, a correction D/A converter part, an error detection processing section generating a digital code to be set to a correction D/A converter unit in the correction D/A converter part, and a control section. The control section compares one bit current source with another bit current source in a lower order than the one bit current source, and corrects a value of the one bit current source by causing the error detection processing section to generate the digital code to be set to the correction D/A converter unit when judging that the value of the one bit current source changes.

Abstract: A receiver circuit is capable of improving its operating characteristics. The receiver circuit includes a variable converter configured to output off-set control voltages in a first output range in a first operation mode and output the off-set control voltages in a second output range in a second operation mode according to a test mode activation signal, and a sense amplifier configured to sense input data based on a sensitivity, wherein the sensitivity is controlled by the off-set control voltages.

Abstract: In a wireless transmitter and receiver, a background calibration type analog-to-digital converter generally occupies a large area because of the phase compensating capacity of an op-amp included in a reference analog-to-digital conversion unit. Further, the calibration type analog-to-digital converter generally requires a sample and hold circuit to exclude influence of parasitic capacitance of wirings, thereby increasing power consumption. Digital calibration is performed by using, as a signal for calibration, an input signal of a digital-to-analog converter in a transmitter circuit of the wireless transmitter and receiver and inputting an output signal from the digital-to-analog converter to the analog-to-digital converter in the receiver circuit.

Abstract: For digitizing analog measurement signals, an analog-to-digital converter is used, wherein the offset to be subtracted from an analog measurement value is taken to account within a locked loop by means of which an analog-to-digital converter operating according to the modulation principle is fed back.

Abstract: A method is provided to produce an error corrected digital output from a temperature measurement system that generates digital outputs representative of the output of one or more temperature sensors. In an embodiment of the invention the method comprises: storing in a plurality of memory locations corresponding error correction data, with each memory location having a correlation to a corresponding range of the digital outputs; utilizing each digital output to identify a corresponding one of the memory locations; accessing the corresponding one memory location to obtain error correction data specific to the digital output; and utilizing the error correction data specific to the digital output to correct the digital output, whereby an error corrected digital output is generated.

Abstract: A signal processing system for reducing calibration-related distortions in a complete-channel signal generated by a multi-channel subsystem, such as an interleaved ADC, includes a channel separator for separating the distorted digital signal into its various sub-channels and a single-channel corrector for independently processing each sub-channel to reduce distortion products present therein. The system additionally includes a subchannel re-combiner for combining the plurality of sub-channels processed by the single-channel corrector and a multi-channel corrector for calibrating each of plurality of sub-channels relative to one another to yield an equalized, complete-channel output signal. The multi-channel corrector includes a bank of optimized filters, each filter being assigned to a corresponding sub-channel of the complete-channel signal.

Abstract: System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.

Abstract: A voltage regulating power supply includes: a switching regulator powered by a supply voltage level, the switching regulator for generating a first output voltage in accordance to a first reference voltage; and a linear regulator coupled to the first output voltage, the linear regulator for generating a second output voltage in accordance to a second reference voltage; wherein a noise sensitive circuit draws power from the second output voltage.

Abstract: To prevent the value of a successive approximation register, which should be holding the value of the comparison result, from changing due to noise or the like during the A/D conversion by a successive approximation A/D converter, a detection circuit is arranged on an arbitrary bit of a successive approximation register 5 to detect the change in the value of the bit. The detection circuit detects the change in the value during the period in which the successive approximation register should be holding the data, such as during the period other than the comparison time, and outputs an abnormal conversion detection signal.

Abstract: A PRA-DAC is disclosed. The PRA-DAC is operable to increase its conversion speed.

Abstract: A calibration device includes a comparison unit, a counting unit, a memory, and a compensation circuit. A residue of a sub analog-to-digital converter is compared with a first and a second voltage by the comparison unit for generating a comparison result. A number of times of the residue voltage, out of bounds defined by the first and the second voltage, is counted by the counting unit in an ith period according to the comparison result. The number of times of the residue voltage out of the bounds in an (i?1)th period is stored in the memory. A clock of the sub ADC is adjusted by the compensation circuit into a direction based on the number of times of the residue voltage out of the bounds in the ith period and the number of times of the residue voltage out of the bounds in the (i?1)th period.

Abstract: A hybrid analog to digital converter circuit for a feedback input to a digital controller of a power supply includes a high resolution, analog to digital converter circuit in communication with a voltage error signal. The high resolution analog to digital converter circuit is configured to provide a first correction signal to the digital controller when the voltage error signal is within a first error range. The hybrid analog to digital converter circuit also includes at least one flash analog to digital converter circuit in communication with the voltage error signal. The flash analog to digital converter circuit(s) is configured to provide at least a second correction signal to the digital controller when the voltage error signal is within at least a second error range.

Abstract: A reference voltage generating unit generates a plurality of analog reference voltages, and an A/D converting unit converts the analog reference voltages thus generated and an analog input voltage input from an external device to digital reference values. A CPU generates, based on the analog reference voltages and the digital reference values converted from the analog reference voltages, an equation for correcting the analog input voltage to be converted to a digital value falling in a range of the digital reference values. With the equation generated, the CPU calculates the analog input voltage for the digital value obtained by conversion.