Having Variable Sampling Rate Patents (Class 341/123)
  • Patent number: 10298251
    Abstract: An embodiment electronic circuit includes an electronic switch comprising a load path, a first protection circuit configured to generate a first protection signal based on a current-time-characteristic of a load current through the load path of the electronic switch, and a drive circuit configured to drive the electronic switch based on the first protection signal. The first protection circuit includes an analog-to-digital converter (ADC) configured to receive an ADC input signal representing the load current, to sample the ADC input signal once in each of a plurality of successive sampling periods, and to output an ADC output signal that includes a sequence of values such that each of the values represents a respective sample of the ADC input signal. The ADC is configured to pseudo-randomly select a sample time in each sampling period.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: May 21, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Robert Illing, Christian Djelassi, Markus Ladurner, David Jansson
  • Patent number: 10235615
    Abstract: An electronic device and corresponding method are used for acquiring, storing, and transmitting radio frequency identification (RFID) credential data previously stored in another device. The electronic device includes a mechanical housing, electronic circuitry mounted within the mechanical housing, a power source coupled to the electronic circuitry to provide electrical power to the electronic circuitry, and an interface mechanism coupled to the electronic circuitry in a manner to allow a human user to effect operation of the electronic circuitry. The electronic circuitry is configured to (a) receive an initial response RF signal emitted by the other device in response to an initial interrogation RF signal, where the initial response RF signal carries the RFID credential data, (b) acquire the RFID credential data from the initial response RF signal, (c) store the RFID credential data, and (d) transmit to an interrogator device an outgoing RF signal that carries the RFID credential data.
    Type: Grant
    Filed: October 1, 2017
    Date of Patent: March 19, 2019
    Assignee: Tiny Labs, Inc.
    Inventor: Elliot Benjamin Buller
  • Patent number: 10219697
    Abstract: Systems and methods for biosignal acquisition, and in particular, electrocorticography signal acquisition, are disclosed for small area, low noise recording and digitization of brain signals from electrode arrays.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: March 5, 2019
    Assignees: The Regents of the University of California, Cortera Neurotechnologies, Inc.
    Inventor: Rikky Muller
  • Patent number: 10218269
    Abstract: Provided is a switching regulator in which a MOS transistor Q1 (first switch) and a MOS transistor Q2 (second switch) are complementarily turned on/off according to an output voltage VOUT, and in which a MOS transistor Q3 (third switch) and a MOS transistor Q4 (fourth switch) are complementarily turned on/off by fixing an on-duty D of the MOS transistor Q3 (third switch) in a step up/down mode. The switching regulator performs current mode control according to information of current flowing in the second switch.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: February 26, 2019
    Assignee: Rohm Co., Ltd.
    Inventors: Yuhei Yamaguchi, Tetsuo Tateishi
  • Patent number: 10142489
    Abstract: An Initial Profile Application Apparatus (IPAA) is operable to apply an initial profile to a modem pair connection system, the modem pair connection system comprising a first modem, a corresponding second modem and a metallic wire connection, wherein the first and second modems are operable to establish a data connection between themselves over the metallic wire connection. The IPAA comprises: a receiver; an evaluator; a line database; a comparator; a determiner; and an applicator.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: November 27, 2018
    Assignee: British Telecommunications Public Limited Company
    Inventors: Trevor Linney, Ian Horsley
  • Patent number: 10101433
    Abstract: A system and method of locating a key fob with respect to a vehicle includes: detecting short-range wireless signals communicated between the key fob and a plurality of nodes at the vehicle using an IEEE 802.11 protocol; calculating the distance of the key fob relative to each of the nodes attached to the vehicle based on the detected short-range wireless signal; and determining the location of the key fob based on the distance of the key fob relative to each of the nodes.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: October 16, 2018
    Assignee: GM Global Technology Operations LLC
    Inventors: Moshe Laifenfeld, Vyacheslav Berezin, Igal Kotzer, Kobi Jacob Scheim
  • Patent number: 9894445
    Abstract: A hearing device comprises a receiver, an input buffer and a sample processor, the receiver being adapted to receive samples of a digital audio signal and feed received samples as a digital input signal to the input buffer, the sample processor being adapted to process the buffered samples to provide samples of a digital output signal such that the digital output signal is a sample-rate converted representation of the digital input signal with a predetermined target sample rate. The hearing device further comprises a latency controller adapted to estimate the quality of reception of the digital audio signal and to control the processing of the buffered samples in dependence on the estimated quality of reception.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: February 13, 2018
    Assignee: SENNHEISER COMMUNICATIONS A/S
    Inventor: Svend Feldt
  • Patent number: 9725006
    Abstract: An electric vehicle charging station with a field upgradeable communications facility is provided. The invention includes a sealable housing including a first compartment and a second compartment, the second compartment including an access to an upgrade port; a partition within the housing that is adapted to insulate the first compartment from the second compartment, the partition including an opening providing access the upgrade port; and an EVSE charging station control circuit configured to recognize a communication module when coupled to the upgrade port and to use the communication module for communications if the communication module is connected. Numerous additional aspects are disclosed.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: August 8, 2017
    Assignee: SIEMENS INDUSTRY, INC.
    Inventors: John R. DeBoer, III, Mario Bilac, Harry Price Haas, John Quentin Cowans, Timothy Biedrzycki, William A. King, Jr.
  • Patent number: 9628147
    Abstract: A method of automatically adjusting a determination voltage used in an induction type power supply system includes detecting an output voltage of a signal analysis circuit; adding a first threshold value to the output voltage to generate a first determination voltage and subtracting a second threshold value from the output voltage to generate a second determination voltage; outputting the first determination voltage as a reference voltage; and comparing a trigger signal of the signal analysis circuit and the reference voltage, in order to generate a first data code; wherein when the step of comparing the trigger signal of the signal analysis circuit and the reference voltage in order to generate the first data code fails, the method further includes outputting the second determination voltage as the reference voltage and comparing the trigger signal of the signal analysis circuit and the reference voltage, in order to generate a second data code.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: April 18, 2017
    Assignee: Fu Da Tong Technology Co., Ltd.
    Inventors: Ming-Chiu Tsai, Chi-Che Chan
  • Patent number: 9571119
    Abstract: A method includes generating a sampling signal having a non-uniform sampling interval and sampling a received signal with an analog-to-digital converter (ADC) using the sampling signal. The method also includes mapping the sampled received signal onto a frequency grid of sinusoids, where each sinusoid has a signal amplitude and a signal phase. The method further includes estimating the signal amplitude and the signal phase for each sinusoid in the frequency grid. In addition, the method includes computing an average background power level and detecting signals with power higher than the average background power level. The non-uniform sampling interval varies predictably.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: February 14, 2017
    Assignee: RAYTHEON COMPANY
    Inventors: Bradley Flanders, Ian S. Robinson
  • Patent number: 9436974
    Abstract: Methods, computer program products, and computer systems for recovering data of scene are provided. The techniques include: obtaining, by at least one processor, data of a scene; re-sampling, by the at least one processor, the data of the scene to obtain re-sampled sensing data of the scene and a corresponding sensing matrix; and constructing, by the at least one processor, recovered data of the scene using the re-sampled sensing data of the scene and the corresponding sensing matrix. In one embodiment, the method includes enhancing occluded data of the scene to construct the recovered data of the scene, where the recovered data of the scene facilitates identification of the scene. In another embodiment, the method includes compressing original data of a scene, the compressing including sampling the original data of the scene to select the data of the scene.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: September 6, 2016
    Assignee: Vencore Labs, Inc.
    Inventors: Chi Leung Lau, Ted K. Woodward
  • Patent number: 9348045
    Abstract: There is provided herein a method of passive seismic acquisition that utilizes real time or near real time computation to reduce the volume of data that must be moved from the field to the processing center. Much of the computation that is traditionally applied to passive source data can be done in a streaming fashion. The raw data that passes through a field system can be processed in manageable pieces, after which the original data can be discarded and the intermediate results accumulated and periodically saved. These saved intermediate results are at least two, more likely three, orders of magnitude smaller than the raw data they are derived from. Such a volume of data is trivial to store, transport or transmit, allowing passive seismic acquisition to be practically used for continuous near-real-time seismic surveillance.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: May 24, 2016
    Assignees: BP Corporation North America Inc., BP Norge AS
    Inventors: Olav Inge Barkved, Joseph Anthony Dellinger, John Etgen
  • Patent number: 9350371
    Abstract: In one aspect, an electrical signal converter is disclosed. The exemplary electrical signal converter may include a plurality of ordered converter elements. Element selection logic may be provided to pseudorandomly select a pointer to a switch matrix, wherein the switch matrix maps converter elements according to a stepwise “delta-two-maximum pattern.” Advantageously, pseudorandom stepwise delta-two-maximum patterns may be applied both to a first order converter, and to a feedback converter for error correction.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: May 24, 2016
    Assignee: Analog Devices Global
    Inventors: Trevor Clifford Caldwell, Richard E. Schreier, David Alldred, Wenhua W. Yang
  • Patent number: 9344110
    Abstract: A delta-sigma modulator capable of outputting an output signal including a plurality of signals having different frequencies. The delta-sigma modulator includes: a plurality of input ports to which a plurality of input signals having different frequencies are inputted, respectively; a plurality of loop filters provided corresponding to the plurality of input ports, respectively; an adder configured to add outputs of the plurality of loop filters; and a quantizer configured to quantize an output of the adder. The plurality of loop filters each receive the input signal inputted to the corresponding input port and a feedback signal of an output of the quantizer. The plurality of loop filters each have a characteristic of stopping noise in the vicinity of a frequency of the input signal inputted to the corresponding input port.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: May 17, 2016
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Takashi Maehata
  • Patent number: 9335771
    Abstract: A feedforward control method, which includes: determining, whether the input voltage rapidly changes or slowly changes; when the input voltage rapidly changes, determining, a first feedforward gain coefficient corresponding to the difference between a input voltage reference value and a first input voltage measurement value acquired by a high-speed low-precision analog-to-digital converter in a current sampling period; when the input voltage slowly changes, determining a second feedforward gain coefficient which is a ratio of the input voltage reference value to a second input voltage measurement value acquired by a low-speed high-precision analog-to-digital converter in the current sampling period; and using the first or the second feedforward gain coefficient as a feedforward gain coefficient of a current input voltage, multiplying the feedforward gain coefficient by an output value of a feedback loop of an output voltage, so as to control stable output of the output voltage.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: May 10, 2016
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Zhaozheng Hou, Chao Jia
  • Patent number: 9256405
    Abstract: A device is configured to receive optimization information associated with a model, determine an amount of delay to be inserted into the model, and determine a sampling factor by which a first data rate associated with a signal is to be modified into a second data rate. The device is configured to determine a region of interest, insert an upsampling block that upsamples the signal entering the region of interest based on the sampling factor, and insert a downsampling block, associated with a unit of delay, which downsamples the signal exiting the region of interest based on the sampling factor. The device is configured to convert the unit of delay into a fast delay block, corresponding to the amount of delay, and insert the fast delay block in the region of interest. The device is configured to generate code associated with the model, and provide the code.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: February 9, 2016
    Assignee: The MathWorks, Inc.
    Inventors: Sankalp S. Modi, Wang Chen, Zhihong Zhao, Partha Biswas
  • Patent number: 9230302
    Abstract: Described is a system for foveated compressive sensing. The system is configured to receive an input image f of a scene and initialize a measurement matrix. Global measurements are then performed, with a lower resolution image of the scene thereafter reconstructed. Task salient regions are extracted from the low resolution image. Thereafter, the system estimates a task-specific operator and detects regions-of-interest (ROI) based on the task salient regions. An ROI-adapted and foveated measurement matrix is then generated. Local measurements are then performed on task-relevant ROIs. A higher resolution image can then be reconstructed of the scene to allow for identification of objects in the ROI.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: January 5, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: Yuri Owechko, Kang-Yu Ni, Shankar R. Rao
  • Patent number: 9049491
    Abstract: A network device may receive a signal from a headend, wherein a bandwidth of the received signal spans from a low frequency to a high frequency and encompasses a plurality of sub-bands. The network device may determine, based on communication with the headend, whether one of more of the sub-bands residing above a threshold frequency are available for carrying downstream data from the headend to the circuitry. The network device may digitize the signal using an ADC operating at a sampling frequency. The sampling frequency may be configured based on a result of the determining. When the sub-band(s) are available for carrying downstream data from the headend to the network device, the sampling frequency may be set to a relatively high frequency. When the sub-band(s) are not available for carrying downstream data from the headend to the network device, the sampling frequency may be set to a relatively low frequency.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: June 2, 2015
    Assignee: MaxLinear, Inc.
    Inventors: Curtis Ling, Timothy Gallagher, Sridhar Ramesh
  • Patent number: 9013339
    Abstract: To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digital post-processing is prohibitive in high speed systems, indicating a need for blind mismatch compensation. Even with blind bandwidth mismatch estimation, though, adjustment of the filter characteristics of track-and-hold (T/H) circuits within the TI ADCs can be difficult. Here, a T/H circuit architecture is provided that uses variations of the gate voltage of a sampling switch (which varies the “on” resistance of the sampling switch) to change the bandwidth of the T/H circuits so as to precisely match the bandwidths.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: April 21, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Robert F. Payne, Marco Corsi
  • Patent number: 8976804
    Abstract: In a programmable logic device with a number of different types of serial interfaces, different power supply filtering schemes are applied to different interfaces. For interfaces operating at the lowest data rates—e.g., 1 Gbps—circuit-board level filtering including one or more decoupling capacitors may be provided. For interfaces operating at somewhat higher data rates—e.g., 3 Gbps—modest on-package filtering also may be provided, which may include power-island decoupling. For interfaces operating at still higher data rates—e.g., 6 Gbps—more substantial on-package filtering, including one or more on-package decoupling capacitors, also may be provided. For interfaces operating at the highest data rates—e.g., 10 Gbps—on-die filtering, which may include one or more on-die filtering or regulating networks, may be provided. The on-die regulators may be programmably bypassable allowing a user to trade off performance for power savings.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: March 10, 2015
    Assignee: Altera Corporation
    Inventors: Sergey Shumarayev, Wilson Wong, Thungoc M. Tran, Tim Tri Hoang
  • Patent number: 8928509
    Abstract: A sampling device for sampling an incoming signal in order to generate an output signal having a different frequency spectrum from the incoming signal. The device comprises a sampler configured to sample the incoming signal at a series of intervals in time, wherein the series of intervals includes a temporally repeating sequence of intervals, and wherein the duration of successive intervals varies throughout the series.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: January 6, 2015
    Assignee: Thales Holdings UK PLC
    Inventor: Benoit Gorisse
  • Patent number: 8912941
    Abstract: An analog-to-digital conversion circuit includes: a clock generating circuit which generates a clock signal including a first initial period and plural normal periods following the first initial period, the first initial period being one of a high period and a low period and being a first period immediately after a reset release, each of the normal periods being one of a high period and a low period and shorter than the first initial period; and an incremental analog-to-digital converter which operates using the clock signal.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: December 16, 2014
    Assignee: Panasonic Corporation
    Inventor: Yusuke Tokunaga
  • Patent number: 8890733
    Abstract: A device including a sample and hold circuit for providing a signal related to an input analogue current signal, by sampling the input analogue current signal and integrating it on capacitive means, thereby charging the capacitive means to a charge value. The capacitive means being configurable to dynamically change its effective capacitance value in order to shape a voltage signal present on the capacitive means such that the charge value remains unchanged. The device also including an analogue-to digital conversion (ADC) and control circuit arranged for performing an ADC of the at least one related signal at the output of the sample and hold circuit into an output digital signal, the ADC and control circuit including successive approximation ADC means for considering the value of the voltage signal on the capacitive means and converting the charge value present in the capacitive means into the digital output signal.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: November 18, 2014
    Assignees: IMEC, Renesas Electronics Corporation
    Inventors: Takaya Yamamoto, Jan Craninckx
  • Patent number: 8854238
    Abstract: An asynchronous sampling frequency conversion device includes: a storage unit configured to store input digital signals; a data specifying unit configured to specify first data and second data based on a ratio of a sampling frequency of the input digital signal to a sampling frequency of an output digital signal, the first data being sampled at a sampling timing immediately before an ith (where i is a natural number) sampling timing of the output digital signal among the input digital signals stored in the storage unit, the second data being sampled at the sampling timing immediately after the ith sampling timing of the output digital signal; and an output data value calculator configured to calculate a value of ith data of the output digital signal based on the first data and the second data specified by the data specifying unit and the ratio.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: October 7, 2014
    Assignee: JVC KENWOOD Corporation
    Inventor: Masami Nakamura
  • Patent number: 8830096
    Abstract: A method of reducing a water-wave noise for an analog to digital conversion includes performing sampling on an analog input signal; determining whether the analog input signal is interfered with by a periodic noise such that a water wave is generated; and executing one or both of the following steps when the analog input signal is interfered with by the periodic noise: adjusting a sampling frequency of the ADC, and adjusting a noise frequency of the periodic noise.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: September 9, 2014
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Po-Chin Hu, Liming Xiu
  • Patent number: 8831158
    Abstract: In one embodiment, a method comprising sampling by a first sampling unit a first signal received via a first antenna; and sampling by a second sampling unit a second signal received via a second antenna, the sampling of the second signal commencing in synchronization with the sampling of the first signal by the first sampling unit based on an accumulated value, the first and second signal sharing common information.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: September 9, 2014
    Assignee: Broadcom Corporation
    Inventors: Ari Huostila, Chun-Hsuan Kuo
  • Patent number: 8786472
    Abstract: Generally described herein are methods and systems for sample rate conversion of non-integer and integer factors. In one or more embodiments an apparatus can include a sample rate converter that can include an input configured to receive an input signal with a first frequency and an output configured to provide an output signal with a second frequency different from the first frequency. The sample rate converter can include a filter coefficient lookup table and a numerically controlled oscillator configured to provide filter coefficients from the filter coefficient lookup table at a rate that is a function of the first frequency and the second frequency.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: July 22, 2014
    Assignee: Raytheon Company
    Inventor: Gregary B. Prince
  • Patent number: 8751097
    Abstract: A method and system for using Equivalent Time Sampling to improve the effective sampling rate of sensor data, and using the improved-resolution data for diagnosis and control. Data samples from existing sensors are provided, where the sampling rate of the existing sensors is not sufficient to accurately characterize the parameters being measured. High-resolution data sets are reconstructed using Equivalent Time Sampling. High-resolution input data sets are used in a system model to simulate the performance of the system being measured. Results from the system model, and high-resolution output data sets from Equivalent Time Sampling, are provided to an estimator, which provides accurate estimation of measured quantities and estimation of quantities not measured. Output from the estimator is used for fault diagnosis and control of the system being measured.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: June 10, 2014
    Assignees: GM Global Technology Operations LLC, Indian Institute of Technology Kharagpur
    Inventors: Soumen De, Pattada A. Kallappa, Pulak Bandyopadhyay, Siddhartha Mukhopadhyay, Somnath Sengupta, Alok Kanti Deb
  • Publication number: 20140152478
    Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs.
    Type: Application
    Filed: January 26, 2013
    Publication date: June 5, 2014
    Applicant: CREST SEMICONDUCTORS, INC.
    Inventors: Donald E. Lewis, Ryan James Kier, Rex K. Hales, Yusuf A. Haque
  • Patent number: 8570405
    Abstract: An imaging system and method that captures compressive sensing (CS) measurements of a received light stream, and also obtains samples of background light level (BGLL). The BGLL samples may be used to compensate the CS measurements for variations in the BGLL. The system includes: a light modulator to spatially modulate the received light stream with spatial patterns, and a lens to concentrate the modulated light stream onto a light detector. The samples of BGLL may be obtained in various ways: (a) injecting calibration patterns among the spatial patterns; (b) measuring complementary light reflected by digital micromirrors onto a secondary output path; (c) separating and measuring a portion of light from the optical input path; (d) low-pass filtering the CS measurements; and (e) employing a light power meter with its own separate input path. Also, the CS measurements may be high-pass filtered to attenuate background light variation.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: October 29, 2013
    Assignee: InView Technology Corporation
    Inventors: Kevin F. Kelly, Richard G. Baraniuk, Leonore McMackin, Robert F. Bridge, Sujoy Chatterjee, Donna E. Hewitt, Tyler H. Weston
  • Patent number: 8570406
    Abstract: An imaging system and method that captures compressive sensing (CS) measurements of a received light stream, and also obtains samples of background light level (BGLL). The BGLL samples may be used to compensate the CS measurements for variations in the BGLL. The system includes: a light modulator to spatially modulate the received light stream with spatial patterns, and a lens to concentrate the modulated light stream onto a light detector. The samples of BGLL may be obtained in various ways: (a) injecting calibration patterns among the spatial patterns; (b) measuring complementary light reflected by digital micromirrors onto a secondary output path; (c) separating and measuring a portion of light from the optical input path; (d) low-pass filtering the CS measurements; and (e) employing a light power meter with its own separate input path. Also, the CS measurements may be high-pass filtered to attenuate background light variation.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: October 29, 2013
    Assignee: InView Technology Corporation
    Inventors: Kevin F. Kelly, Richard G. Baraniuk, Lenore McMackin, Robert F. Bridge, Sujoy Chatterjee, Donna E. Hewitt, Tyler H. Weston
  • Patent number: 8538329
    Abstract: A sensing and recovery system includes a sensing unit and a recovery unit coupled together. The sensing unit includes a sensor to generate a bandlimited continuous time analog signal, and a modulator coupled to the sensor to generate a modulated analog signal based upon modulation of the bandlimited continuous time analog signal at a modulating rate at least equal to a Nyquist rate for the bandlimited continuous time analog signal. A compressive sensing circuit is coupled to the modulator to generate a compressed sensed signal based upon conversion of the modulated analog signal at a sampling rate less than the Nyquist rate. The recovery unit recovers the bandlimited continuous time analog signal from the compressed sensed signal.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: September 17, 2013
    Assignee: Harris Corporation
    Inventors: Edward R. Beadle, Charles Zahm
  • Patent number: 8508394
    Abstract: In a semiconductor integrated circuit, having a central processing unit, a clock generating unit, an A/D converter and a sample and hold signal generating circuit, noise from an element that operates in accordance with operation timing that is difficult to predict beforehand is reduced. In a calibration operation, in response to a clock signal from the clock generating unit, a sample and hold signal generating circuit supplies a plurality of clock signals sequentially to a sample and hold circuit of the A/D converter. By analyzing a plurality of digital signals that are sequentially output from an A/D conversion circuit of the A/D converter, a timing of a holding period for allowing A/D conversion under a low noise condition is selected from the clock signals. In normal operation, a clock signal selected by the calibration operation is supplied as a sample and hold control signal to the sample and hold circuit.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: August 13, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiyuki Ishioka, Takuji Aso
  • Patent number: 8482444
    Abstract: A particular method includes calibrating data capture by a data register, where the data register receives a data signal from an analog-to-digital converter (ADC). The data capture may be calibrated by determining a peak value of a set of output values of the data register, where the peak value is determined in response to the ADC receiving a known input signal, and increasing a delay interval applied to registering of a value by the data register when the peak value satisfies a threshold.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: July 9, 2013
    Assignee: The Boeing Company
    Inventors: David C. Dominguez, Paul L. Deming
  • Patent number: 8390490
    Abstract: Compressive sensing is an emerging field that attempts to prevent the losses associated with data compression and improve efficiency overall, and compressive sensing looks to perform the compression before or during capture, before energy is wasted. Here, several analog-to-digital converter (ADC) architectures are provided to perform compressive sensing. Each of these new architectures selects resolutions for each sample substantially at random and adjusts the sampling rate as a function of these selected resolutions.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: March 5, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Patrick Satarzadeh, Marco Corsi, Victoria Wang, Arthur J. Redfern, Fernando Mujica, Charles Sestok, Kun Shi, Venkatesh Srinivasan
  • Patent number: 8311170
    Abstract: A data transfer system which can surely transfer data between two function circuits which operate synchronously with different clock frequencies. A data loading signal is generated just before timing when edges of two clocks of different frequencies coincide. Only information data received by the function circuit on a transfer data reception side within an existence period of the data loading signal is determined to be valid.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: November 13, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Atsushi Yusa
  • Patent number: 8306147
    Abstract: A 4× over-sampling data recovery system consists of a charge pump PLL, a 4× over-sampler, a data regenerator and a digital PLL. The charge pump PLL receives a clock signal and generates a plurality of multiplicative clock signals in response to the clock signal. The 4× over-sampler samples a serial data to generate a M-bit signal according to the plurality of multiplicative clock signals, wherein each bit in the serial data is sampled for four times. The data regenerator sequentially receives and combines two M-bit signals to generate a (M+N)-bit signal. The digital PLL divides the (M+N)-bit signal into (N+1) groups of M-bit data and selects a designated M-bit data from the (N+1) groups of M-bit data to generate a P-bit recovery data.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: November 6, 2012
    Assignee: Sunplus Technology Co., Ltd.
    Inventor: Chia-Hao Hsu
  • Patent number: 8248282
    Abstract: To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digital post-processing is prohibitive in high speed systems, indicating a need for blind mismatch compensation. Even with blind bandwidth mismatch estimation, though, adjustment of the filter characteristics of track-and-hold (T/H) circuits within the TI ADCs can be difficult. Here, a T/H circuit architecture is provided that uses variations of the gate voltage of a sampling switch (which varies the “on” resistance of the sampling switch) to change the bandwidth of the T/H circuits so as to precisely match the bandwidths.
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: August 21, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Robert F. Payne, Marco Corsi
  • Patent number: 8223057
    Abstract: A system and methods for synchronizing quantized sampled data in a monitoring device. A variable frequency output signal is coupled to an analog to digital converter. A fixed frequency clock is coupled to the analog to digital converter. The analog to digital converter samples the output signal at a fixed frequency to produce high speed samples. A group of initial high speed samples is stored from the analog to digital converter over a fixed window of time. The group of initial high speed samples is interpolated to produce a group of fewer low speed samples from the initial group of high speed samples over the fixed window of time. The group of low speed samples is stored as a representation of the variable frequency output signal.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: July 17, 2012
    Assignee: Schneider Electric USA, Inc.
    Inventors: Ronald W. Carter, Kurt H. Copley
  • Publication number: 20120176261
    Abstract: In a semiconductor integrated circuit, having a central processing unit, a clock generating unit, an A/D converter and a sample and hold signal generating circuit, noise from an element that operates in accordance with operation timing that is difficult to predict beforehand is reduced. In a calibration operation, in response to a clock signal from the clock generating unit, a sample and hold signal generating circuit supplies a plurality of clock signals sequentially to a sample and hold circuit of the A/D converter. By analyzing a plurality of digital signals that are sequentially output from an A/D conversion circuit of the A/D converter, a timing of a holding period for allowing A/D conversion under a low noise condition is selected from the clock signals. In normal operation, a clock signal selected by the calibration operation is supplied as a sample and hold control signal to the sample and hold circuit.
    Type: Application
    Filed: January 6, 2012
    Publication date: July 12, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshiyuki ISHIOKA, Takuji ASO
  • Patent number: 8217812
    Abstract: Techniques of this disclosure provide for adjustment of a conversion rate of a sampling rate converter (SRC) in real-time. The SRC determines relative timing of generated output samples based on non-approximated integer components that are recursively updated. The SRC may further base relative timing of output samples on a value of one or more step size components associated with the integer components. Also according to techniques of this disclosure, a conversion rate of an SRC may be adjusted in real-time based on a detected mismatch between a source clock of a digital input signal and a local clock.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: July 10, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Song Wang, Aris Balatsos
  • Patent number: 8164498
    Abstract: A system and method for clocking in analog-to-digital (ADC) converter in a synthetic instrument unit is presented. A method begins by applying an input clock to an amplifier to produce an amplified clock. The amplified clock is filtered to produce a filtered clock. The ADC of this synthetic instrument unit is clocked with the filtered clock. The input frequency of the ADC corresponds to a second or higher order Nyquist zone that is above the sampling frequency of the ADC. The input data is carried by an intermediate frequency (IF) signal. The filtered clock of ADC is switched off a clock path of the ADC when the ADC is not in use.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: April 24, 2012
    Assignee: BAE Systems Information Solutions Inc.
    Inventor: Anthony J. Estrada
  • Patent number: 8102959
    Abstract: A digital audio processing system includes an input to receive a phase component of a signal. The digital audio processing system includes symbol recognition logic to adjust a sample of the phase component using an offset value. The symbol recognition logic maps the adjusted sample to a nearest predetermined phase value of a plurality of predetermined phase values. The symbol recognition logic determines a symbol using a difference between the nearest predetermined phase value and a prior nearest predetermined phase value. The prior nearest predetermined phase value corresponds to a prior sample of the phase component of the signal. The offset value is based on a detected error of the prior sample of the phase component of the signal. The digital audio processing system also includes an output to provide a second signal that indicates the symbol.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: January 24, 2012
    Assignee: Sigmatel, Inc.
    Inventors: Jeffrey Donald Alderson, Darrell Tinker, K. Gozie Ifesinachukwu
  • Patent number: 7969337
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes an analog to digital converter, a digital interpolation circuit, a phase error circuit, and a phase adjustment control circuit. The analog to digital converter samples an analog data input at a sampling phase governed at least in part by a coarse control, and provides a series of digital samples. The digital interpolation circuit interpolates between a subset of the series of digital samples based at least in part on a fine control. The phase error circuit calculates a phase error value. The phase adjustment control circuit is operable to determine the coarse control and the fine control based at least in part on the phase error value.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: June 28, 2011
    Assignee: LSI Corporation
    Inventors: Nayak Ratnakar Aravind, James A. Bailey, Robert H. Leonowich
  • Patent number: 7953196
    Abstract: A method includes receiving first data corresponding to a first signal sampled at a first sample rate, decimating the first data to provide a second signal sampled at a second sample rate, and recovering a pilot signal from the second signal. The method also includes evaluating the pilot signal to determine an error value, where the error value is based on a comparison of a sample of the pilot signal to zero. The method also includes adjusting the second sample rate based on the error value.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: May 31, 2011
    Assignee: Sigmatel, Inc.
    Inventors: Jeffrey Donald Alderson, Darrell Tinker, K. Gozie Ifesinachukwu
  • Patent number: 7916053
    Abstract: Apparatus and methods are provided for performing a sampling sequence for a plurality of samples. An analog-to-digital conversion module comprises a sampling module, a register, and a sampling control module coupled to the sampling module and the register. The sampling module is configured to convert analog signals into corresponding digital values in response to sampling trigger signals and the register is configured to maintain scan mode criteria for a plurality of samples. The sampling control module is configured to identify a scan mode criterion for a respective sample of the plurality of samples, automatically generate a sampling trigger signal when the scan mode criterion for the respective sample is equal to a first value, and generate the sampling trigger signal in response to a timing trigger signal when the scan mode criterion for the respective sample is equal to a second value.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: March 29, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael E. Stanley, Mark A. Lancaster, Chongli Wu
  • Patent number: 7876251
    Abstract: A patient monitoring signal processing system adaptively varies medical signal data rate. The system uses an analog to digital converter for digitizing an analog cyclically varying input signal derived from a patient in response to a sampling clock input. The sampling clock determines frequency of analog to digital sampling of the analog input signal by the analog to digital converter. A detector detects first and second different signal portions within a cycle of the cyclically varying input signal.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: January 25, 2011
    Assignee: Siemens Medical Solutions USA, Inc.
    Inventor: Hongxuan Zhang
  • Patent number: 7843371
    Abstract: A method and apparatus for error avoidance in data transmission using dynamic modification of sampling rates. An embodiment of a method for transmission of data includes determining the transmission capacity for a transmission channel or channels. A sampling rate is selected based at least in part on the determined transmission capacity for the one or more transmission channels. An instruction, command, or information regarding the sampling rate is inserted in a data packet, and the data packet is transmitted.
    Type: Grant
    Filed: July 19, 2007
    Date of Patent: November 30, 2010
    Assignee: Sofaer Capital, Inc.
    Inventors: Stephen R. Rumbaugh, Gary M. Kolstoe
  • Patent number: 7837110
    Abstract: A point of sale terminal includes a microcontroller integrated circuit. In one aspect, a regulator within the IC receives power from a supply voltage terminal and/or a battery terminal. If the regulator does not receive adequate power from either terminal, then energy stored on-chip in a capacitor is used to erase secure memory. In another aspect, pulses of current are made to pulse through conductors of a conductive mesh. A tamper condition is detected if an improper voltage is detected on the IC terminal through which the pulse is conducted. In another aspect, each vendor signs his/her firmware with his own vendor ID. A bootloader uses the vendor ID to lookup a public key that is then used to verify a private key supplied by the firmware to be executed. In another aspect, a magnetic card reader includes a digital peak detector circuit involving programmable positive and negative thresholds.
    Type: Grant
    Filed: May 28, 2005
    Date of Patent: November 23, 2010
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Mark Hess, Raymond O. Chock
  • Patent number: 7831001
    Abstract: A digital audio processing system and method is disclosed. In an embodiment, the digital audio processing system can include a phase detector to sample an input signal and provide an output to adjust a decimation rate of an input signal. In another embodiment, the digital audio processing system can include symbol recognition logic to determine a symbol using a difference between a nearest predetermined phase value to a sample and a nearest predetermined phase value to a prior sample.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: November 9, 2010
    Assignee: Sigmatel, Inc.
    Inventors: Jeffrey Donald Alderson, Darrell Tinker, K. Gozie Ifesinachukwu