Abstract: A circuit comprising: a first passive mixer (21) having mixer inputs configured to receive in-phase (I) and quadrature-phase (Q) differential signals; and a first differential sub-circuit (31). The first passive mixer is configured to switch the in-phase (I) and quadrature-phase (Q) differential signals to the first differential sub-circuit at a mixing frequency. The first differential sub-circuit (31) has a pair of differential inputs configured to receive the switched in-phase (I) and quadrature-phase (Q) differential signals from the first passive mixer (21), each input having a capacitance capable of storing a charge that depends on the switched in-phase or quadrature-phase signals. The circuit further comprises a charge canceller configured to supply, to at least one of: the mixer inputs; and the pair of differential inputs, an opposite charge compared with a charge that has been stored on the pair of differential inputs by the operation of the first passive mixer.

Abstract: A method of incorporating Programmable Gain Amplifier (PGA) function into pipelined ADC for wide input range. The power consumption is saved without adding extra stage to reduce input range. The ADC input range can be adjusted on the fly using resistor bank and capacitor bank to achieve optimal system performance.

Abstract: Methods and systems are provided for generating an event reel based on spectator reaction data, the event reel is temporally synchronized to a music track. A method includes receiving a video file for video content and receiving spectator reaction data related to reactions generated by spectators while viewing the video content. The method includes processing the spectator reaction data to identify video time slices from the video content that correspond to segments of interest of the video content. The method includes processing a music track to identify markers for the music track that correspond to beats of the music track and generating an event reel having a video component defined by a sequence of the video time slices that is temporally synchronized to the markers of the music track.

Abstract: Provided herein are a semiconductor memory device and a method of operating the semiconductor memory device, which have an improved processing speed for a suspend operation. The semiconductor memory device includes a memory cell array, a peripheral circuit configured to perform a data operation corresponding to an externally provided command on the memory cell array and a control circuit configured to control the peripheral circuit to perform the data operation by sequentially executing instructions corresponding to a plurality of instruction lines of an operation algorithm for the data operation and, when a suspend command is provided during the data operation, to perform a preset suspend operation in any one of a checker mode and an instant mode.

Abstract: A two-step, hybrid analog-to-digital converter (ADC) includes a Delta-Sigma ADC that employs chopping to resolve MSBs, a Nyquist ADC that employs correlated double sampling (CDS) to resolve LSBs, and a combiner that combines the MSBs and the LSBs to generate a digital output signal. The Delta-Sigma ADC has first and second integrators where, after resolving the MSBs, the first integrator is re-configured to function as a reference buffer for the Nyquist ADC and the second integrator is re-configured to function as the Nyquist ADC.

Abstract: An apparatus to monitor and control a switching rate in a switch includes a differentiator circuit including a capacitor and a configurable resistor. The differentiator circuit further includes an input terminal of the capacitors configured to receive a first voltage from a switch and a differentiator node configured to receive a differentiated voltage based on the first voltage. The apparatus includes a peak detector circuit coupled to the differentiator node and configured to detect a peak value of the differentiated voltage. The apparatus further includes a driver circuit coupled to the peak detector circuit and configured to adjust a control signal to the switch responsive to the detected peak value of the differentiated voltage.

Abstract: Apparatus and associated methods relating to a digital-to-analog converter (DAC) include a programmable resistance network coupled between a voltage supply node VDD and a switch cell circuit to provide a predetermined resistance in response to the VDD and current IS of the switch cell circuit. In an illustrative example, the DAC may include a switch cell circuit comprising one or more switch cells connected in parallel. Each switch cell may include a differential gain circuit having a first branch coupled to a second branch at an input of a current source. The programmable resistance may include a variable resistance configured to adjust a voltage (Vbias) supplied to the switch cell circuit in response to a control signal. By introducing the programmable resistance network, predetermined bias and/or gain values may be dynamically adjusted with a constant board-level power supply VDD.

Abstract: An electronic device includes a display panel. The display panel includes a number of pixels, each of which includes a driving thin-film-transistor (TFT) and a light-emitting diode. Compensation circuitry external to the display panel applies offset data to pixel data for each pixel of the plurality of pixels before the pixel data is provided to the plurality of pixels.

Abstract: A differential digital-to-analog (DAC) circuit that can include a reservoir capacitor and various switches to couple the bottom plates of the input capacitors, e.g., bit-trial capacitors, to reference voltages, e.g., REF+ or REF?. In this manner, the reservoir capacitor can be used to provide any differential charge to the input capacitors, e.g., bit-trial capacitors, and the reference voltages, e.g., REF+ and REF?, can be used to provide any common mode charge to the input capacitors.

Abstract: A computing system can be arranged to generate a range of different frequencies with at least one oscillator of a clock module prior to providing a first clock frequency to a controller with a channel selector of the clock module in response to a dither control circuit. A system operation may be executed with the controller before the first clock frequency is changed to a second clock frequency during the execution of the system operation as directed by the dither control circuit. The second clock frequency can be chosen from the range of different frequencies. The computing system may return to the first clock frequency at the conclusion of the execution of the system operation.

Abstract: A conversion time and an acquisition time of an ADC can be estimated so that a speed of the ADC can be calibrated. An ADC circuit can perform M bit-trials in its conversion phase and continue performing additional bit-trials in a calibration mode. The ADC can count the number of additional bit-trials performed, e.g., X bit-trials, that occur before the next conversion phase, where additional bit-trials can be considered to be the number of available bit-trials during an acquisition time if the ADC continues performing bit-trials instead of sampling an input signal. The ADC can estimate the conversion time and the acquisition time using M and X. Then, the conversion time of the ADC can be calibrated by adjusting one or more of the comparison time, DAC settling delay, and logic propagation delay.

Abstract: A dielectric resonator oscillator includes a dielectric resonator; a transmission line disposed adjacent the dielectric resonator; an active device having an input electrically connected to the transmission line; a matching network having an input electrically connected to an output of the active device and an output configured to be connected to a load; wherein both the transmission line and the active device are positioned sufficiently close to the dielectric resonator to form part of a resonant circuit with the dielectric resonator.

Abstract: Techniques to provide automatic-gain ranging for high dynamic range by including a separate S/H capacitor, segmenting the S/H capacitor into a plurality of capacitors, and determining the number of segments to use for a sample. In this manner, the size of the S/H capacitor can be changed (by adjusting the number of capacitors), which can change the amount of input voltage that produces an amount of charge. Using these techniques, the full-scale input range for a sample of the analog input signal can be adjusted automatically based on the magnitude of the sample, which can provide better resolution and/or better noise performance for that particular sample then would otherwise be possible.

Abstract: This disclosure relates to data converters for electronic systems. An example system includes a primary analog to digital converter (ADC) circuit, a slope calculation circuit, a digital phase lock loop (DPLL) circuit, a sampling error circuit, and a summing circuit. The primary ADC circuit samples an input signal and produces a digital output signal representative of the input signal. The slope calculation circuit generates a digital slope signal representative of slope of the input signal, and the DPLL circuit provides a sampling clock signal to the primary ADC circuit. The sampling error circuit generates a sampling error signal representative of sampling error by the primary ADC circuit using the digital slope signal and the sampling clock signal. The summing circuit receives the sampling error signal and the digital output signal of the primary ADC circuit and generates an adjusted digital output signal representative of the input signal.

Abstract: A semiconductor device having a novel structure is provided. Fluctuation in the grayscale voltage due to an offset voltage is suppressed. When a current corresponding to a lower-bit grayscale voltage is generated in a transconductance amplifier, voltages VHI and VLO supplied to the transconductance amplifier are alternately input to two input terminals in accordance with a digital signal of the most significant bit of lower bits. Since a change corresponding to the offset voltage is added to both the maximum and minimum values of the current output from the transconductance amplifier, fluctuation in the grayscale voltage due to the offset voltage can be suppressed.

Abstract: A sample and hold (S/H) circuit includes a capacitor coupling a sample node to a first voltage and an input line carrying a signal from an input. The S/H circuit also can include one or more transistors coupling the input line to the sample node. The S/H circuit also can include a switch coupled to one or more sources or drains of the one or more transistors and to a second voltage. The S/H circuit also can include a hold circuit coupled to the switch and to one or more gates of the one or more transistors, the hold circuit configured to open, during a sample period, the input line between the input and the sample node.

Abstract: A novel non-uniform sampling technique for a burst type signal. The analog signal is digitized with high sampling rate to maintain harmonics at higher frequencies and consequently the integrity of the analog signal. Then by using non-uniform sampling technique the most significant samples are selected for further processing which results in overall cost and power consumption reduction.

Abstract: Systems and methods for tracking dynamic structure in physiological data are provided. In some aspects, the method includes providing physiological data, including electroencephalogram (“EEG”) data, acquired from a subject and assembling a time-frequency representation of signals from the physiological data. The method also includes generating a dynamic model of at least one non-stationary spectral feature, such as at least one non-stationary spectral peak, using the time-frequency representation and a user indication, and applying a dynamic model of at least one non-stationary spectral feature in a parameter estimation algorithm to compute concurrent estimates of spectral parameters describing the at least one non-stationary spectral feature. The method also includes tracking the spectral parameters of the at least one spectral feature over time.

Abstract: A voltage sampling circuit and method are provided. The voltage sampling circuit includes a capacitor having a first terminal and a second terminal. A first pre-charge circuit is coupled to a first voltage supply terminal and to the first terminal of the capacitor. The first pre-charge circuit is configured to receive a first control signal and pre-charge the capacitor to a first voltage. A switch circuit includes a first transistor having a first current electrode coupled to an input terminal of the voltage sampling circuit, a control electrode coupled to the first terminal of the capacitor, and a body electrode coupled to the second terminal of the capacitor. A second transistor having a first current electrode coupled to a second current electrode of the first transistor, a body electrode coupled to the second terminal of the capacitor, and a second current electrode coupled to an output terminal of the voltage sampling circuit.

Abstract: Methods and systems for generating a digital representation of the amplitude and phase of a bandpass signal are disclosed. The methods comprise filtering the bandpass signal with a bandpass filter, generating the real and imaginary parts of the complex analytic signal with a quadrature hybrid, determining the amplitude of the complex analytic signal by adding an even power-law transform of the real and imaginary parts of the complex analytic signal, and determining the phase of the complex analytic signal by comparing the real and imaginary parts of the complex analytic signal to zero and comparing an even power-law transform of the real and imaginary parts of the complex analytic signal to each other. Analog to digital converters and methods of converting complex analytic signals to digital signals are also disclosed.

Abstract: This application discloses an implementation of a novel non-uniform sampling technique for a burst type signal. A simple circuit is developed that implements an analog computation of a complex digital calculation to skip the unnecessary samples and choose the optimum next sample. Then the optimum samples are selected for further processing which results in overall cost and power consumption reduction.

Abstract: A digital-to-analog converter performs a ?? computation process to start the ?? computation based upon the second clock signal with respect to the digital data of music sound if the ?? computation is not under execution when the control signal is outputted by the signal output process, a control process to inhibit the ?? computation based upon the second clock signal from being started with respect to the digital data of music sound until the ?? computation is not under execution when the ?? computation is under execution, and an output process to convert a computation result of the ?? computation process into an analog signal and output the analog signal.

Abstract: A sampling device samples a differential measuring voltage. The sampling device comprises a first holding device, a second holding device and a multiplexing circuit, which is configured to provide a differential sample of a sampled differential signal, derived from the differential measuring voltage by sampling with a first clock signal of a first clock rate, to the first holding device, at the occurrence of each HIGH-value of a second clock signal of a second clock rate being half of the first clock rate and provide a differential sample of the sample differential signal to the second holding device, at each LOW-value of the second clock signal. The sampling device comprises a reset device configured to reset the second holding device at or after each HIGH-value of the second clock signal and reset the first holding device at or after each LOW-value of the second clock signal.

Abstract: A data driver capable of displaying images with a substantially uniform brightness, an organic light emitting display device using the same, and a method of driving the organic light emitting display device. The data driver includes a plurality of current sink units for controlling predetermined currents to flow through data lines, a plurality of voltage generators for resetting values of gray scale voltages using compensation voltages generated when the predetermined currents flow, a plurality of digital-to-analog converters for selecting one gray scale voltage among the gray scale voltages as a data signal in response to bit values of the data supplied from the outside, and a plurality of switching units for supplying the data signal to the data lines. The predetermined currents may be set equal to pixel currents that correspond to a maximum brightness.

Abstract: Ingress noise from subscriber equipment is mitigated or prevented from reaching a cable television (CATV) network. All upstream signals including ingress noise are initially transmitted to the CATV network whenever their instantaneous power exceeds a threshold which typically distinguishes ingress noise from a valid upstream signal. Whenever the instantaneous power is below the threshold, ingress noise is blocked from reaching the CATV network. A gas tube surge protection device is included to resist component destruction and malfunction arising from lightning strikes and other high voltage, high current surges.

Abstract: Methods and systems for generating a digital representation of the amplitude and phase of a bandpass signal are disclosed. The methods comprise filtering the bandpass signal with a bandpass filter, generating the real and imaginary parts of the complex analytic signal with a quadrature hybrid, determining the amplitude of the complex analytic signal by adding an even power-law transform of the real and imaginary parts of the complex analytic signal, and determining the phase of the complex analytic signal by comparing the real and imaginary parts of the complex analytic signal to zero and comparing an even power-law transform of the real and imaginary parts of the complex analytic signal to each other. Analog to digital converters and methods of converting complex analytic signals to digital signals are also disclosed.

Abstract: Vibration gyroscope circuitry, connectable to a vibrating MEMS gyroscope, includes drive circuitry for driving the gyroscope and a measurement circuit for providing a drive measurement signal indicating displacement of a mass along a drive axis. Sense circuitry processes a sense measurement signal of the gyroscope indicating displacement of the mass along a sense axis. A digital sample clock generator includes an oscillator for generating a master clock, a counter for counting master clock periods during one period of an input signal derived from the drive measurement signal, and a number count monitor for determining during how many input signal periods the number count stays constant and for comparing a number of constant periods with a critical number of constant periods. A frequency shifter triggers the oscillator to shift the master clock frequency whenever the monitor determines that the number of constant periods exceeds the critical number of constant periods.

Abstract: A physical quantity detection device includes a switched capacitor filter circuit having a first sample-and-hold circuit adapted to sample and hold a first signal, which is based on an output signal of a physical quantity detection element, an amplifier circuit to which an output signal of the first sample-and-hold circuit is input, and a first switched capacitor circuit to which a first output signal of the amplifier circuit is input, wherein an output signal of the first switched capacitor circuit is input to the amplifier circuit, and an A/D conversion circuit adapted to perform an A/D conversion on an output signal of the switched capacitor filter circuit.

Abstract: This disclosure provides systems, methods, and apparatus, including computer programs encoded on computer storage media, for contemporaneously estimating transmitter in-phase and quadrature (I/Q) imbalances, receiver I/Q imbalances, and transmit carrier leakage in a wireless transceiver. In some implementations, first, second, and third frequency-domain multi-tone (FDMT) signals transmitted through a calibration path of the wireless transceiver are captured to generate frequency domain representations of the first, second, and third FDMT signals. The frequency domain representations of the first, second, and third FDMT signals may be used to contemporaneously estimate the transmitter I/Q imbalances, receiver I/Q imbalances, and the transmit carrier leakage, which in turn may be used to determine transmitter and receiver I/Q imbalance correction filter coefficients and a transmit carrier leakage correction factor.

Abstract: A system and method for digitizing data from an imaging system includes sampling a signal from an optical detector with a first circuit having a first attenuation and with a second circuit having a second attenuation different than the first attenuation. The system and method further includes digitizing the sampled signal at a predetermined number of bits desired for an analog to digital conversion of the sampled signal by allocating a first portion of bits to digitizing a signal from the first circuit and allocating a second portion of bits to digitizing a signal from the second circuit. The system and method further includes encoding the first and second portion of bits into one monotonic digital word corresponding to a range of the sampled signal.

Abstract: The invention relates to encapsulating scalable tiled timed media data comprising timed samples in a server and providing a timed media data bit-stream from encapsulated scalable tiled timed media in a client device. Each timed sample comprises a first layer and at least one second layer and at least one of the layers comprises a plurality of subsamples represented by one or more coding units. After having obtained at least one subsample from amongst the plurality of subsamples of one of the timed samples, one track comprising the at least one obtained subsample is created. Next, the created track is independently encapsulated in at least one media segment file, said media segment file comprising mapping metadata for providing information about the at least one obtained subsample relative to the one of the timed samples and the layer it belongs to.

Abstract: A charge sharing filter includes a rotating capacitor, and a plurality of elementary filters, each elementary filter comprising: an elementary switch coupled between a first node of the respective elementary filter and a second node of the respective elementary filter; and a history capacitor coupled to the first node of the respective elementary filter, wherein the second nodes of the plurality of elementary filters are interconnected with the rotating capacitor in one interconnecting node.

Abstract: A method for reducing the jitter introduced into a digital signal by a non-linear processing element involves applying an input word representing the digital signal to a first signal path comprising a first non-linear processing element, and a complementary version of the input word to a second signal path comprising a second non-linear processing element. A common mode dither signal is injected into each signal path upstream of the non-linear processing elements. The outputs of the non-linear processing elements are combined to produce a common output with the common mode dither signal removed.

Abstract: Methods, systems and devices for dynamically controlling resolution of an analog-to-digital converter (ADC). The ADC receives an analog input signal and outputs digital data. A statistical unit coupled to the ADC obtains samples of the output signal and transmits a control signal to the ADC to adjust the resolution of the ADC. The control signal is generated by the statistical unit based on a comparison of at least one performance indicator with a target performance level. The at least one performance indicator is calculated using the samples.

Abstract: The present disclosure describes a channel selector for use in an analog-to-digital converter that has a sampling circuit for converting an analog input to a digital output within a fault tolerance range. The channel selector includes a reception channel, a diagnostic channel, and an impedance compensator. The reception channel receives an analog signal for delivery to the sampling circuit when it is selected for coupling with the sampling circuit. The diagnostic channel receives a diagnostic signal for verifying the digital output of the sampling circuit when it is selected for coupling with the sampling circuit. The impedance compensator is configured to offset a high channel impedance of the reception channel based on the fault tolerance range of the sampling circuit and when the diagnostic channel is selected.

Abstract: A method for pre-loading a SAR ADC with an initial value for a selected range of high-order bits. If the ADC resolves at either an upper or a lower limit set by the pre-loaded value, the ADC may discard the pre-loaded value and perform a full search. Alternatively, the ADC may perform one or more “bonus steps” before giving up and performing a full search.

Abstract: Methods and systems for frequency generation may comprise a circuit with a first input coupled to receive a first satellite signal at a first satellite downlink frequency, a second input coupled to receive a second satellite signal at a second satellite downlink frequency, and a first analog-to-digital converter (ADC) having an input coupled to receive the first satellite signal. The first ADC may be configured to create a first digital output signal representing the first satellite signal. A second ADC having an input coupled to receive the second satellite signal may be configured to create a second digital output representing the second satellite signal. The circuit may comprise a dielectric resonator oscillator having an output and a clock generator circuit having an input coupled to the oscillator output and configured to output one or more clocks used by the first and second ADCs.

Abstract: A solid-state imaging apparatus of this invention includes an output unit that outputs an analog signal, and an offset addition unit that, in a case where the analog signal is out of a range in which A/D conversion is possible in the A/D conversion unit, adds an offset to the analog signal in the output unit so that the analog signal is not out of the range in which A/D conversion is possible.

Abstract: A phase angle can be measured between an analog signal and a reference signal by converting the analog signal to digital samples in a residue number system (RNS) analog-to-digital converter (ADC), based on a RNS scheme. The phase angle can be measured directly from the RNS values output by the RNS ADC, or the RNS values can be converted to a binary scheme, such as straight binary, offset binary or two's complement, before calculating the phase angle measurement.

Abstract: A successive comparison A/D conversion circuit includes: an comparison circuit including a differential amplification circuit which includes a pair of differential input terminals, amplifies a pair of first differential signals input into the pair of differential input terminals, and outputs a pair of second differential signals, and a latch circuit which compares voltages of the second differential signals output from the differential amplification circuit, retains an comparison result, and outputs the retained comparison result; a digital circuit which generates a digital signal corresponding to the first differential signal, based on the comparison result; an arithmetic circuit which generates a reference signal based on the digital signal, generates the first differential signal by subtracting the reference signal from a third differential signal or adding the reference signal to the third differential signal, and outputs the generated first differential signal to the pair of differential input terminals;

Abstract: Reduced noise and power with rapid settling time and increased performance in multi-modal analog multiplexed data acquisition systems. An example apparatus arrangement includes a circuit input configured to receive a plurality of analog input signals; an analog to digital converter circuit configured to output a digital representation of an analog voltage; a selection circuit configured to select one of the analog input signals received at the circuit input; a buffer coupled to receive the selected one of the analog input signals; a filter coupled to the buffer and configured to perform a high bandwidth sample operation and a low bandwidth sample operation and having a filter output, responsive to a control signal; and a sampling capacitor coupled to the filter to sample the filter output, and having an output coupled to the analog to digital converter. Methods and additional apparatus arrangements are disclosed.

Abstract: In one aspect, a buffer circuit comprises a source or emitter follower input stage and output stage. A load is provided between the stages which comprises a representation of an output load of the buffer circuit. This improves the circuit linearity whilst enabling a high input impedance to be obtained. In another aspect, a buffer circuit comprises a source or emitter follower output stage. A load is in the form of a filter is provided and which comprises a representation of an output load of the buffer circuit.

Abstract: An analog-to-digital conversion device for multiple input signals includes a sample-and-hold amplifier and an analog-to-digital converter for converting an analog signal output from the sample-and-hold amplifier into a digital signal. According to the analog-to-digital conversion device for multiple input signals and a conversion method therefor, even if an input buffer is not provided, the dynamic range of the analog-to-digital converter may be optimally set depending on the input signals, and current consumption may be reduced.

Abstract: A system for measuring electrical signals in a biological subject includes a variable gain amplifier with a predetermined transfer function that generates amplified signals corresponding to an input from electrical signals in the biological subject over a predetermined range of frequencies and amplification gain levels, an analog to digital converter generating digital data corresponding to the amplified signals, and a signal processing device receiving the digital data for the plurality of amplified signals. The signal processing device applies an inversion filter with another transfer function that is an inverse of the transfer function of the variable gain amplifier to remove an effect of the transfer function from the digital data, and generates an output signal corresponding to the electrical signals in the subject with reference to the filtered digital data.

Abstract: A quasi-resonance switching power supply quickly determines the number of bottom skips corresponding to the load condition even in abrupt load change. The quasi-resonance switching power supply is provided with a bottom skipping control function and a capacitor to hold a voltage corresponding to the load condition of the switching element over one switching period of the switching element. The quasi-resonance switching power supply comprises a bottom skipping number determining circuit that compares the voltage held on the capacitor with comparison reference voltages selected from a plurality of reference voltages for determining the number of bottom skips, and revises the comparison reference voltage according to the comparison result. The processing of comparison and revision is executed multiple times in one switching period of the switching element. Thus, the bottom skipping number determining circuit determines the number of bottom skips corresponding to the voltage held on the capacitor.

Abstract: Methods and systems for frequency generation may comprise a circuit with a first input coupled to receive a first satellite signal at a first satellite downlink frequency, a second input coupled to receive a second satellite signal at a second satellite downlink frequency, and a first analog-to-digital converter (ADC) having an input coupled to receive the first satellite signal and an output. The first ADC may be configured to create a first digital output signal representing the first satellite signal. A second ADC having an input coupled to receive the second satellite signal and an output may be configured to create a second digital output representing the second satellite signal. The circuit may comprise a dielectric resonator oscillator having an output and a clock generator circuit having an input coupled to the oscillator output and configured to output one or more clocks used by the first and second ADCs.

Abstract: Embodiments presented herein describe a method, a system and a computer program product for ultrasound imaging. The method in one example includes receiving a plurality of ultrasound echo signals from a plurality of transducer elements in response to ultrasound transmit beams. The method computes beam sums of ultrasound echo signals originating from a point to be imaged, for the corresponding ultrasound transmit beams. The method generates a time record comprising a plurality of beam sums, wherein the time record includes beam sums corresponding to multiple instants of time in a time window. The method filters the time record based, at least in part, on a predetermined response function. Finally, the method reconstructs the point to be imaged based on one or more of the filtered time records corresponding to one or more of the plurality of ultrasound transmit beams. The method repeats this process for each point to be imaged.

Abstract: Presented herein are novel shared amplifier charge mode readout architectures for image sensors, for example, configured to process a pair of signals comprising photointegration and reset signals from a pixel. The invention encompasses a novel 2-channel configuration wherein a single amplifier can serve the two channels in alternating phases. In the first phase, a selected pair of signals from the first channel is read out to an ADC using the amplifier while the readout components of the second channel are reset. In the second phase, a selected pair of signals from the second channel is read out an ADC using the amplifier while the readout components of the first channel are reset. This alternating arrangement allows a single amplifier to be shared between two readout channels. Level shifting may be included in the signal pathway to modulate output swing and other signal parameters.

Abstract: The present disclosure describes a channel selector for use in an analog-to-digital converter that has a sampling circuit for converting an analog input to a digital output within a fault tolerance range. The channel selector includes a reception channel, a diagnostic channel, and an impedance compensator. The reception channel receives an analog signal for delivery to the sampling circuit when it is selected for coupling with the sampling circuit. The diagnostic channel receives a diagnostic signal for verifying the digital output of the sampling circuit when it is selected for coupling with the sampling circuit. The impedance compensator is configured to offset a high channel impedance of the reception channel based on the fault tolerance range of the sampling circuit and when the diagnostic channel is selected.

Abstract: An A/D converter includes: plural comparators to which reference voltages as ramp waves different from each other are supplied, which are configured to compare the supplied reference voltages with an analog input signal; and plural latches arranged so as to correspond to the plural comparators, which are configured to count comparison time of the corresponding comparators, to stop counting when an outputs of the comparator is inverted and to store the count value, wherein the plural reference voltages are off set by an arbitrary voltage at the same time point.