Abstract: A system and a method are provided for receiving analog and digital audio input via a single audio input connector. The method includes receiving an input signal from a single audio input connector, splitting the received input signal into a first input signal and a second input signal, filtering the first input signal to pass a digital signal, filtering the second input signal to pass an analog signal, digitizing the filtered analog signal, and multiplexing the filtered digital signal and the filtered digitized analog signal.

Abstract: Provided are a multiplexer for controlling a data output sequence and a parallel-to-serial converter using the multiplexer. The multiplexer is configured to simply control the output sequence of input data in accordance with a value of a selection signal. The parallel-to-serial converter with the multiplexer can easily control an output bit sequence of serial data without altering an interconnection structure of parallel data signal lines.

Abstract: An inverter system includes a comparator unit receiving an analog input voltage signal and compared with at least one threshold voltage value to determine a voltage range of the analog input voltage signal. An amplifier unit receives and amplifies the analog input voltage signal. A feedback-controlling gain unit adjusts a voltage gain of the amplifier unit according to the voltage range of the analog input voltage signal. An analog-to-digital converter unit converts an analog signal outputted from the amplifier unit into a digital count. A microcontroller unit is electrically connected with the analog-to-digital converter unit and the comparator unit. The microcontroller unit receives an indicating signal outputted from the comparator unit to know the voltage range of the analog input voltage signal. The microcontroller unit receives a digital count outputted from the analog-to-digital converter unit to correctly calculate an original value of the analog input voltage signal.

Abstract: A system and a method are provided for receiving analog and digital audio input via a single audio input connector. The method includes receiving an input signal from a single audio input connector, splitting the received input signal into a first input signal and a second input signal, filtering the first input signal to pass a digital signal, filtering the second input signal to pass an analog signal, digitizing the filtered analog signal, and multiplexing the filtered digital signal and the filtered digitized analog signal.

Abstract: A modulator described herein provides digital modulation and direct digital-to-analog conversion capable of achieving 12-bit resolution or higher for high frequency signals. The modulator comprises a digital modulator, conversion circuit, and multiplexer. The digital modulator generates a plurality of sample streams at a plurality of different sample phases that collectively represent a desired modulated digital carrier waveform modulated by a digital input signal. The conversion circuit converts the sample streams into a plurality of continuous analog signals. The multiplexer multiplexes the analog signals together to generate a modulated analog carrier signal representative of the desired modulated digital carrier waveform.

Abstract: The present invention is a programmable Analog to Digital Converter (ADC) unit (200) that includes an analog to digital converter (204), which includes one or more analog inputs (202). The unit (200) additionally includes a control/status register block (216). The unit 200 further includes a FIFO register block (206) with a first, second, third, and fourth FIFO conversion register. Further included is a programmable sequencer (300) that includes a first (208), second (210), third (212), and fourth (214) programmable sample sequencer. And further, the unit (200) includes a first (226), second (228), third (230), and fourth (232) trigger event control multiplexer, where each trigger event control multiplexer corresponds to each programmable sample sequencer.

Abstract: There is provided a demodulator system comprising a first input to receive a first analog signal at a first rate; a second input to receive a second analog signal at the first rate; a MUX coupled to the first input and the second input to receive the first analog signal and the second analog signal, and to multiplex the first analog signal and the second analog signal to generate a multiplexed analog output; an ADC to receive the multiplexed analog output and generate a multiplexed digital output, the ADC operating at a second rate, the second rate substantially equal to the first rate multiplied by a total number of input analog signals; a DEMUX to receive the multiplexed digital output and generate a first digital output having a first bitstream and a second digital output having a second bitstream corresponding to the first analog signal and the second analog signal.

Abstract: A system comprising an radio frequency (RF) signal input; a plurality of time-skewed, undersampled analog to digital converters (ADCs); a plurality of complex finite input response (FIR) filters in parallel, wherein each complex FIR filter receives the output beam and/or band provided by the plurality of ADCs and generates a corresponding output beam of a given frequency.

Abstract: A coder-decoder simultaneously processing a plurality of first analog signals with only one analog-to-digital converter is provided. In an exemplary embodiment, the coder-decoder comprises a multiple access modulator, the analog-to-digital converter, and a multiple access demodulator. The multiple access modulator combines the first analog signals according to a multiple access algorithm to obtain a first multiple access signal comprising the first analog signals. The analog-to-digital converter then converts the first multiple access signal from analog to digital to obtain a second multiple access signal. The multiple access demodulator then separates the second multiple access signal according to the multiple access algorithm to obtain a plurality of first digital signals respectively corresponding to the first analog signals.

Abstract: A flash ADC in which different thresholds are provided to different comparators in different time instances. Such a feature may be advantageously used in digital converters type components since the flash ADC would provide more time for amplifiers to generate amplified residue signals.

Abstract: In an analog-to-digital converter used to convert and store in buffer registers signals from a plurality of peripheral devices, a mode is provided wherein, for selected peripherals, the most recent converted signal overlays the previously stored signal in the buffer registers.

Abstract: In an integrated circuit including a first multibit digital-to-analog converter and a second multibit digital-to-analog converter, a calibration circuit is provided which is shared between the first and second digital-to-analog converters.

Abstract: A system and method are disclosed for providing an ultra low power scalable digital-to-analog converter architecture. Refresh buffer circuits are provided to buffer a voltage reference resistor string. The refresh buffer circuits may be coupled to the resistor string at selected binary fold points. The refresh buffer circuits can reduce the output impedance of the resistor string. Also, each digital-to-analog converter channel can be provided with a multi-dimensional multiplexer that minimizes settling time. The number of refresh buffer circuits and the number of dimensions of the multiplexer can be selected to maximize circuit performance for a given load capacitance and bit rate of the digital-to-analog converter.

Abstract: A sigma-delta modulator can be used for actuating a sensor element. The sigma delta modulator includes: a forward branch to which an input signal is fed at an input and which includes a loop filter, a quantizer and an output for providing an output signal. A feedback branch is configured to feed back the output signal of the forward branch at least temporarily to the input of the forward branch. A signal source is configured to generate a readout signal which corresponds to the voltage profile at the sensor element during a measuring process. A control unit is configured to generate a control signal dependent on which either the output signal of the forward branch or the readout signal of the signal source is fed back to the input of the forward branch.

Abstract: An integrated multi-mode sensor system is described that integrates into a single housing a sensor, signal conditioning circuitry, calibration memory, and interface circuitry that is compatible with both analog and digital end-use circuits. The sensor includes a housing, a sensor circuit, memory, and an interface circuit. The sensor circuit is disposed within the sensor housing, is operable, upon being energized, to supply an output signal that varies with at least one physical parameter to which the sensor circuit is exposed. The interface circuitry disposed within the sensor housing is adapted to receive a mode select signal and the sensor signal. The output circuit is selectively configurable, in response to the mode select signal, to implement one of a plurality of signal processing modes, including analog voltage output, asynchronous pulse density modulation (APDM) and synchronous pulse density modulation (SPDM) of various moduli, and an APDM or SPDM mode using a selectable I2C or SPI interface protocol.

Abstract: An arrangement for a time interleaved analog-to-digital converter that converts an signal to a digital signal and has a converter array with a plurality of analog-to-digital converters arranged in a fixed sequence in parallel with one another and can be operated with staggered timing with respect to one another is disclosed. The arrangement has a connection network which, for the purposes of actuation with staggered timing, generates in each case one control signal for an individual analog-to-digital converter in each case, with the connection network predefining the time sequence with which the control signals actuate the individual analog-to-digital converters in such a way that owing to this sequence of the control signals and thus the sequence of the actuated individual analog-to-digital converters there is at least a reduction in an interference spectrum in the spectrum of the input and/or output signal. A sorting method for operating this analog-to-digital converter is also disclosed.

Abstract: An A/D conversion apparatus performs motor current detection in an A/D conversion period corresponding to two phases out of three phases of a sinusoidal drive motor, using reduced register resources while minimizing the number of A/D converters. The A/D conversion apparatus includes: a selection unit selecting one of a plurality of input channels; an A/D converter converting an analog signal from the selected input channel to a digital signal; a start register holding a start channel number of sequential conversion; an end register holding an end channel number of the sequential conversion; a prohibition information holding unit holding prohibition information indicating an input channel to be excluded from the sequential conversion; and a control unit causing the selection unit to select, in channel number order, input channels corresponding to channel numbers from the start channel number to the end channel number except the input channel indicated by the prohibition information.

Abstract: A method and apparatus for compensating for gain offset, bias offset, and skew in a parallel processing environment is disclosed. The method and apparatus may be configured to compensate for mismatches between the sub-channel signals in a parallel ADC. This allows for accurate combination of the signals on the sub-channels. The method and apparatus may be utilized in a high speed data communication system having two or more channels, each of which are interleaved into two or more sub-channels. In one embodiment a DC loop processes signals on two or more sub-channels to account for and remove unwanted bias offset. In one embodiment a sub-channel gain mismatch compensation system (SCGMC) processes signals on two or more sub-channels to account for and remove unwanted gain offset. In one embodiment a skew compensation system, such as a parallel interpolator, processes signals on two or more sub-channels to remove unwanted skew across sub-channels.

Abstract: In order to convert a complex analog signal into a complex digital signal in an analog-digital conversion device having two channels, I and Q respectively, in quadrature, each comprising an input and an associated output, each output being fed back onto said associated input so as to form a first and a second feedback loops each comprising a digital-analog converter, the device comprising a complex filter with a first stage and a last stage, after sampling (508), a signal integration is performed in a first stage (501) of the filter without introducing any substantial delay. Then, an integration is performed in the last stage (502) of the filter. A substantial delay (507) is then introduced and the output signal of the last stage is converted into a digital signal over several bits. The digital signal is injected into the feedback loop (108) of said channel and the digital signal is converted into a feedback signal.

Abstract: A method and apparatus are disclosed for generating multiple separate analog signals using a single microcontroller output pin. The microcontroller generates a waveform that is used to concurrently generate multiple separate analog signals. The microcontroller outputs a waveform that includes a first signal from one of the microcontroller's output pins. The first signal is used to produce a first analog signal. The microcontroller then outputs a delineating signal, as part of the waveform, from the microcontroller's output pin. The delineating signal indicates the start of a next signal in the waveform. The microcontroller then outputs a second signal, as part of the waveform, from its output pin. The second signal is used to produce a second analog signal. The waveform includes the first signal that is followed by the delineating signal that is followed by the second signal.

Abstract: A transmit path in a physical layer device comprises a first transmit encoding device that has N outputs, that receives a first data stream at a first data rate and that performs a first type of encoding on the first data stream. A second transmit encoding device has an output, receives a second data stream at a second data rate and performs a second type of encoding on the second data stream. The first data rate is N times the second data rate. An output selector has a first set of N inputs that communicates with the N outputs of the first transmit encoding device, a second set of N inputs that communicate with the output of the second transmit encoding device and N outputs. The output selector selectively connects one of the first and second sets of N inputs to the N outputs.

Abstract: A method for operating a signal converter, and a signal converter is disclosed. One embodiment has at least one register and a plurality of input channels, wherein information stored in the register is variably assignable to at least one of the plurality of input channels by one or a plurality of corresponding assignment bits.

Abstract: An A/D converter capable of generating an interrupt for requesting a control circuit to read the results of A/D conversion, in desired timing. Analog signals input from channels selected by a channel-selecting section are input to an A/D conversion section, and are sequentially A/D-converted. The results of A/D conversion are sequentially stored in different stages of a FIFO. A stage number-counting section counts the number of the stages of the FIFO where the results of A/D conversion are stored. An interrupt signal-delivering section outputs an interrupt signal for requesting a CPU to read the results of A/D conversion when the number of stages counted by the stage number-counting section is equal to an interrupt-generating stage number set by an interrupt-generating stage number-setting section.

Abstract: A reconfigurable signal processor receives continuously changing signal elements for analyzing signal patterns through a conversion process further defined by a coarse sample reference and a fine sample reference. Receiving the plurality of signal elements to produce raw data status representing specific signal elements, the coarse sample reference is used to sub-divide raw data patterns into a predetermined number of equal parts. The fine sample reference is used to define specific variations or gaps between the predetermined number of equal sub-divided parts for data patterns to trigger status updates in a bit-mapped memory array with a bit pattern mutually exclusive of logic one bit states. A decoder is used to convert sub-divided data patterns into a digital bit pattern of mutually exclusive logic one states which is stored in the memory away when triggered by specific variations or gaps between the predetermined number of equal sub-divided parts for signal data patterns.

Abstract: The present invention is a programmable Analog to Digital Converter (ADC) unit (200) that includes an analog to digital converter (204), which includes one or more analog inputs (202). The unit (200) additionally includes a control/status register block (216). The unit 200 further includes a FIFO register block (20)6 with a first, second, third, and fourth FIFO conversion register. Further included is a programmable sequencer (300) that includes a first (208), second (210), third (212), and fourth (214) programmable sample sequencer And further, the unit (200) includes a first (226), second (228), third (230), and fourth (232) trigger event control multiplexer, where each trigger event control multiplexer corresponds to each programmable sample sequencer.

Abstract: An analog-to-digital converter based on an interleaving architecture is disclosed. The analog-to-digital converter can include a first sample and hold circuit for sampling and temporarily storing a first input signal. The analog-to-digital converter can also include a comparator for converting the sampled first input signal into a digital signal in a first time period. The analog-to-digital converter can further include a second sample and hold circuit for sampling and temporarily storing a second input signal in a second time period. The second time period at least partially overlaps with the first time period.

Abstract: Provided are an apparatus and method for processing analog monitoring signals by using a serial bus. The apparatus includes a multiplexer receiving at least one analog signal and outputting only one of the at least one analog signal in response to a predetermined control signal; an analog-to-digital converter converting the output analog signal into a digital signal; a first controller generating the control signal, outputting the control signal to the multiplexer, and controlling the operation of the analog-to-digital converter; and a bus controller outputting the digital signal via an external serial bus. Accordingly, analog monitoring signals are received, converted into digital data, and output via serial bus even when a large number of analog monitoring signals are present, only if the address input to the apparatus is identical to unique address of the apparatus.

Abstract: A mixed signal device having an analog-to-digital converter (ADC) with offset and gain calibration using internal voltage references whereby the digital processor calibrates out offset and gain errors in the analog-to-digital converter by adjusting the analog input amplifier gain and offset or with software compensating the digital representations of the voltages measured. Two different known voltage values are used in determining the offset and gain adjustments needed to calibrate the ADC against the two know voltage values. The mixed signal device may further comprise a Bandgap voltage reference having an accurate known voltage value. Wherein the Bandgap voltage reference may be used for further offset and gain calibration of the ADC to produce substantially absolute voltage values.

Abstract: An apparatus and method for providing an analog-to-digital converter (ADC) in programmable logic devices is disclosed. A plurality of multi-purpose input/output (I/O) blocks is configured to provide analog-to-digital conversion and other I/O functionality. The plurality of multi-purpose I/O blocks is also configured to save power when ADC mode is disabled.

Abstract: An exemplary data driver chip (23) includes a multiplexer (31); a first digital/analog (D/A) converter (32); and a second digital/analog (D/A) converter (33). The multiplexer receives a multiplex data stream and decomposes the multiplex data stream to a first signal and a second signal, and respectively sends the first and second signals to the first and the second D/A converters. The first D/A converter converts the first signal to an analog gamma voltage to the second D/A converter, and the second D/A converter converts the second signal to analog video signal according to the analog gamma voltage.

Abstract: An integrated circuit device having at least one bond pad is coupled to a selectable plurality of input-output functionalities, e.g., an oscillator input, an analog input, an analog output, a digital input and a digital output. These analog, digital and oscillator functionalities may selectably share the same integrated circuit package external connection.

Abstract: A signal conditioning circuit time share multiplexes anti-aliasing filters and an A/D converter. A plurality of first tier multiplexers each time share multiplex one of a plurality of antialiasing filters between a plurality of AC or baseband input signals from a plurality of sensors. A second tier multiplexer selects its inputs from the outputs of the first tier multiplexers. The output of the second tier multiplexer feeds a high speed A/D converter. Thus, the A/D converter is time share multiplexed by the second tier multiplexer. In this manner, a plurality of sensors can share a single A/D converter. After allowing a settling time for the multiplexers and antialiasing filters, a plurality of samples of the input signals are taken, such as for one period. The samples of each AC input signal are multiplied by a sine vector and a cosine vector. The product vectors are then each averaged and the root mean square of the two averages yields the magnitude of the input signal.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of digital intermediate signals in response to an analog input signal, a first set of threshold and reference voltages and a second set of threshold and reference voltages, where the threshold and reference voltages of the first set are shifted with respect to corresponding threshold and reference voltages of the second set. The second circuit may be configured to generate a digital output signal in response to the plurality of digital intermediate signals.

Abstract: A multiplexing circuit uses parallel-configured pairs of resistors and signal sources in a voltage divider network in such a way that a single analog-to-digital input can be used to specify the state of more than one signal source. One circuit includes a microprocessor having an analog-to-digital (ADC) input; a memory communicatively coupled to the microprocessor; and a voltage divider network having an output coupled to the ADC input, wherein the network includes a plurality of resistors paired with a plurality of respective signal sources, and wherein the output is unique for each combination of states of the signal sources in accordance with a known relation that is stored in the memory. The signal sources are selected from two categories of sources: continuous sources and discrete sources, where discrete sources may be binary discrete or random discrete. In one embodiment, the first signal source is either a continuous source or a random discrete source, and the second signal is a binary discrete source.

Abstract: A multi-channel digital/analog converter arrangement comprises at least two data channels for receiving and forwarding a corresponding number of digital data input signals comprising respective time characteristics, a digital multiplexer generating a digital intermediate signal present at a common node by combining the at least two digital data input signals, and a digital/analog converter connected downstream of the multiplexer for converting the digital intermediate signal into an analog output signal. The multiplexer comprises a tuning device for tuning the time characteristics of the at least two digital data input signals in respect to each other.

Abstract: The sampling time in a multichannel analog-to-digital converter is programmed with a circuit comprising a memory register with memory locations, which can be respectively coupled to the channels of the converter. The memory locations of the register are able to store a signal identifying a sampling-time value selected for each individual channel of the converter. The circuit likewise comprises a converter module coupled to the memory register for converting the signal identifying the sampling-time value into a corresponding signal for driving the respective channel of the converter for a sampling time corresponding to the sampling time selected. The circuit can be actuated in a synchronized way with the converter so as to vary selectively the sampling time applied to the channels of the converter in the course of operation.

Abstract: In response to a selected analog applied to the input terminal of an analog-to-digital converter, the digitized output signal is stored in a buffer/register. In making a comparison with a predetermined value, a second buffer/register stores either a preselected value or a second digitized signal. A comparator is coupled to the first and the second buffer/register to provide the result of a comparison. In this manner, the central processing unit is not involved in the comparison testing procedure.

Abstract: Interface unit for voltage input signals comprising two or more input channels. The input signals of these two or more input channels are connected alternately by an analog multiplexer to an analog-to-digital converter. The A/D converter comprises an integrated sigma-delta modulator circuit which generates a digitized 1-bit signal representing the input signal voltage level for a control unit irrespective of whether the input channel signal is digital or analog. By means of the invention all input voltage channels are made similar such that the input channels of the interface unit can receive an analog or digital signal irrespective of each other.

Abstract: A sigma-delta circuit with time sharing architecture includes a coefficient generation element, a sigma-delta processing element, and a storage element. The coefficient generation element is used for generating coefficients for sigma-delta operations. The sigma-delta processing element is used for executing sigma-delta operations according to the coefficients generated by the coefficient generation element. The storage element is used for storing results of the sigma-delta operations executed by the sigma-delta processing element. The sigma-delta circuit is used for executing a plurality of orders of sigma-delta operations through the coefficient generation element, the sigma-delta processing element and the storage element.

Abstract: A bias circuit includes a digital to analog converter (D2A) generating an output representing a voltage level for tuning an analog signal. The D2A is coupled to a primary register frame that is one of a plurality of register frames forming a data chain. The plurality of register frames are serially linked and data within the data chain is shifted among the plurality of register frames. Through a time domain multiplexing scheme, the D2A can be shared by control knobs of the equalization circuit. The bias circuit includes a decoder also coupled to the primary register frame. An output enable logic module is also included. The output enable logic module determines when the primary register has a complete data set as the data within the data chain is shifting according to the clock period. A method for adjusting a signal through a bias circuit is also provided.

Abstract: An apparatus for adaptively generating video signal thresholds for a comparator circuit having a plurality of signal channels. The apparatus has input circuitry in electrical signal communication with the plurality of signal channels. The input circuitry uses a selector circuit to select one signal channel of the plurality of signal channels for processing. The apparatus also has a processing resource having an input joined to process the electrical signals on the selected one signal channel to determine if a video signal is present and, if no video signal is present, to process noise signals on the selected one signal channel to generate a new video signal threshold. The processing resource has an output to provide the new video signal threshold to the comparator circuit corresponding to the selected signal channel.

Abstract: A signal selecting circuit is disclosed which outputs a first and a second digital signals by converting a first and a second analog signals into digital signals, the first and the second analog signals being the same or different signals selected from a plurality of analog signals, the signal selecting circuit comprising: an analog signal selection circuit that, based on an analog selection signal, selects the first and the second analog signals from the plurality of analog signals; a first AD converter that converts the first analog signal outputted from the analog signal selection circuit into a third digital signal to output the third digital signal; a second AD converter that converts the second analog signal outputted from the analog signal selection circuit into a fourth digital signal to output the fourth digital signal; a digital signal selection circuit that, based on a digital signal, selectively outputs one or both of the third and the fourth digital signals as the first and the second digital sig

Abstract: An integrated circuit includes a plurality of circuit groups, each circuit group containing a plurality of analog inputs, a buffer, a sample/hold circuit and a comparator. Each buffer has an input to which any of the analog inputs in its group may be programmably connected. The output of each buffer is coupled to the input of the sample/hold circuit in the group. The output of each sample/hold circuit is coupled to one input of a multiplexer. The output of the multiplexer is coupled to the input of an amplifier having programmable gain and programmable offset. The comparator in each group has inputs that may be programmably coupled to at least one analog input in the group or to a reference voltage source.

Abstract: An operational amplifier circuit is described. The operational amplifier circuit includes an operational amplifier, a high-pass filter portion, and a feedback loop, wherein the operational amplifier circuit is configured to output an amplified filtered version of a bio-signal. The operational amplifier includes a non-inverting input terminal, and an inverting input terminal, wherein the inverting input terminal and the non-inverting input terminal are configured to be coupled to a common reference potential through resistors. The high-pass filter portion is configured to receive a bio-signal as input and to provide input to the non-inverting input terminal of the operational amplifier. The feedback loop includes a low-pass filter portion, wherein the low-pass filter portion is configured to receive input from an output of the operational amplifier and to provide input to the inverting input terminal of the operational amplifier.

Abstract: A sampled-data-integrating front end is employed to convert an optical signal to a digital electrical signal. The front end includes a photodetector and an array of parallel conversion circuits, each including an activation switch, a charge amplifier and an Analog to Digital Converter (“ADC”). The charge amplifier includes a reset switch, a capacitor, and an amplifier. The resent switch is operable to discharge the capacitor. The capacitor is operable to charge to the voltage of a signal charge when the activation switch is closed, and to hold that voltage after the activation switch is opened. The amplifier is operable to provide current at the voltage across the capacitor for a period sufficient to enable the ADC to obtain an accurate sample. The parallel conversion circuits are time-interleaved to provide a selected resolution in the digital electrical representation of the optical signal.

Abstract: A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each sample-and-hold circuit in a first group of N sample-and-hold (S/H) circuits is connected to a corresponding output of the analog demultiplexer. Similarly, each S/H circuit in a second group of N S/H circuits is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the S/H circuits in the first group and a second input connected to an output of a corresponding one of the S/H circuits in the second group.

Abstract: A system for multi-channel analog-to-digital conversion has a plurality of sampling modules, wherein each of the modules includes an input node and an output node; multiplexing circuitry configured to selectively route at least one of a plurality of electrical signals present on the output nodes to an analog-to-digital converter; and control circuitry in communication with the multiplexing circuitry, wherein the control circuitry is programmatically configured to control a sequence in which the electrical signals are routed to the analog-to-digital converter.

Abstract: The present invention provides an OFDM receiver having a level control section comprising comparators which respectively compare a first signal outputted from an ADC with threshold values, counters which respectively count the frequencies with which the level of the first signal exceeds the threshold values, based on second and third signals corresponding to the results of comparison by the comparators, a moving average unit which calculates an average value of the level of the first signal lying in a predetermined period, based on fourth and fifth signals corresponding to the frequencies counted by the these counters, and a DAC which generates a gain control signal for controlling an AMP in such a manner that the average level of the first signal outputted from the ADC becomes a predetermined value, according to a sixth signal calculated by the moving average unit.

Abstract: A sensing circuit determines whether an integrated circuit is currently exposed to one of a relatively low or a relatively high temperature. A selection circuit selects a measured voltage across the base-emitter of a bipolar transistor if the sensing circuit indicates that the circuit is exposed to the relatively low temperature or, alternatively, selects a measured delta voltage across the base-emitter of the bipolar transistor if the sensing circuit indicates that the circuit is exposed to the relatively high temperature. A comparator compares the selected measured voltage against a first reference voltage indicative of a too cold temperature condition or compares the selected measured delta voltage against a second reference voltage indicative of a too hot temperature condition. As a result of the comparison, detection may be made as to whether the integrated circuit is currently exposed to a too cold or too hot temperature.

Abstract: A method of encoding a multi-channel signal having first and second signal components includes determining a set of filter parameters a prediction filter such that the prediction filter provides an estimate of the second signal component when receiving the first signal component as an input. The multi-channel signal is represented as the first signal component and the set of filter parameters. A corresponding decoding method and arrangements for encoding and decoding multi-channel signals are also provided.