Abstract: This disclosure is directed to artificially intelligent (AI) communication generation by traversing routes of a graph in a complex computing network. The intelligent communication generation is used for determining whether an input signal has certain desired signal attributes.

Abstract: An embodiment of a capacitance sensing circuit includes a set of bridge switches coupled with a reference cell and a sensor cell. The set of bridge switches is configured to, over a first phase, increase a voltage difference between a first modulation capacitor and a second modulation capacitor, and over a second phase, decrease the voltage difference at a rate corresponding to a difference between a capacitance of the sensor cell and a capacitance of the reference cell. The capacitance sensing circuit also includes a comparator configured to generate an output based on comparing a first voltage of the first modulation capacitor with a second voltage of the second modulation capacitor, and initiate a transition between the first phase and the second phase in response to the comparing.

Abstract: Clock rate adjustment methods and systems, including receiving, by a playback device from a source device, a plurality of frames, including a first frame and a second frame, each frame being associated with audio information and a time indicating when to play the audio information wherein the time is based on the clock of the source device; determining, by the playback device an expected time value for a third frame; comparing, by the playback device, the expected time value to the time indicating when to play the audio information associated with the third frame; and when the difference between the expected time value and the time indicating when to play the audio information is above a threshold level, adjusting, by the playback device, a rate of a digital to analog converter clock associated with the playback device.

Abstract: A sigma-delta converter including a sigma-delta modulator including at least one analog filter capable, for each cycle of a conversion phase, of receiving an internal analog signal originating from the analog input signal and of supplying an analog output signal, wherein: the contribution of the internal analog signal to the output value of the filter is smaller at a given cycle of the conversion phase than at a previous cycle, the contributions to the different cycles being governed by a first predetermined law which is a function of the rank of the cycle; and the duration of a given cycle of the conversion phase is shorter than the duration of a previous cycle, the durations of the different cycles being governed by a second predetermined law which is a function of the rank of the cycle in the conversion phase.

Abstract: A pixel circuit comprises a first capacitor, a photo diode and a switch. A voltage source generates a reference voltage to reset the pixel circuit. The pixel circuit is reset for a first reset time period by electrically coupling a cathode of the photo diode and a first capacitor terminal to the voltage source. The cathode is decoupled from the voltage source and the photo diode is exposed to light for an accumulation time period. After the accumulation time period, a first reference voltage is sampled. The cathode is then coupled, via the switch, to the first capacitor terminal for a selected transfer time period, during which a second signal voltage is sampled. After the selected transfer time period, a first signal voltage is sampled with the cathode decoupled. The pixel circuit is then reset for a second reset time period, after which a second reference voltage value is sampled.

Abstract: Some embodiments include apparatus and methods using an integrator in a loop filter of a sigma-delta analog-to-digital converter (ADC), a digital-to-analog converter (DAC) located on a feedback path of the ADC, the DAC including output nodes coupled to input nodes of the integrator, and a comparator including input nodes to receive signals from output nodes of the integrator, and an output node to provide information during calibration of the DAC.

Abstract: A delta-sigma modulator includes a first integrator configured to integrate a sum of an input signal and a first feedback signal, a second integrator configured to integrate a sum of an output value of the first integrator and a second feedback signal, a first FIR filter circuit configured to perform a first FIR filtering on an output modulation signal and a delay modulation signal and feeds back the signals to stage prior to the first integrator, and a second FIR filter circuit configured to perform a second FIR filtering on the output modulation signal and the delay modulation signal and feeds back the signals to a stage prior to the second integrator.

Abstract: Methods and apparatus embodiments to communicate data via a digital isolator by receiving an input data stream having first and second states, generating a first pulse train for the first state and a second pulse train for the second state. The first and second pulse types are transmitted across a voltage barrier of a digital signal isolator and received by a receive channel. The first and second pulse trains are processed to recover the input data stream in an output data stream. Data/System integrity functionality can identify fault conditions from an alteration of transmitted pulses.

Abstract: To convert a first stage input to a digital output, a delta-sigma modulator, an analog-to-digital converter and an associated signal conversion method based on an MASH structure are provided. The analog-to-digital converter includes the delta-sigma modulator and a sample and hold circuit. The delta-sigma modulator includes a first signal converter, a second signal converter and a digital cancellation logic. The first signal converter converts the first stage input to a first converted output. The first signal converter shapes a first stage quantization error to generate a second stage input. The first stage input and the second stage input are analog signals. The second signal converter converts the second stage input to a second converted output. The digital cancellation logic generates a digital output according to the first converted output and the second converted output.

Abstract: A transducer for an ultrasound imaging system includes an array of transducer elements and an analog-to-digital converter configured to convert analog signals produced by the transducer elements into corresponding digital samples that are encoded with a first number of bits. One or more memories are used to store digital samples associated with frames of ultrasound data. A processor or logic circuit in the transducer is configured to compress the digital ultrasound data by calculating differences between the samples and encoding the differences with a second number of bits that is less than the first number of bits. In addition, the logic circuit is configured to transmit a packet that includes the differences encoded with the second number of bits and an overflow portion that encodes the differences that are too large to be encoded with the second number of bits.

Abstract: A low power high precision mixed signal analog to digital converter is provided for processing biometric signals in the presence of a large interferer signal for cableless patient monitoring; a capacitive difference circuit produces an analog difference signal by differencing an analog feedback loop signal and an input signal; an analog-to-digital converter sigma delta converter produces a digital version of the difference signal, a digital feedback loop includes a digital integrator and a capacitive digital-to-analog converter configured to produce the analog loop feedback signal based upon the digital version of the difference.

Abstract: Techniques are provided for low, or deep, dimming of a light-emitting diode (LED) load. In an example, a method of adjusting an initial voltage of a driver circuit for an LED load can include providing current to an LED load from a power stage of the driver during an on-time of a pulse-width modulation (PWM) cycle, receiving error current information of the driver circuit at a low-dimming control circuit of the driver, and adjusting a voltage of an output capacitor coupled to the driver during an off-time of the PWM cycle, the charge adjustment based on the error current information.

Abstract: Techniques are described to cancel kT/C sampling noise and residue amplifier sampling noise while also reducing power consumption in a pipelined analog-to-digital converter circuit.

Abstract: A digital transmitter includes baseband interfaces to generate digital baseband signals with baseband frequencies, digital-upconverting stages to upconvert the baseband frequencies to first radio frequencies having a predetermined frequency range, a M-Band ??M modulator to modulate the up-stage signals based on noise shaping and noise quantization processes, delay registers to align phases of the modulated up-stage signals, a noise canceler to generate noise canceling signals with a converted polarity, a Switch Mode Power Amplifier to amplify the phase aligned modulated up-stage signals up to a predetermined power level, a linear power amplifier to amplify the noise canceling signals up to the predetermined power level, a power combiner to combine to generate transmitting signals by combining the amplified phase aligned modulated up-stage signals and the amplified noise canceling signals, and an antenna to transmit the transmitting signals.

Abstract: A current mode sigma-delta modulator comprises an input node; a comparator that compares a voltage of the input node to a reference voltage and outputs a comparison result; an integrating capacitor connected to an input of the comparator; and a switched capacitor circuit connected at a first end to the input node, the input of the comparator, and the integrating capacitor, and connected at a second end to an output of the comparator. The current mode sigma-delta modulator is a component of an analog-to-digital converter.

Abstract: In various embodiments, a circuit is provided. The circuit includes: a voltage biasing circuit coupled to a microelectro-mechanical system (MEMS) microphone sensor, the MEMS microphone sensor coupled to a driver circuit, and the driver circuit coupled to an oscillator-based ADC circuit. The oscillator-based ADC circuit may include an Nth order sigma-delta modulator, where N is an integer equal to or greater than 1.

Abstract: Systems, methods, and other embodiments are disclosed that are configured to provide on-chip current sensing by employing a power distribution network voltage de-convolution technique. A voltage signal on a voltage plane of a system-on-chip device is measured during operation of the system-on-chip device. The voltage signal derives from a power distribution network. The voltage signal is de-convolved, based at least in part on inverse convolution coefficients derived from the power distribution network, to recover a current signal being drawn by the system-on-chip device from the power distribution network.

Abstract: A sigma-delta converter comprises a sigma-delta modulator suitable for supplying a series of binary samples (BS(k)) representative of an analogue input signal (Vin) to be digitized, in which at least one analogue signal internal to the modulator is weighted by a coefficient that is variable according to a first predetermined law (f).

Abstract: A method and apparatus for temperature compensation for data converters in a software defined radio. Specifically, the system and method are teach monitoring the temperature of critical signal processing components such as band pass filters, ADCs and DACs and retrieving modulator coefficients in response to the temperatures and the like. The modulator coefficients are then used to compensate for temperature changes, performance changes and the like.

Abstract: A delta sigma modulator circuit comprises a forward circuit path including a first integrator stage and an analog-to-digital converter (ADC) circuit, wherein a transfer function of the forward circuit path includes a signal gain element of m, wherein m is a positive integer; an input path to the first integrator stage, wherein a transfer function of the input path includes a signal gain element of l/m; and a feedback circuit path operatively coupled to an output of the ADC circuit and an inverting input of an op amp of the first integrator stage, wherein the feedback circuit path includes at least a first digital-to-analog converter (DAC) circuit and a transfer function of the feedback circuit path includes a signal gain element of l/m.

Abstract: A method of managing traffic in a communications channel includes the steps of receiving a subscriber ID corresponding to a subscriber, performing a spectral analysis on a signal received from the subscriber within a time interval identified by the subscriber ID, and adjusting transmission characteristics of the subscriber based on the spectral analysis.

Abstract: An optical data circuit includes threshold adjustment circuits to perform threshold adjustment compensation of asymmetrical optical noise. The optical data circuit includes an optical-to-electrical conversion circuit configured to produce first and second differential electrical data signals, at respective first and second electrical nodes, in response to an optical data signal. First and second digital-to-analog converter (DAC) circuits are each respectively coupled to the first and second electrical nodes and configured to respectively generate first and second adjustment signals. The first and second DAC circuits are configured to adjust the first and second differential electrical data signals such that a zero-crossing point of positive data is pulled up in response to the first adjustment signal and a zero-crossing point of negative data is pulled down in response to the second adjustment signal.

Abstract: A signal processing system for producing a load voltage at a load output of the signal processing system, wherein the load output comprises a first load terminal having a first load voltage and a second load terminal having a second load voltage such that the load voltage comprises a difference between the first load voltage and the second load voltage, and may include a first processing path configured to process a first signal derived from an input signal to generate the first load voltage at a first processing path output, a second processing path configured to process a second signal received at a second processing path input and derived from the input signal, wherein the second signal comprises information of the input signal absent from the first signal, to generate the second load voltage at a second processing path output, and a high-pass filter coupled between the first processing path output and the second processing path input.

Abstract: The present application provides a noise shaping circuit including a first modulation unit, configured to generate a first digital output signal according to a first digital input signal, the first modulation unit comprising a first quantizer; a first subtractor, coupled to an input terminal and an output terminal of the first quantizer, configured to generate a first quantization noise; and a second modulation unit, configured to generated a second digital output signal according to a second digital input signal, wherein the second digital input signal is related to the first quantization noise; wherein the noise shaping circuit generates an overall analog output signal according to the first digital output signal and the second digital output signal.

Abstract: A method includes providing a first voltage to a first output node during a first time interval, providing a second voltage to the first output node during a second time interval, and averaging the first and second voltages to provide a reference voltage to a second output node. The first voltage includes a proportional-to-absolute-temperature (PTAT) component, a complementary-to-absolute-temperature (CTAT) component, and a first residual offset component. The second voltage includes the PTAT component, the CTAT component, and a second residual offset component. An apparatus includes a discrete-time circuit to provide the first voltage to the first output node during the first time interval and to provide the second voltage to the first output node during the second time interval, and a filter to average the first and second voltages to provide the reference voltage to the second output node.

Abstract: Circuits and methods for inter-symbol interference compensation are described. These circuits and methods may be used in connection with delta-sigma analog-to-digital converter. During a sensing phase, a value indicative of the inter-symbol interference may be sensed. The value may be obtained by (1) causing the ADC to generate a first number of transitions during a first time interval; (2) causing the ADC to generate a second number of transitions during a second time interval; (3) sensing the number of logic-0s and logic-1s occurring in the first and second time intervals; and (4) computing the value based at least in part on the number of logic-0s and logic-1s occurring in the first and second time intervals. During a compensation phase, inter-symbol interference may be compensated based on the value obtained in the sensing phase.

Abstract: According to at least one aspect, a delta sigma modulator circuit is provided. The delta sigma modulator circuit includes a first signal processor circuit configured to receive an input signal and a feedback signal and generate a processed signal using the input signal and the feedback signal, a quantizer configured to generate a digital code using the processed signal, a second signal processor circuit configured to receive the digital code, segment the digital code to form a segmented digital code that is smaller in size than the digital code, and generate a rotated digital code using the segmented digital code at least in part by rotating the segmented digital code to compensate for an excess loop delay in the circuit, and an digital-to-analog converter (DAC) configured to receive the rotated digital code and generate the feedback signal using the rotated digital code.

Abstract: A sigma delta modulator includes a sigma delta modulating loop and a plurality of adjusting loops. The sigma delta modulating loop processes an input signal and an adjustment signal based on a first clock signal, so as to generate a quantized output signal. The first clock signal has a clock cycle. The sigma delta modulating loop has a first delay time that is the same as M times of the clock cycle. M is an integral multiple of 0.5 and is larger than 1. The adjusting loops delay the quantized output signal for second delay times, respectively, so as to generate the adjustment signal.

Abstract: A communication system includes a data source to receive a block of bits, a memory to store a set of distribution matchers. Each distribution matcher is associated with a probability mass function (PMF) to match equally likely input bits to a fixed number of output bits with values distributed according to the PMF of the distribution matcher. Each distribution matcher is associated with a selection probability, such that a sum of joint probabilities of all distribution matchers equals a target PMF. A joint probability of a distribution matcher is a product of PMF of the distribution matcher with the selection probability of the distribution matcher.

Abstract: A delta-sigma modulator may comprise a loop filter for integrating and outputting a difference between an input signal and an analog signal; a quantizer for quantizing and outputting a signal output from the loop filter; and a digital-to-analog converter (DAC) for outputting the analog signal by digital-to-analog converting a signal output from the quantizer. Also, the loop filter may comprise an operational amplifier; and a circuit including at least one capacitor, at least one resistor, and at least one switch which are connected to the operational amplifier. Also, signal transfer characteristics of the loop filter satisfy a third-order transfer function or a second-order transfer function by turning on or off the at least one switch.

Abstract: In the present invention, an all digital, multi channel RF transmitter is utilized for a parallel magnetic resonance imaging (MRI) device, MRI signal generation, modulation and amplification are employed entirely digitally in the proposed RF transmitter, which enables each transmit channel to be easily and individually reconfigured in both amplitude and phase. Individual channel control ensures a homogeneous magnetic field in the multi channel RF coil in MRI. Besides the homogeneous magnetic field generation, multi-frequency MRI signal generation is made easy by the present invention with very high frequency resolution. Multi-frequency enables faster image acquisition which reduces MRI operation time. Digital Weaver Single Side Band (SSB) modulation is also incorporated into the all digital transmitter to suppress unwanted bands of Double Side Band (DSB) MRI signals. The power amplifier in the MRI transmitter does not amplify the unwanted band so that SSB modulation leads to higher power efficiency.

Abstract: Provided is a quantum random pulse generator having enhanced security using a phenomenon in which a radioactive isotope naturally collapses. The quantum random pulse generator includes a photodiode detection unit which has a photodiode disposed at the center of the photodiode detection unit on a top surface, a radioactive isotope emission unit which emits alpha particles discharged when an atomic nucleus naturally collapses toward a photodiode, and a plate which is disposed on a top surface of the radioactive isotope emission unit and supports the radioactive isotope emission unit. The alpha particles discharged by the emission unit come into contact with the photodiode to generate a random pulse.

Abstract: A sigma delta analog to digital converter for converting an analog input into a digital output comprises a reference path for receiving a reference voltage. The reference path comprises a digital to analog converter. The digital to analog converter comprises a reference voltage input for receiving the reference voltage, wherein the reference voltage input comprises two contacts and wherein each contact is a beginning of a voltage line of two voltage lines. The digital to analog converter comprises a plurality of switches and a plurality of capacitors. The switches of the plurality of switches are configured to connect the digital to analog converter in a sampling phase with the reference voltage and to disconnect the digital to analog converter in an integrating phase from the reference voltage.

Abstract: Techniques for generating signals with arbitrary noise shaping are discussed. One example apparatus configured to be employed within a transmitter can comprise a noise shaper configured to: receive an input signal xq; and apply noise shaping to the input signal xq to generate a noise shaped output signal yq, wherein an in-band noise of the noise shaped output signal yq is below an in-band noise threshold of a spectral mask associated with the noise shaper, wherein an out-of-band noise of the noise shaped output signal yq is below an out-of-band noise threshold of the spectral mask, and wherein a noise of the output signal yq in each of a plurality of bandpass regions is below an associated noise threshold for that bandpass region of the spectral mask.

Abstract: Systems, apparatuses, and methods for implementing a low power filter. A low power filter may generate a reference sum from a reference vector in order to reduce the number of additions which are needed to filter an input sample vector. The reference sum may be used as the starting point for filtering the input sample vector. Then, each input sample of the input sample vector may be compared to a corresponding reference vector sample. If an input sample is different from the corresponding reference vector sample, a correction value based on the corresponding filter coefficient value may be added or subtracted from the reference sum. After all input samples have been compared to corresponding reference vector values and all correction values applied to the reference sum, the modified reference sum may be the output of the filter.

Abstract: Disclosed are systems and methods for identifying and reporting failures of an analog-to-digital converter (ADC). Specifically, the systems and methods described herein evaluate quantization noise properties of ADCs, including delta-sigma ADCs and successive approximation register (SAR) ADCs, to verify functionality and/or identify failures. Quantization noise properties can be evaluated in the frequency domain by, for example, comparing RMS values, magnitudes, frequency spectrums, and the like, in various frequency bands to threshold values and/or to verify an expected noise shape. Quantization noise properties can additionally or alternatively be evaluated in the time domain by, for example, comparing counts of pulse widths, average pulse widths, and/or number of transitions within a sequence of pulses to threshold values and/or to similar identifiable characteristics in other pulse width bands.

Abstract: Systems and methods for sampling data in bandwidth constrained data acquisition systems are provided. More specifically, the method may include selecting an anti-aliasing filter corner frequency equal to a first frequency, selecting an oversampling rate that is greater than a data sample transmission bandwidth, wherein the data sample transmission bandwidth is a data sample transmission rate from a data acquisition system to a receiving entity for data samples acquired from a sensor and having a selected sample resolution, acquiring data samples at the oversampling rate with the data acquisition system, and transmitting a fraction of the acquired data samples in accordance with the data sample transmission bandwidth.

Abstract: An error feedback system for a delta sigma modulator is disclosed. The error feedback system has an error transfer function where at least k?1 coefficients are set to zero. This allows the error feedback system to be divided into k feedback paths that are performed in parallel at a clock speed that is 1/k of the system clock of the delta sigma modulator (i.e. the rate at which the output of the delta sigma modulator changes).

Abstract: Described herein are various technologies relating to processing a coherent signal. A receiver is configured to receive an analog signal, and process the analog signal to generate an input analog signal. The input analog signal has been modulated according to a suitable modulation sequence. A coherent signal sampler coherently samples the modulation sequence, and the result of such sampling is in turn used to demodulate the input analog signal. The resultant signal is then passed to a sigma delta modulator, where it is converted to digital form.

Abstract: A method for measuring capacitance may include integrating charge with a charge integrator having a charge integrator input and output, filtering, with a loop filter having a loop filter input coupled to the charge integrator output and having a loop filter output, a first signal generated at the charge integrator output, quantizing, with quantizer having a quantizer input coupled to the loop filter output and a having quantizer output, a second signal generated at the loop filter output, processing, with a first feedback path having a first feedback path input coupled to the quantizer output and a first feedback path output coupled to the charge integrator input, a low-frequency spectrum of a quantizer output signal, and processing, with a second feedback path having a second feedback path input coupled to the quantizer output and a second feedback path output coupled downstream in a signal path of the apparatus relative to the charge integrator, a high-frequency spectrum of the quantizer output signal.

Abstract: A data processor is disclosed. The data processor includes a data processing module. The data processing modules includes an input for receiving an input signal, an output for providing a quantized output signal, a combining unit configured to combine a feedback signal from the output with the input signal and a quantizer configured to provide the quantized output signal based on the combined signal. The data processor further includes a correction module configured to receive the quantized output signal, generate a full-scale digital signal based on the quantized output signal, determine a metastability error in the full-scale digital signal and provide a compensated output signal based on the quantized output signal and the determined metastability error.

Abstract: A time-to-digital converter includes: an input for receiving a time-domain input signal; an output for providing a digital output signal; a time register coupled to the input and to a first node; a time quantizer coupled to the time register for providing the digital output signal at the output; and a digital-to-time converter coupled to the output for providing a feed-back signal at the first node.

Abstract: The present invention relates to a method and a device for measuring currents or magnetic fields using at least one Hall sensor, which is operated with spinning current technology. In addition to first sample values for calculating a spinning current measurement value (6), second sample values are formed from the digitally converted sensor signals (1) of the Hall sensor in the method. The second sample values are formed over shorter periods of time (9) and are corrected with an offset, which is calculated from the spinning current measurement value (6) and the first sample values. In addition to the precise spinning current measurement value (6), fast offset-corrected measurement values (10) of the magnetic field or current are obtained using the method and the associated device, without elaborate calibration or additional analog circuitry expenses.

Abstract: A Gated CDS Integrator (GCI) may amplify low-level signals without introducing excessive offset and noise. The GCI may also amplify the low level signals with accurate and variable gain. The GCI may include a modulator preceding a linear amplifier such that offset or noise present in a signal path between the modulator and a demodulator input is translated to a higher out of band frequency.

Abstract: With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status.

Abstract: A delta-sigma modulator includes a receiving circuit, a loop filter, a quantizer, a dynamic element matching circuit and a digital to analog converter. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter is arranged for receiving the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a digital output signal according to the filtered summation signal. The dynamic element matching circuit is arranged for receiving the digital output signal to generate a shaped digital output signal for shaping element mismatch. The digital to analog converter is arranged for performing a digital to analog converting operation upon a signal derived from the shaped digital output signal to generate the feedback signal to the receiving circuit, wherein clock signals used by the quantizer and the dynamic element matching circuit have different frequencies.

Abstract: A method of estimating diaphragm excursion of an electrodynamic loudspeaker may be performed using audio signals. An audio output signal may be applied to a voice coil of the electrodynamic loudspeaker through an output amplifier to produce sound. A detected voice coil current and a determined voice coil voltage may be applied to a linear adaptive digital loudspeaker model that has a plurality of adaptive loudspeaker parameters. The parameter values of the adaptive loudspeaker parameters may be computed based on the linear adaptive digital loudspeaker model and applied to a non-linear state-space model of the electrodynamic loudspeaker. For the non-linear state-space model, a predetermined non-linear function may be applied to at least one of the plurality of received parameter values to compute at least one non-linearity compensated parameter value of the adaptive loudspeaker parameters, to determine an instantaneous excursion of the diaphragm.

Abstract: An exemplary circuit includes a tracking circuit, a current estimator, a switch control logic, and a switching load circuit. The tracking circuit tracks a digital output signal of a delta-sigma modulator (DSM) and provides a tracking signal representing an average of the digital output signal during a time period. The current estimator determines an amount of loading to be applied to positive and negative reference voltages based on the tracking signal. The switching load circuit is coupled to positive and negative reference voltages of the DSM, the switching load circuit connects a selected amount of loading to the positive and negative reference voltages in response to a control signal to balance a reference load current applied to the DSM. The switch control logic provides the control signal to the switching load circuit based on the determined amount of loading to be applied to the positive and negative reference voltages.

Abstract: Apparatuses and methods of converting a capacitance measured on a sense element to a digital value are described. One apparatus includes a modulator having a modulator capacitor, a sense element selectively coupled in a feedback loop of the modulator to operate as a switching capacitor. The apparatus also includes a first switch coupled between a voltage source and a first node of the switching capacitor and a second switch coupled between the first node of the switching capacitor and a first node of the modulator capacitor. The switching capacitor provides a charge current to the modulator capacitor via the second switch. The modulator measures a capacitance of the sense element and converts the measured capacitance to a digital code representing the capacitance.

Abstract: Provided, among other things, is an apparatus for digitally processing a discrete-time signal that includes: an input line for accepting an input signal, processing branches coupled to the input line, and an adder coupled to outputs of the processing branches. First and second lowpass filters, each having a frequency response with a magnitude that varies approximately with frequency according to a product of raised functions, are included within baseband processors in such processing branches.