With Intermediate Conversion Of Digital Value To Time Interval Patents (Class 341/152)
  • Patent number: 10317252
    Abstract: In accordance with an embodiment, a method of performing a measurement with a capacitive sensor includes generating a periodic excitation signal that includes a series of pulses and smoothing edge transitions of the series of pulses to form a shaped periodic excitation signal that includes a flat region between the smoothed edge transitions. The method further includes providing the shaped periodic excitation signal to a first port of the capacitive sensor and measuring a signal provided by a second port of the capacitive sensor.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: June 11, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Andreas Wiesbauer, Christian Ebner, Ernesto Romani, Stephan Mechnig, Georgi Panov, Christian Jenkner, Benno Muehlbacher
  • Patent number: 9985644
    Abstract: A DTC (digital-to-time converter) includes: an inverter configured to receive an input clock at an input node and output an output clock at an output node, and a variable source degeneration network controlled by a digital word, wherein the inverter includes a transistor with a gate terminal connected to the input node, a drain terminal coupled to the output node, and a source terminal connected to the variable source degeneration network, and the variable source degeneration network includes a parallel connection of a resistor and a digitally-controlled capacitor of a capacitance controlled by the digital word.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: May 29, 2018
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yu Zhao, Chia-Liang (Leon) Lin
  • Patent number: 9802718
    Abstract: A duty cycle-based bit interface system includes a first stage voltage converter and second stage voltage converter in signal communication with the first stage voltage converter. The first stage voltage converter converts a digital voltage signal into an analog voltage signal. The second stage voltage converters convert the digital voltage signal into a scaled version of the same. A sampling unit is in signal communication with at least one of the second stage voltage converters, and is configured to sample a portion of the first stage analog output voltage signal during a sampling time period. The sampled portion has a duty cycle based-analog voltage signal during the sampling time period. A bit selector unit is in signal communication with the sampling unit, and outputs a bit enable signal that initiates a specific diagnostic test among a plurality of diagnostic tests based on the duty cycle of the sampled portion.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: October 31, 2017
    Assignee: HAMILTON SUNDSTRAND CORPORATION
    Inventor: Brian R. Golden
  • Patent number: 9386651
    Abstract: A backlight unit includes a dimming signal generator configured to generate first and second pulse width modulation signals, first and second driving blocks configured to receive a driving voltage to emit a light, a controller configured to receive the first and second pulse width modulation signals and an output signal from one of the first and second driving blocks to generate a voltage control signal, and a voltage converter configured to control a level of an input voltage in response to the voltage control signal to generate the driving voltage.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: July 5, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sanghyun Lee, Seonhye Kim, Jeong Bong Lee, MiKyung Kang, Kyung-Uk Choi
  • Patent number: 9166615
    Abstract: A system and method is disclosed for a digital to analog converter which includes an interpolation filter to up-sample a digital signal, a cascaded digital pulse width modulation noise shaper having multiple stages to suppress in-band quantization errors due to digital pulse width modulation and truncation errors, and a hybrid finite impulse response filter/digital to analog converter coupled to a reconstruction filter which outputs the analog signal. The cascaded noise shaper stages each operate using the same quantization error signal.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: October 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Martin Kinyua
  • Patent number: 9159446
    Abstract: Digital focal plane arrays (DFPAs) with multiple counters per unit cell can be used to convert analog signals to digital data and to filter the digital data. Exemplary DFPAs include two-dimensional arrays of unit cells, where each unit cell is coupled to a corresponding photodetector in a photodetector array. Each unit cell converts photocurrent from its photodetector to a digital pulse train that is coupled to multiple counters in the unit cell. Each counter in each unit cell can be independently controlled to filter the pulse train by counting up or down and/or by transferring data as desired. For example, a unit cell may perform in-phase/quadrature filtering of homodyne- or heterodyne-detected photocurrent with two counters: a first counter toggled between increment and decrement modes with an in-phase signal and a second counter toggled between increment and decrement modes with a quadrature signal.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: October 13, 2015
    Assignee: Massachusetts Institute of Technology
    Inventors: Kenneth I. Schultz, Brian Tyrrell, Michael W. Kelly, Curtis Colonero, Lawrence M. Candell, Daniel Mooney
  • Patent number: 9136829
    Abstract: A system and method for controlling a power converter includes a digital-to-analog converter (DAC) and ramp generator for generating a reference current command. The DAC is configured to decrement (or increment) to a next state after a fixed number of clock pulses have occurred. The reference current command controls an output of the power converter. Means are provided for delaying an output of the DAC for a number of clock pulses less than the fixed number to increase a resolution of the DAC.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: September 15, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Hrishikesh Ratnakar Nene
  • Patent number: 9071304
    Abstract: Embodiments of a digital-to-time converter (DTC) and methods for generating phase-modulated signals are generally described herein. In some embodiments, a divide by 2N+/?1 operation on an oscillator signal generates first and second divider signals, the first divider signal is sampled to provide a rising-edge correlated signal, a divider unit output signal is sampled to provide a falling edge correlated signal, and either the second divider signal or a delayed version of the second divider signal is provided as the divider unit output signal. A selection between the rising-edge and the falling-edge correlated signals generates edge signals. A fine phase-modulated output signal is generated based on an edge interpolation between a first and second edge signals.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: June 30, 2015
    Assignee: Intel IP Corporation
    Inventors: Rotem Banin, Ofir Degani, Markus Schimper, Ashoke Ravi
  • Patent number: 9013341
    Abstract: A circuit including an analog-to-digital converter (ADC). The ADC is configured to receive an analog feedback signal and an analog input signal and generate a digital output. The circuit further includes a noise shaper. The noise shaper is configured to truncate the digital output and generate a noise shaper output having a lower number of bits than the digital output, and to shape quantization noise generated during truncation. The circuit further includes a pulse width modulation digital-to-analog converter (PWM DAC). The PWM DAC configured to process the truncated digital output of the noise shaper output and generate a PWM DAC output.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eric Soenen, Alan Roth, Martin Kinyua, Justin Shi, Justin Gaither
  • Patent number: 8988261
    Abstract: A delta-sigma D/A converter, by which a digital valued, input signal is convertible into a binary, clock signal time discrete, output signal. By forming an average value of the output signal over a number of clock signal cycles, an analog value of the input signal can be displayed. The delta-sigma D/A converter is embodied in such a manner that, in use, it provides the output signal by serial arrangement of signal patterns of a set of signal patterns, wherein the signal patterns of the set are, in each case, binary, clock signal time discrete and extend over a signal pattern cycles total of a plurality of clock cycles. At least two signal patterns of the set have mutually different signal pattern average values, which are formed over the respective signal pattern cycles total, and all signal patterns of the set have, in each case, essentially the same number, especially exactly the same number, of edges.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: March 24, 2015
    Assignee: Endress + Hauser Wetzer GmbH + Co. KG
    Inventors: Roberto Lugli, Michael Korn, Alfred Zotz, Stephan Damith
  • Patent number: 8988262
    Abstract: A delay circuit includes a first inverter in which a delay time of rising is larger than a delay time of falling, and a second inverter which is connected in series with the first inverter and in which a delay time of falling is larger than a delay time of rising. Transistors for each of the first and second inverters are connected in series between a power supply terminal and a ground terminal.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Daisuke Miyashita
  • Patent number: 8976051
    Abstract: Aspects of the present disclosure relate to floating point timers and counters that are used in a variety of contexts. In some implementations, a floating point counter can be used to generate a wave form made up of a series of pulses with different pulse lengths. An array of these floating point counters can be used to implement a pool of delays. In other implementations, an array of floating point counters can be used to analyze waveforms on a number of different communication channels. Analysis of such waveforms may be useful in automotive applications, such as in wheel speed measurement for example, as well as other applications.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ljudmil Anastasov, Jens Barrenscheen
  • Patent number: 8964860
    Abstract: To provide a digital modulator including: a signal adjuster (105) which is provided with a plurality of output lines, and which outputs, to the output line, which corresponds to a range to which a level of an input signal belongs, a signal of a level corresponding to the level of the input signal; a plurality of internal digital modulators (111-1 to 111-N), each of which is provided so as to correspond to each of the plurality of output lines and carries out delta-sigma modulation on the signal of the corresponding output line to output the modulated signal; and an encoder (113) which encodes the plurality of modulated signals respectively outputted by the plurality of internal digital modulators.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: February 24, 2015
    Assignee: NEC Corporation
    Inventor: Shinichi Hori
  • Publication number: 20150035690
    Abstract: A delay circuit includes a first inverter in which a delay time of rising is larger than a delay time of falling, and a second inverter which is connected in series with the first inverter and in which a delay time of falling is larger than a delay time of rising. Transistors for each of the first and second inverters are connected in series between a power supply terminal and a ground terminal.
    Type: Application
    Filed: February 26, 2014
    Publication date: February 5, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Daisuke MIYASHITA
  • Patent number: 8941521
    Abstract: To decrease the burden of digital processing, provided is an AD conversion apparatus comprising a pattern generating section that, for each target bit specified one bit at a time moving downward in the output data, generates a pattern signal having a pulse width or number of pulses corresponding to a weighting of the target bit; an integrating section that integrates the pattern signals according to a judgment value for judging a value of the target bit each time a pattern signal is generated, and outputs a reference signal obtained by accumulating the integrated value of each pattern signal; a comparing section that, each time generation of a pattern signal is finished, compares the input signal to the reference signal; and an output section that outputs the output data to have values corresponding to the comparison results obtained after each generation of a pattern signal corresponding to a bit is finished.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: January 27, 2015
    Assignee: Advantest Corporation
    Inventor: Yasuhide Kuramochi
  • Patent number: 8860597
    Abstract: Digital-to-analog converter circuitry is described. The digital-to-analog converter circuitry includes a plurality of weighted resistance elements. A first weighted resistance element includes a switch coupled to a reference voltage. The first weighted resistance element also includes a T-network coupled to the switch. The T-network approximately equalizes a first response speed of the first weighted resistance element with a response speed of a differently weighted resistance element.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: October 14, 2014
    Assignee: QUALCOMM Incorporated
    Inventor: Matthew D. Sienko
  • Patent number: 8860596
    Abstract: A redundant signed digit (RSD) analog to digital converter (ADC) includes an amplifier, a first variable capacitance circuit coupled to a first input to the amplifier, a second variable capacitance circuit coupled to a second input to the amplifier, a third variable capacitance circuit coupled to a first output of the amplifier, and a fourth variable capacitance circuit coupled to a second output of the amplifier. An output of the third and fourth capacitance circuits are coupled to one another and to inputs to the first and second variable capacitance circuits. Capacitance values of the first, second, third and fourth variable capacitance circuits are higher when inputs to the ADC correspond to a selected number of more significant bits than when inputs to the ADC correspond to a remaining number of less significant bits.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: October 14, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert S. Jones, Peijun Wang
  • Patent number: 8775107
    Abstract: Methods and devices to measure voltage margins of electromechanical devices are disclosed. The voltage margins are determined based on responses to test voltages which cause the devices to change states. State changes of the devices are detected by monitoring integrated current or charge used to drive the devices with the test voltages.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: July 8, 2014
    Assignee: Qualcomm MEMS Technologies, Inc.
    Inventors: Alok Govil, Kostadin Djordjev, Alan Lewis, Wilhelmus Johannes Robertus Van Lier
  • Patent number: 8766840
    Abstract: A system and method is disclosed for a digital input Class D amplifier which includes an interpolation filter to up-sample a digital signal, a noise shaping modulator to suppress in-band quantization errors due to digital pulse width modulation and truncation errors, and a hybrid finite impulse response filter/digital to analog converter coupled to an analog input Class D amplifier with digital pulse width modulation control loop. The hybrid finite impulse response filter/digital to analog converter uses N-taps implemented digitally and N-tap weights implemented in analog using resistors.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Martin Kinyua, Eric Soenen
  • Patent number: 8736478
    Abstract: A digital-to-analog converter (DAC) has a pulse-width encoder that generates a charging pulse having a pulse width proportional to the DAC's digital input value. The charging pulse controls a charging switch that selectively connects a current source to a capacitor for the duration of the charging pulse. At the end of the charging pulse, a voltage corresponding to the charge stored in the capacitor forms the DAC's analog output signal. Such DACs can be configured (1) with negative-gain amplifiers across the capacitor to form a negative feedback loop, (2) with multiple parallel current sources, and/or (3) in differential architectures.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: May 27, 2014
    Assignee: LSI Corporation
    Inventors: James A. Bailey, Abhishek Duggal
  • Patent number: 8717212
    Abstract: An improved quadrature bandpass-sampling delta-sigma analog-to-digital demodulator is provided, which includes a loop filter, an A/D responsive to the loop filter, and a first feedback D/A responsive to the A/D up-converted in frequency by a first multiplier and a clock. A first summing circuit is responsive to the first D/A and an RF input for providing an input to the loop filter. A plurality of feedback D/As is responsive to the A/D up-converted in different frequencies by a plurality of multipliers and a plurality of clocks for providing feedback inputs to the loop filter. The loop filter comprises a plurality of resonators arranged in cascade configuration, a plurality of analog mixers to provide frequency shifting of the error signals propagating through the resonators, and a plurality of summing circuits responsive to the feedback D/As.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: May 6, 2014
    Assignee: Phuong Huynh
    Inventor: Phuong Huynh
  • Patent number: 8698662
    Abstract: A system and method is disclosed for a digital to analog converter which includes an interpolation filter to up-sample a digital signal, a noise shaping modulator to suppress in-band quantization errors due to digital pulse width modulation and truncation errors, and a hybrid finite impulse response filter/digital to analog converter coupled to a Class D delta-sigma pulse width modulation control loop.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: April 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Martin Kinyua, Eric Soenen
  • Patent number: 8698661
    Abstract: A system and method is disclosed for a digital to analog converter which includes an interpolation filter to up-sample a digital signal, a noise shaping modulator to suppress in-band quantization errors due to digital pulse width modulation and truncation errors, and a hybrid finite impulse response filter/digital to analog converter coupled to a reconstruction filter which outputs the analog signal.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: April 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Martin Kinyua, Eric Soenen
  • Patent number: 8599052
    Abstract: An controller for use in a power supply includes a variable oscillator and a digital-to-analog converter (DAC). The variable oscillator generates a switching signal having an on-time and a switching period to control a first switch to regulate an output of the power supply. The DAC provides the variable oscillator with a first analog signal and a second analog signal, where the on-time of the switching signal is responsive to the first analog signal and where the switching period is responsive to the second analog signal. The DAC includes a current source and a second switch that is configured to couple the current source to provide current to the first analog signal in response to a binary digit received by the DAC, and to couple the current source to provide current to the second analog signal in response to a complement of the binary digit.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: December 3, 2013
    Assignee: Power Integrations, Inc.
    Inventors: Mingming Mao, Yury Gaknoki
  • Patent number: 8560258
    Abstract: Methods and devices to measure voltage margins of electromechanical devices are disclosed. The voltage margins are determined based on responses to test voltages which cause the devices to change states. State changes of the devices are detected by monitoring integrated current or charge used to drive the devices with the test voltages.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: October 15, 2013
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Alok Govil, Kostadin Djordjev, Alan Lewis, Wilhelmus Johannes Robertus Van Lier
  • Patent number: 8548767
    Abstract: The invention relates to a measuring device having at least one first assembly and at least one second assembly. The first assembly and the second assembly each comprise an intermediate frequency interface or a complex baseband interface. The intermediate frequency interfaces or baseband interfaces are designed as serial digital interfaces.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: October 1, 2013
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Gottfried Holzmann, Werner Mittermaier
  • Patent number: 8519877
    Abstract: A circuit for providing audio signals to a load such as a speaker is provided that uses the speaker or headphone amplifier structure as a current to voltage converter, thereby eliminating a separate current to voltage converter from the circuit. Such a design removes one of the elements that creates noise in the circuit architecture and improves the dynamic range for the audio signal. For example, the output of a digital to analog converter is a single ended output provided to the speaker or headphone amplifier. The digital to analog converter can include a series of current sources that are summed up to provide the single ended output. Where the current sources have positive and negative current source mismatch, a feedback mechanism is employed to correct for the mismatch and reduce introduction of harmonic noise into the signal through the digital to analog converter.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: August 27, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Shailendra Kumar Baranwal
  • Patent number: 8472552
    Abstract: A digital linear transmitter for digital to analog conversion of a radio frequency signal. The transmitter includes a delta sigma (??) digital to analog converter (DAC) and a weighted signal digital to analog converter in the transmit path of a wireless device to reduce reliance on relatively large analog components. The ?? DAC converts the lowest significant bits of the oversampled signal while the weighted signal digital to analog converter converts the highest significant bits of the oversampled signal. The transmitter core includes components for providing an oversampled modulated digital signal which is then subjected to first order filtering of the oversampled signal prior to generating a corresponding analog signal. The apparatus and method reduces analog components and increases digital components in transmitter core architecture of wireless RF devices.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: June 25, 2013
    Assignee: Icera, Inc.
    Inventors: Tajinder Manku, Abdellatif Bellaouar
  • Patent number: 8471746
    Abstract: A digital-to-analog converter includes first and second pulse modulators to generate first and second pulse modulated signals in response to first and second digital values, a third pulse modulator to generate a third pulse modulated signal in response to a third digital value, and a switch/filter circuit to generate an analog signal by combining the first and second pulse modulated signals in response to the third pulse modulated signal. The first and second pulse modulated signals may be low-pass filtered before being combined. In some embodiments, the third digital value may be incremented in a single direction between transitions of the first and second digital values. In some other embodiments, the third digital value may be incremented in opposite directions between alternating transitions of the first and second digital values.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: June 25, 2013
    Assignee: Tektronix, Inc.
    Inventor: David F. Hiltner
  • Patent number: 8471747
    Abstract: A method is provided. A noise shaped signal having a plurality of instants is generated with each instant being associated with at least one of a plurality of output levels. A next phase is selected for each instant, where each next phase is a circularly shifted phase based at least in part on a previous phase for the associated output level for its instant. A plurality of PWM signals is then generated using the phase for each instant, and an amplified signal is generated from the plurality of PWM signals.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: June 25, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Lei Ding, Rahmi Hezar, Joonhoi Hur, Baher S. Haroun
  • Patent number: 8355883
    Abstract: Methods and devices to measure voltage margins of electromechanical devices are disclosed. The voltage margins are determined based on responses to test voltages which cause the devices to change states. State changes of the devices are detected by monitoring integrated current or charge used to drive the devices with the test voltages.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: January 15, 2013
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Alok Govil, Kostadin Djordjev, Alan Lewis, Wilhelmus Johannes Robertus Van Lier
  • Patent number: 8315331
    Abstract: A transmission method for transmitting transmission data via a single line, includes: transmitting, as the transmission data, data that has one rising or falling transition of the amplitude of the data in each clock cycle of a clock and that carries a 2- or greater-bit value, making use of the phase from the edge of the clock to the transition in amplitude of the data.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: November 20, 2012
    Assignees: NEC Corporation, Elpida Memory, Inc.
    Inventors: Hideaki Saito, Hiroaki Ikeda
  • Patent number: 8299946
    Abstract: A noise shaper that compares an input signal to a feedback output signal, which is a truncated version of the input signal, and generates the difference between the two signals (i.e., the error). The noise shaper then integrates the errors by adding to the error multiple of its delayed versions, and quantizes the integrated errors in such a way that the spectrum of the quantization noise is shaped toward high frequencies to be removed by a LC low-pass filter used in conjunction with the noise shaper. The low frequency content of the desired signal is mostly unaffected.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: October 30, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eric Soenen, Alan Roth, Martin Kinyua, Justin Shi, Justin Gaither
  • Patent number: 8289034
    Abstract: A capacitance measurement circuit and a capacitance measurement method thereof. The capacitance measurement circuit for measuring a capacitor under test includes a capacitance to time unit, a continuous time integrator and an analog to digital converter. The capacitance to time unit generates a first clock signal and a second clock signal reverse to the first clock signal according to a first charge time of the capacitor under test and a second charge time of a variable capacitor. The continuous time integrator receives the first clock signal and outputs an integral signal according to the first clock signal. When the number of clocks of the second clock signal is equal to a default value, the analog to digital converter outputs a digital signal corresponding to a capacitance difference between the capacitor under test and the variable capacitor according to the integral signal.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: October 16, 2012
    Assignee: Raydium Semiconductor Corporation
    Inventor: Yu Kuang
  • Patent number: 8284088
    Abstract: A complementary pulse width modulation circuit is composed of a signal generating circuit 10 for generating first and second pulse width modulation signals (PWM#1 and PWM#2) that are complementary to each other from an input signal (IN) in response to a sampling synchronous signal (Sample) generated in synchronization with a clock (CLK); and a signal output circuit 20 for combining a positive signal and a negative signal of the first pulse width modulation signal (PWM#1) generated by the signal generating circuit, and for combining the first pulse width modulation signal (PWM#1) combined with the second pulse width modulation signal (PWM#2), followed by outputting.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: October 9, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kohei Teramoto, Tsuyoshi Nakada, Seiki Suzuki, Takahisa Aoyagi, Jun Yoshida, Ryoichi Hamahashi
  • Patent number: 8249129
    Abstract: Systems and methods are disclosed that provide ultra-wideband frequency hopping spread spectrum (UWB-FHSS) solutions for transmit and receive architectures. These UWB-FHSS transmit and receive architectures can transmit signals over an extremely wide bandwidth while using a relatively slow analog-to-digital converter (ADC) without suffering from unacceptable performance degradation. For example, ADCs can be used having sample rates lower than standard Nyquist criteria would require for the bandwidth of the spread spectrum utilized.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: August 21, 2012
    Assignee: L-3 Communications Integrated Systems L.P.
    Inventor: Gerald L. Fudge
  • Patent number: 8217820
    Abstract: A mixed signal processing circuit includes an analog to PWM converting circuit and a finite impulse response (FIR) filter having a multiple output tapped delay line and a summing and integration circuit. The mixed signal processing circuit converts an input analog signal to a PWM signal, forms a multi-level PWM signal from the PWM signal and one or more delayed versions of the PWM signal, and converts the multi-level PWM signal to an output analog signal. The analog to PWM converting circuit is implemented using a triangle waveform generator and a comparator. The FIR filter is implement using a resistive network to apply scaling coefficients of the FIR filter. The mixed signal processing circuit can be implemented within a noise cancellation headphone to generate a noise cancelling signal or generally in applications that would be benefitted from the combination of analog input/output and digital filter techniques.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: July 10, 2012
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Walter Y Chen
  • Patent number: 8212704
    Abstract: Aspects of the present disclosure relate to floating point timers and counters that are used in a variety of contexts. In some implementations, a floating point counter can be used to generate a wave form made up of a series of pulses with different pulse lengths. An array of these floating point counters can be used to implement a pool of delays. In other implementations, an array of floating point counters can be used to analyze waveforms on a number of different communication channels. Analysis of such waveforms may be useful in automotive applications, such as in wheel speed measurement for example, as well as other applications.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: July 3, 2012
    Assignee: Infineon Technologies AG
    Inventors: Ljudmil Anastasov, Jens Barrenscheen
  • Patent number: 8204703
    Abstract: Methods and devices to measure threshold voltages of electro-mechanical systems devices are disclosed. The threshold voltages are determined based on which of multiple test voltages cause the devices to change states. State changes of the device are detected by monitoring integrated current or charge used to drive the test voltages.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: June 19, 2012
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Alok Govil, Kostadin Djordjev, Alan Lewis, Wilhelmus Johannes Robertus Van Lier
  • Publication number: 20120146827
    Abstract: The invention relates to a method and a system for external, digital coding of a baseband or intermediate-frequency signal. Initially, a digital datastream is converted in a coding device into a digital-baseband signal in the time domain or into a digital intermediate-frequency signal in the time domain. The digitally generated signal is output via an asynchronous-serial interface of the coding device to another device. Such a device also provides an asynchronous-serial interface, which is connected to the asynchronous-serial interface of the coding device. The device reads in the output digital-baseband signal or intermediate-frequency signal for further processing.
    Type: Application
    Filed: August 3, 2010
    Publication date: June 14, 2012
    Applicant: ROHDE & SCHWARZ GMBH & CO. KG
    Inventors: Manfred Reitmeier, Cornelius Heinemann
  • Publication number: 20120119931
    Abstract: A device includes a digital-to-time converter and an interpolator having a data input and a data output coupled to the digital-to-time converter. The interpolator may be configured to receive a converter control signal at the data input and to provide an interpolated converter control signal at the data output. An interpolation rate of the interpolator may depend on the converter control signal.
    Type: Application
    Filed: November 14, 2011
    Publication date: May 17, 2012
    Inventors: Andreas Menkhoff, Zdravko Boos
  • Patent number: 8174543
    Abstract: A display device driving circuit includes: a grayscale signal output circuit, grayscale signal lines, a grayscale voltage output circuit, grayscale voltage lines, a digital-analog conversion circuit, a first to third switches. The grayscale signal output circuit outputs complementary signals as a digital grayscale signal. The grayscale signal lines receive the complementary signals. The grayscale voltage output circuit outputs analog grayscale voltages. The grayscale voltage lines receive the analog grayscale voltages. The digital-analog conversion circuit selects and outputs one of the analog grayscale voltages in response to the complementary signals. The first switch shuts off a first connection path between the grayscale signal output circuit and the digital-analog conversion circuit. The second switch shuts off a second connection path between the grayscale voltage output circuit and the digital-analog conversion circuit.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: May 8, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Koushirou Yanai
  • Patent number: 8144043
    Abstract: A signal converting system is described that has a multi-segment digital to analog converter coupled to one or more error shaping loops. Each error shaping loop includes a quantizer with a feedback loop configured to generate a control signal responsive to a stream of symbols and to an error signal. Each error shaping loop also includes an inter-symbol-interference (ISI) shaping loop coupled to receive the control signal and to produce an ISI portion of the error signal that is responsive to inter-symbol transition rate.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: March 27, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Lars Risbo, Rahmi Hezar, Burak Kelleci, Anker Bjoern-Josefsen
  • Patent number: 8144045
    Abstract: A timing signal generator circuit includes a DA converter converting an input digital value into an analog voltage, and a VT converter converting the analog voltage into a corresponding delay time. The DA converter includes a current source circuit, which supplies a current (n×Is) (“n” is a number corresponding to the input digital value) selected from a total supply current (N×Is) as a current Iout to the resistors, and supplies the remaining current (N?n)×Is as a current Idump to the resistors, outputs a voltage across the resistors as an analog voltage Vdac, and outputs a voltage across the resistor as a reset voltage Vreset. The VT converter charges the integration capacitor with a constant current from the constant current source by using the reset voltage as an initial voltage, and outputs a timing signal when the integral voltage exceeds the analog voltage.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: March 27, 2012
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Makoto Nagata, Takushi Hashida
  • Patent number: 8130128
    Abstract: In a particular embodiment, a circuit device is disclosed that includes a data generator adapted to output a random pulse sequence having a particular spectral shape. The data generator includes a feedback loop with a transfer function, the output of which may be altered by limiter circuitry to increase stability of the data generator. The circuit device may further include, for example, a pulse edge control circuit to selectively apply a carrier suppression operation to at least one pulse-width modulated (PWM) signal in response to the random pulse sequence to produce at least one modulated PWM output signal. In such an example, the spectral energy associated with a PWM carrier of the modulated PWM output signal at a carrier frequency and associated harmonics is changed such that the modulated PWM output signal has a spectral shape defined by the particular spectral shape.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: March 6, 2012
    Assignee: Silicon Laboratores Inc.
    Inventor: Jeff D. Alderson
  • Patent number: 8125365
    Abstract: A generation method of an analogue signal generated by a PWM signal whose cyclic ratio and period are parametrizable is discussed. It is thus possible choose the pair formed from the cyclic ratio and the period producing an analogue value that is the closest to the value corresponding to the programmed command value. But the differences between the analogue values can be very great and generate zones of imprecision of variable width. Outside of these zones, the generated analogue signal is very precise. Therefore, when the command value associated with a pair is imprecise, a digital shift is applied to the command value at the same time as the application of an analogue shift means. Both shifts have the same amplitude and of opposite directions such that the cancel each other out, producing a precise analogue value. A device for generating an analogue signal implementing the method is also discussed.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: February 28, 2012
    Assignee: Thomson Licensing
    Inventors: Philippe Mace, Xavier Guitton, Philippe Benezeth
  • Patent number: 8125366
    Abstract: A current source is used to pre-charge a capacitor to a known value. The capacitor can then be connected to a unity gain buffer to provide a low cost DAC. The DAC can include a self-calibration stage to improve accuracy. The DAC can include two or more circuit branches, each including a current source and a capacitor, where each branch can be calibrated and operated separately to reduce mismatch and to provide a continuous analog voltage output.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: February 28, 2012
    Assignee: Atmel Corporation
    Inventor: Trond Jarle Pedersen
  • Patent number: 8115663
    Abstract: In an embodiment, a digital-to-analog converter (DAC) includes inputs for receiving first and second signals encoded as a digital signal pair including overlapping low value portions that are substantially equal in duration to overlapping high value portions, within a frame. The DAC further includes an output terminal for providing an analog signal and includes first and second switches responsive to the first and second signals alter a level of the analog signal based on values of the first and second signals to provide a mismatch-immune DAC functionality. In one instance, the switches couple current sources to a common node. In another instance, the switches configure a resistive network to alter a resistance at an input to an amplifier.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: February 14, 2012
    Assignee: Silicon Laboratories Inc.
    Inventor: Joao Pedro Santos Cabrita Marques
  • Publication number: 20120001785
    Abstract: A timing signal generator circuit includes a DA converter converting an input digital value into an analog voltage, and a VT converter converting the analog voltage into a corresponding delay time. The DA converter includes a current source circuit, which supplies a current (n×Is) (“n” is a number corresponding to the input digital value) selected from a total supply current (N×Is) as a current Iout to the resistors, and supplies the remaining current (N?n)×Is as a current Idump to the resistors, outputs a voltage across the resistors as an analog voltage Vdac, and outputs a voltage across the resistor as a reset voltage Vreset. The VT converter charges the integration capacitor with a constant current from the constant current source by using the reset voltage as an initial voltage, and outputs a timing signal when the integral voltage exceeds the analog voltage.
    Type: Application
    Filed: July 1, 2010
    Publication date: January 5, 2012
    Inventors: Makoto NAGATA, Takushi Hashida
  • Patent number: 8067927
    Abstract: A control circuit for a multi-phase converter including an analog front-end circuit for receiving and processing an output voltage and current of the converter circuits and an average output current; a digital circuit for producing an output voltage reference for setting a desired output voltage of the converter; and an error circuit for comparing the output voltage reference and a parameter related to said output voltage and current for generating control signals for controlling the converter circuits, said error circuit including an Analog to Digital Converter circuit, further comprising a digital PWM generation circuit controlled by said Analog to Digital converter circuit for generating digital control signals for controlling the converter circuits.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: November 29, 2011
    Assignee: International Rectifier Corporation
    Inventors: Wenkai Wu, George Schuellein