Abstract: A pulse-width-modulated digital-to-analog converter is responsive to a digital control value for switching between a high gain mode and a low gain mode. The converter includes a free-running rollover counter, a reference register and a comparator. Pulses from a comparator are split into two paths, one path including a switch, and fed into a plurality of resistive elements connected connected to a common output node. Depending on the state of the switch, the network's output value will either follow its input or be a fraction thereof, without change of duty cycle or output impedance. The output node may be connected to a capacitive element to form a low pass filter for generating an analog waveform.

Abstract: The invention concerns an arrangement including a microprocessor controller, PROM memory, and a digital to analog converter (DAC) arrangement for generating a plurality of control voltages for trimming respective ones of a plurality of varactor controlled tunable filters. The controller couples digital control signals to the respective DACs which generate respective analog control voltages which are applied to the respective tunable filters. A tuning voltage generated by a closed control loop, such as phased locked loop also under the control of the controller, is combined with the output control voltages generated by the respective DAC's in a resistance divider arrangement.

Abstract: A system uses a charge storage unit to produce shaped pulses in response to an incoming digital signal. The system detects transitions or patterns in the digital signal and produces a charging waveform that controls the charge maintained in the charge storage unit, and thus, the instantaneous value of an output voltage produced by the unit. The charging waveform is, in turn, controlled by transition characteristics or counts that are stored, respectively, in transition memories. In the case of a binary transmission the memories contain rising and falling characteristics. These memories are addressed by addresses generated in response to the detection of a pattern, or as appropriate, a transition in the incoming digital signal. The charging waveform may be a series of pulses with varying widths, a signal that has a variable duty cycle, or a varying pulse count. The charging waveform controls the charging of capacitors in the charge storage unit, which consists essentially of cascaded low pass filters.

Abstract: The process of converting a digital data word having N-bits into an analog voltage value includes decrementing or incrementing a counter word (B) having N-bits from a respective maximum or minimum value to form a series of decremented or incremented values, synchronizing the decrementing or incrementing of the counter word (B) to a time course of an analog reference voltage (U.sub.ramp) having a ramp-shaped time dependence, evaluating a logical connection function of the decremented or incremented values of the counter word (B) with a digital data word (A) to determine when one of the decremented or incremented values of the counter word (B) is equal to a complement of the digital data word (A) and setting an output analog voltage value (U.sub.column) equal to the analog reference voltage (U.sub.ramp) as soon as the decremented or incremented value of counter word (B) equal to the complement of data word (A) is reached.

Abstract: A 1-bit D/A conversion circuit according to the present invention comprises an RZ signal generating circuit and a PRZ signal generating circuit. The RZ signal generating circuit receives 1-bit digital data sampled at a predetermined frequency, converts the digital data into a first RZ signal and a second RZ signal complementary to the first RZ signal, shifts the first and second RZ signals with respect to each other by an integral multiple of the predetermined frequency, which is greater than one, and outputs these RZ signals. The PRZ signal generating circuit receives the first and second RZ signals, combines these signals together, and outputs a signal which is a type of a PRZ signal.

Abstract: A system and method for the conversion of digital signals to analog signals increases the resolution of the output analog signal beyond the analog quantization size associated with the given input digital word length. The rate of change of the Least Significant Bits (LSB)is detected. The "square waves" produced by changes in the polarity of the LSB correspond to low amplitude signals comprising audible high frequency components. The high frequency noise associated with these detected low signal levels is attenuated by digital low pass filters of varying cut-off frequencies at the output stage. This creates a signal of a resolution higher than the step size inherent in the length of the input digital word, and reduces high frequency noise at low signal amplitudes, resulting in a smooth analog output signal.

Abstract: The D/A converter comprises: a digital counter receiving a reference clock pluses and a reference voltage as a start signal so as to output a stop signal when the digital counter counts the reference clock pulses until a predetermined number; and a number is reached, and an RC circuit having a resister and a capacitor receiving the reference voltage so as to be charged by a predetermined time constant until the stop signal is inputted to the RC circuit, whereby the RC circuit is charged up to a voltage corresponding to a time distance between the start signal and the stop signal.

Abstract: A more accurate voltage-to-time and then time-to-voltage conversion is accomplished by tailoring the amplitude versus time characteristics of the pulses generated in the voltage-to-time conversion. One embodiment includes applying a ramped voltage supply to an amplifier coupled between the voltage/time converter and the time/voltage converter. The ramped supply is arranged to condition the amplitude of a portion of respective pulses to include a slope similar to the ramped voltage applied to the time/voltage converter. This tends to effect a more accurate response in the time/voltage converter.

Abstract: A digital-to-analog converter (DAC) for generating a pulse width modulated (PWM) signal. A dual-DAC implementation includes a read-only memory (ROM) containing a plurality of addressable output signals, respective shift left and shift right registers configured to simultaneously receive an output signal from the ROM, and respective first and second DACs are configured to receive the left shifted output and right shifted output, respectively, from the shift left and shift right registers. Both DAC outputs are applied to an analog summer which generates an output signal indicative of the sum of the outputs from the two DACs.

Abstract: An integrating D-A/A-D converter includes a reference value generation circuit for generating at least one reference value relating to voltage or current, a control circuit for carrying out switching between a digital or analog input and the reference value every predetermined time to connect a switched one to thereby control an integral time, and an integration circuit for respectively integrating an analog value corresponding to the digital or analog input and the reference value switched in sequence every predetermined time and delivered through the control circuit to output an integral value for providing a digital or analog output.

Abstract: A pair of equilibrium output signals P(+) and P(-) from a 1-bit D/A converter IC, which is made up of an oversampling filter, noise shaper and a pulse converter, are supplied to a pair of field effect transistors connected in a common drain configuration. A constant current I.sub.0 is supplied to the common drain from a constant current source and at least one of the source output currents is converted by an output circuit into a voltage. In this manner, a 1-bit D/A converted output signal freed of fluctuations of the power source is provided at an output terminal.

Abstract: The digital-to-analog conversion apparatus operates in synchronization with a system clock signal having a short period to oversample and delta-sigma-modulate a digital input to produce a requantized digital signal. The system clock signal is mixed with noise leaked back due to the oversampling and delta-sigma modulating operation. The system clock signal is frequency-divided by the rate of one-fourth or less to produce a divided clock signal having a long period and being free of the noise. The requantized digital signal is detected each long period, and is pulse-modulated according to the detected results to generate a pulse signal having the long period. This pulse signal is low-pass-filtered to produce an analog output having improved S/N ratio.

Abstract: A digital-to-analog converter (20) includes a linear interpolator (24) and a converter (25, 26) such as a sigma-delta modulator (25) and an associated analog summing network (26). The linear interpolator (24) includes a differentiator (200), an integrator (202), and a multiplexer (201). The differentiator (200) differentiates a received signal at a first rate. The multiplexer (201) multiplexes an output of the differentiator (200) to provide a multiplexed signal having a larger number of bits than the received signal in order to support multiple interpolating ratios. The integrator (202) integrates the multiplexed signal at a second rate to present to the converter (25, 26). By connecting the multiplexer (201) between the differentiator (200) and the integrator (202), the digital-to-analog converter (20) minimizes the size of the linear interpolator (24) while relieving a critical path between the linear interpolator (24) and the converter (25, 26).

Abstract: A sigma-delta digital-to-analog converter (20) reduces even order distortion, such as a DC offset, in an output signal by chopping the output signal alternately with set and reset pulses. The sigma-delta digital-to-analog converter (20) includes a sigma-delta modulator (25), a chop circuit (261) associated with a corresponding bit of the sigma-delta modulator (25), and an output buffer (264) for providing the output signal. The chop circuit (261) alternately inserts first and second logic levels into an output data stream of the sigma-delta modulator (25) before providing it to the output buffer (264). Even-order distortion is eliminated with only a tolerable attenuation of the output signal.

Abstract: A dual-ranked time-interval conversion circuit. Two time trap circuits are employed to convert the time interval between a logic level transition of a first signal and a logic level transition of a second signal to an analog or digital signal representative of that time interval. Each time trap circuit employs a delay line for receiving and propagating the first signal and a series of taps and respective storage elements along the delay line for detecting and storing the logic level of the delay line at each tap at the time of receipt of a second signal. A first time trap circuit is employed to measure the time interval in course quanta of time and a second time trap circuit is employed to measure in fine quanta of time the time difference between the actual first signal-to-second signal time interval and the coarse measurement of that interval.

Abstract: The present invention relates to a pulse width modulation (PWM) decoder, and more particularly to a PWM decoder which demodulates a pulse width modulated signal for proper interface with the operational characteristics of an object to be controlled. The present invention includes a PWM input terminal for receiving a PWM signal, an integrator for converting the PWM signal to a linear analog signal, and a transfer characteristic converter for changing the slope of the transfer characteristic of the integrator, so that a microcomputer can be interfaced with a signal processor without changing the microcomputer's internal design.

Abstract: A digital-to-analog converter utilizing a PWM system for converting input digital data to PWM signals and finally to an analog signal divides the sampling period of the input digital data into an even number of sampling periods and produces PWM signals with equal pulse widths corresponding to the input digital data each divided sampling period, whereby a simple structure is provided to reduce harmonic distortion and obtain a high quality analog signal.

Abstract: A CMOS circuit for averaging digital-to-analog converters includes a shift register of series-connected master and slave cells controlled by a shift clock. The input of the shift register is supplied with a pulse-density-modulated data signal, and the outputs of each of the master and slave cells are connected to a data-dependent control input of a multistage gate circuit. The gate circuits are controlled by a gate clock and cause constant currents to be switched via two buses to the input and output of a p-channel current mirror in accordance with the state of the master or slave cell. The input of a current mirror is constantly supplied with one-half the sum current of the constant-current sources, and the current mirror provides current scaling, preferably by a factor of 0.5.

Abstract: A current-integrating analog-to-digital converter includes a comparator having a non-inverting input coupled to a ground voltage and an inverting input coupled to an input conductor carrying an analog input current. An integrating capacitor having one terminal coupled to the input conductor and another terminal coupled to an output of a digital-to-analog converter. A tracking circuit is coupled to an output of the comparator to apply digital signals to inputs of the digital-to-analog converter to maintain the inverting input close to a virtual ground voltage. A digital filter filters the digital signals to produce a digital output signal that precisely represents the input current.

Abstract: A digital control circuit with a device for generating a high-resolution tuning voltage is suitable for use in receivers for RF signals, particularly in consumer equipment. The tuning voltage can be electronically switched from one value to another at a high speed. The transient time required with conventional control loops is nearly eliminated since the low-pass filter or the digital integrator is preset to its steady-state integration value. To generate the tuning voltage, dynamic digital-to-analog convertors are provided which, despite their high resolution, require only a smoothing filter with a short response time and a short time constant.

Abstract: A decoder for decoding a delta-modulated code represented with binary digit "1" or "0" to convert it into an analog signal, wherein when the delta-modulated code takes the first value ("1" or "0"), a positive pulse signal is applied to an integrator to increase its accumulated value by a constant value and when the delta-modulated code takes the second value ("0" or "1"), a negative pulse signal is appied to the integrator to decrease its accumulated value by the constant value, and this accumulated value of the integrator is outputted as an analog signal which corresponds to a code train of the delta-modulated code. The decoder is characterized in that it has a pulse width modulater which limits an effective pulse width of the pulse signal by performing pulse width modulation of the positive or negative pulse signal in response to a control signal.

Abstract: In a digital-to-analog converter for converting a received digital signal having N bits and a sampling frequency fs to an analog signal; digital interpolation filter receives the digital signal and generates a modified digital signal having a number of bits less than N and a sampling frequency greater than fs, pulse width modulator receives the modified digital signal and generates a pulse signal having pulse widths which correspond to the modified digital signal, output buffer having a complementary metal oxide semiconductor (CMOS) inverter circuit including P channel and N channel transistors having respective resistance values receives the pulse signal and low-pass filter receives the output signal from the output buffer, wherein the digital interpolation filter, the pulse width modulator and the output buffer are formed in an integrated circuit, and when the transistors are conductive the resistance values of the P channel and N channel transistors are set equal to each other by adjusting a voltage applie

Abstract: A PWM digital-to-analog converter is disclosed in which a value representing a differential between a first pulse width modulated waveform based upon input digital data and a second pulse width modulated waveform representing a 2's complement version of the input digital data is produced by a differential amplifier and high frequency components thereof are attenuated to produce an analog output signal and with an improved distortion factor.

Abstract: A PWM type D/A converter having a first PWM converter, a second PWM converter and an analog adder. The digital input signals are designated as odd and even numbered input signals and the reference timing points for outputting odd/even numbered input signal are designated as odd/even numbered reference timing points. The first PWM converter receive the digital input signal to output signal whose rising/falling timing point is set at the earlier/later timing, the larger the value of the odd/even numbered input signal relative to the odd/even numbered reference timing point and the pulse width is determined by the values of the odd numbered input signal and the next even numbered input signal.

Abstract: A data generator generates digital data at a sampling time interval .sub..DELTA. T (sampling frequency f.sub.s =1/.DELTA.T), and the three latest items of digital data V.sub.-1, V.sub.0, V.sub.+1 are repeatedly latched successively in three latch circuits every 3.multidot..sub..DELTA. T. A pulse response signal generator outputs unit pulse response signals of period 3.multidot..sub..DELTA. T at the time interval .multidot..sub..DELTA. T, and three multiplying-type DA converters multiply these three unit pulse response signals .phi..sub.0 (t+.sub..DELTA. T), .phi..sub.0 (t), .phi..sub.0 (t-.sub..DELTA. T) by the digital data V.sub.-1, V.sub.0, V.sub.+1, respectively, at a speed of a.multidot.f.sub.s (a times in time .sub..DELTA. T). The outputs of these multiplying-type DA converters are combined into an analog signal S.sub.A, which is delivered as an output.

Abstract: A voltage coupling circuit for use in a digital-to-time converter insures that converter operation is stabilized against temperature and power supply variations. The digital-to-time converter operates by comparing a ramp voltage to a threshold voltage that is set in accordance with an input digital word. The voltage coupling circuit, which causes the ramp voltage to track changes in the threshold voltage, includes a current mirror arrangement that separates the voltage coupling and ramp generation functions. As a result, transistor base currents are not drawn through the ramp capacitor, and accuracy is improved in the case of long time delays.

Abstract: A precision ratioed digital-to-analog data converter. A first latch stores a first digital word having a first numerical value and a second latch stores a second digital word having a second numerical value. A down counter alternately receives data from the first and second latches and is connected to a flip flop device to produce a waveform signal having first and second pulse components of opposite polarity. The first and second pulse components have a duration proportional to the first and second digital words. The output waveform is then inverted through an inverter comprising matched P and N channel MOSFETS. The inverted waveform is then presented to an RC integrator circuit which produces a DC signal. The DC signal is passed through a buffer amplifier connected in a voltage follower configuration.

Abstract: Pulse modulation circuitry which receives n binary data bits and generates a rate/width pulse modulated signal representing the binary value of the received data bits. The lower order m of the n bits generate a rate modulated signal having a number of pulses equal to the binary value of the m bits. The remainder of the n bits width modulate the rate modulated pulses. Each least significant bit increase in the binary value of the received date bits increases the width of a rate modulated pulse by a predetermined amount.

Abstract: An apparatus is provided which is responsive to a multiple bit sample of digital information for producing a pulse width modulated signal, the apparatus comprising: a first signal match detector, responsive to a first subset of the multiple bit sample, for producing a first signal that can transition between first and second logical states; a second signal match detector, responsive to a second subset of the multiple bit sample, for producing a second signal that can transition between the first and second logical states; and a voltage summing circuit for producing a first voltage that is substantially proportional to a magnitude of the first signal in one of the first logical state and the second logical state and for producing a second voltage that is substantially proportional to a magnitude of the second signal in one of the first logical state and the second logical state and for producing an output voltage that is substantially proportional to a sum of the first voltage and the second voltage.

Abstract: A digital-to-analog converter comprising: a distributing circuit (2, 3, 4, 5; 2, 13, 14-26) for distributing data pulses, which are bit-serially supplied at constant time intervals, into a plurality of routesand for providing them as pulses having a constant width; and a converting circuit (12) for adding together the pulses from the distributing circuit and thereby for converting them to an analog output. Such a circuit arrangement can provide pulses for conversion to analog form which all have an identical waveform and an identical area, and errors caused by the difference between the rise and fall times of the pulses can be eliminated and therefore D/A conversion characteristics can be improved.

Abstract: A digital-to-analog converting device, particularly useful in audio device such as compact disc players, including an adder (CA; CA1, CA2) for adding a common random data to a digital data (d) supplied at a constant period and to a sign-reversed data (d), respectively. The signals containing the added random data are converted into analog form by a digital-to-analog converter (DT; DT1, DT2). The difference is taken between the analog signals obtained from the digital data (d) containing the added random data and the sign-reversed data (d) containing the added random data. Such circuit arrangement can provide an analog ouput signal having an amplitude which is twice as large as that obtained by the prior art and yet the resistance thermal noise contained in such analog signal has a reduced relative magnitude, whereby an improvement in signal-to-noise ratio and in tone quality can be achieved.

Abstract: A circuit and method for converting a binary number having a plurarity of bits, D.sub.o to D.sub.n, to a signal having a proportionally equivalent characteristic. The circuit comprises a parallel input for receiving each bit, D.sub.o to D.sub.n, of the binary number and means for generating a plurarity of wavetrains, W.sub.o to W.sub.n, having frequencies decreasing by powers of two from the least significant wavetrain, W.sub.o, to the most significant wavetrain, W.sub.n. Each wavetrain comprises pulses having a pulse width equal to the inverse of twice the frequence of the least significant wavetrain, W.sub.o, so that the duty cycle of each of the wavetrains is proportional to the corresponding frequency thereof. The pulses of each of the wavetrains are not overlapping with the pulses of the other wavetrains. The circuit also comprises logic means, connected to the input and the generating means, for logically multiplying each wavetrain taken in an order from the least significant to the most significant, W.

Abstract: An integration type D/A and A/D converter having improved linearity and low power consumption. Logic circuits such as ECL counters consuming a major part of power of the D/A and A/D converters are realized through CMOS process. Current source circuits, current switch circuit and comparator circuit of the integration type A/D converter are realized in IC through bipolar process ensuring high accuracy and low noise. Logic parts such as counter is realized through CMOS process.