Abstract: A filter stage system, includes a continuous time baseband filter comprising a feedback loop that employs at least one first impedance node and at least one second impedance node, wherein the at least one first impedance node has a higher impedance than the at least one second impedance node, and wherein the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole, and wherein the continuous time baseband filter generates a filtered current, and a mirroring component mirrors the filtered current to an output.

Abstract: A low-power display device is provided. The display device is provided with a plurality of display portions. A data driver circuit and an addition circuit are provided to have a region overlapping with the display portion. First analog data is output from the data driver circuit in the case where first digital data consisting of a first digital value is input to the data driver circuit, whereas second analog data is output from the data driver circuit in the case where second digital data consisting of a second digital value is input to the data driver circuit. The addition circuit generates analog data corresponding to digital data that has a high-order bit that is the first digital value and a low-order bit that is the second digital value, by adding the second analog data to the first analog data. An output terminal of the data driver circuit is directly connected to an input terminal of the addition circuit without through an amplifier circuit.

Abstract: A pixel compensation method includes determining an actual driving digital voltage of each organic light-emitting sub-pixel in a detection row; performing mean value calculation based on the actual driving digital voltage of each organic light-emitting sub-pixel in the detection row to determine an average driving digital voltage corresponding to the detection row; calculating a voltage difference between the actual driving digital voltage of the organic light-emitting sub-pixel in the detection row and the average driving digital voltage, and counting the voltage differences to form a voltage difference set; and outputting a corresponding data compensation analog voltage to the organic light-emitting sub-pixel in the detection row when an absolute value of a maximum voltage difference in the voltage difference set is greater than or equal to a target threshold. The pixel compensation method of this disclosure can improve the uneven display and improve the display effect.

Abstract: A photoelectric conversion device comprising a pixel unit in which a plurality of pixels each comprising a photoelectric conversion element are arranged in a matrix, and a plurality of delta-sigma AD converters each configured to convert a signal output from the pixel unit into a digital signal, is provided. The plurality of delta-sigma AD converters are divided into at least two groups having different timings of starting AD conversion from each other when converting, into digital signals, signals output from the pixels selected out of the plurality of pixels via a common pixel control line.

Abstract: An ADC system dynamically adjusts threshold levels used to resolve PAM signal amplitudes into digital values. The ADC circuitry includes an analog front end to receive and condition the PAM signal, a low-resolution ADC to digitize the conditioned signal according to a first set of threshold values, and a high-resolution ADC to subsample the conditioned signal to generate subsampled signals. A microprocessor in communication with the low-resolution ADC and the high-resolution ADC derives a statistical value from the subsampled signals, determines an updated set of threshold values, and dynamically replaces the first set of threshold values for the low-resolution ADC with the updated set of threshold values.

Abstract: An amplifying circuit, which can operate in one of a sample mode and a hold mode, comprising: an amplifier; a current providing circuit, configured to provide a first bias current to the amplifier in a power saving time interval when the amplifying circuit operates in the sample mode, and configured to provide a second bias current to the amplifier when the amplifying circuit operates in the hold mode; wherein the first bias current is smaller than the second bias current.

Abstract: A semiconductor integrated circuit includes a first MOS transistor, a second MOS transistor, and a P+ region. The first MOS transistor is an NMOS transistor which has a first N-type region and a second N-type region and in which a first power supply voltage is supplied to the first N-type region. The second MOS transistor is an NMOS transistor which has a third N-type region and a fourth N-type region and in which a second power supply voltage higher than the first power supply voltage is supplied to the third N-type region. The P+ region is supplied with the first power supply voltage. In plan view of the semiconductor substrate, the first MOS transistor and the second MOS transistor are disposed to be adjacent to each other, and the P+ region is located between the first N-type region and the third N-type region.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for content addressable memory (CAM) cells. Each CAM cell may include a comparator portion which stores a bit of information. Each CAM cell may also include a comparator portion, which compares an external bit to the stored bit. A group of CAM cells may be organized into a CAM register, with each CAM cell coupled in common to a signal line. Any of the CAM cells may change a voltage on the signal line if the external bit does not match the stored bit.

Abstract: An analog-to-digital converter configured to convert an analog signal into a digital signal includes a first converter configured to receive an input signal of an analog type, compare the input signal with a plurality of reference signals, select one of the plurality of reference signals based on the comparison, and output an upper bit that is a portion of the digital signal based on the selected reference signal, a second converter configured to perform an oversampling operation n times based on a residue signal indicating a difference between an upper analog signal corresponding to the upper bit value and the input signal and output an intermediate bit value of the digital signal corresponding to the first to n-th oversampling signals generated respectively during the oversampling operations performed n times, and a third converter configured to output a lower bit value of the digital signal corresponding to the n-th oversampling signal.

Abstract: A device includes a capacitive digital to analog converter (CDAC) that further includes a plurality of capacitors to sample an analog input signal. The sampled analog input signal is converted into a digital signal and the digital signal is stored by a successive approximation register (SAR). Thereafter, the SAR regenerates the stored digital signal to a reset plurality of capacitors, and a comparator is configured as an amplifier to generate an equivalent analog voltage of the stored digital signal.

Abstract: A vehicular sensing system includes a radar sensor having a field of sensing exterior of the vehicle, a plurality of transmitters that transmit radio signals, a plurality of receivers that receive radio signals. The radar sensor includes a first ADC, a second ADC, a DAC and a subtractor. The first ADC converts an analog input signal derived from the received radio signals into a first number of bits. The DAC converts the first number of bits into a first analog signal. The subtractor subtracts the first analog signal from the input signal to determine a second analog signal. The second ADC converts the second analog signal into a second number of bits. The first and second numbers of bits are appended to establish a total number of bits that represent a digital value of the voltage of the analog input signal.

Abstract: A device to read a variable resistor has an analog to digital converter (ADC), a first switch and a second switch. The ADC has a first ADC input, a second ADC input and an ADC output. The first switch selectively couples a first voltage indicative of a voltage across a first resistance to the first ADC input. The second switch selectively couples a second voltage indicative of a voltage across a second resistance to the second ADC input. The ADC outputs a signal indicative of a value of the second resistance.

Abstract: A coherent optical modem includes one or more inputs; one or more amplifier circuits, each coupled to a respective input of the one or more inputs; and one or more receiver circuits each including an analog-to-digital converter, each coupled to a respective amplifier circuit of the one or more amplifier circuits; wherein the one or more amplifier circuits are configured to implement an automatic gain control loop to provide a constant signal amplitude at an input of the analog-to-digital converter of a respective receiver circuit.

Abstract: An apparatus for calibrating a time-interleaved analog-to-digital converter including a plurality of time-interleaved analog-to-digital converter circuits is provided. The apparatus includes a clock generation circuit configured to generate a plurality of phase shifted clock signals for the plurality of time-interleaved analog-to-digital converter circuits and a reference clock signal. Further, the apparatus includes a reference signal generation circuit configured to generate a reference signal based on the reference clock signal. The reference signal is a square wave signal. The apparatus additionally includes a coupling circuit configured to controllably couple an input node of the time-interleaved analog-to-digital converter to either the reference signal generation circuit or to a signal node capable of providing an analog signal for digitization.

Abstract: An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to output a first digital value corresponding to an analog input voltage. A current steering DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first current signal and the second current signal in the current domain, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values into a digital output voltage.

Abstract: A family of current mode analog to digital converters, or TiADC, utilizing methods, circuits, and apparatuses, are disclosed with the following benefits: (1) There are normal and random non-systematic mismatch between devices in silicon manufacturing, that introduce non-linearity in current mode analog to digital converter's, or iADC, reference network. The iADC's linearity is improved by utilizing a thermometer current mode signal conditioning method, SCM. Successive applications of the SCM effectuates a segmented current reference network to function like a thermometer network, which operates based on the function of summation. Having a TiADC with a thermometer reference network, where current segments are summed or accumulated incrementally, would inherently reduce the impact of statistical distribution of component's random mismatch on the iADC's non-linearity.

Abstract: An A/D converter includes multiple bin comparators that compare an analog voltage to corresponding bin threshold voltages to provide output signals for providing corresponding comparison results. Some of the comparators includes enable inputs that selectively enable the output signal of the bin comparator to provide the corresponding comparison result based on a corresponding comparison result from at least one other bin comparator. The A/D convertor includes an encoder that utilizes the output signals to provide encoded bit values of the digital output. The A/D converter includes a bin selection circuit that utilizes the output signals to select a voltage level based on the output signals and provides the selected voltage level to a next stage of the A/D convertor. The next stage uses the selected voltage level and the analog voltage to provide at least one lessor bit of the digital output.

Abstract: An analog-to-digital converter includes a cycle processing unit and a control unit. The cycle processing unit converts an analog input signal into a digital signal having a plurality of bits by performing a plurality of cycle processing on the analog input signal to acquire values of each bit in order from a higher-order bit to a lower-order bit. The control unit controls the cycle processing unit such that a period of the cycle processing is shortened according to a cycled number of the cycle processing.

Abstract: A device includes a capacitive digital to analog converter (CDAC) that further includes a plurality of capacitors to sample an analog input signal. The sampled analog input signal is converted into a digital signal and the digital signal is stored by a successive approximation register (SAR). Thereafter, the SAR regenerates the stored digital signal to a reset plurality of capacitors, and a comparator is configured as an amplifier to generate an equivalent analog voltage of the stored digital signal.

Abstract: An analog-to-digital converter including a first stage and a second stage. The first stage includes a first sample-and-hold (SH) having an input coupled to a voltage input node of the ADC, and having a first SH output. The first stage also includes a buffer, a first flash converter and a first digital-to-analog converter (DAC). The buffer has an input coupled to the first SH output and has a buffer output. The first flash converter has an input coupled to the first SH output, and has a first flash converter output. The first DAC has an input coupled to the first flash converter output. The second stage includes a second flash converter having an input coupled to the buffer output.

Abstract: A disclosed analog-to-digital converter includes; a sampling circuit to sample a pair of analog signals as a differential input signal; a binary capacitance holding the sampled pair of analog signals and reflecting a level of a reference signal to the analog signals through the binary capacitance to generate a pair of voltage signals; a comparator including a transistor to which the voltage signals are input, to compare one of the voltage signals with the other; a correction circuit provided previously to the comparator, to output to the comparator the pair of voltage signals in which voltage dependency of stray capacitance in the input transistor is cancelled; and a controller that successively determines a value of each bit of a digital signal corresponding to the binary capacitance based on a comparison by the comparison circuit, and reflects the value of each bit of the digital signal to the reference signal.

Abstract: An analog-to-digital converter (ADC) and a method are disclosed. The ADC has a quantizer. The quantizer comprises a linear-feedback shift register (LFSR), a decoder configured to provide a plurality of switch control signals at a plurality of decoder outputs, respectively, the plurality of switch control signals responsive to a LFSR value of the LFSR output; an electrical reference, the electrical reference having a plurality of reference outputs, the electrical reference configured to provide a plurality of reference levels at the plurality of reference outputs, respectively; a first switch providing a first switch output and a second switch output; and a comparator, the comparator having a signal input, a first reference input, and a second reference input, the first reference input connected to the first switch output, and the second reference input connected to the second switch output.

Abstract: A pipeline ADC architecture with suitable feedback can implement noise shaping. By feeding back the residue generated by the last residue generating stage to selected locations in the pipeline ADC, the delays in a pipeline ADC can create a finite impulse response (FIR) filtered version of the quantization error. The FIR filtered quantization error is added to the signal and evaluated by the pipeline ADC, which results in spectral shaping of the quantization noise. Unlike a conventional pipeline ADC, the output of the backend stage is scaled and filtered by a noise transfer function (NTF) of the residue generating stages prior to combining the output with other outputs of the pipeline ADC. The processing of the shaped quantization noise by the backend stage results in further noise suppression.

Abstract: An analog-to-digital converter (“ADC”) has an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and an analog residue signal corresponding to a difference between the first digital value and the analog input signal. A second ADC stage is coupled to the first ADC stage and is configured to convert the analog residue signal to a second digital value. At least one of the first ADC stage and the second ADC stage includes a first sub-stage configured to convert an analog signal to a first number of bits of a digital value representing the analog signal, and a second sub-stage configured to convert the analog signal to a second number of bits of the digital value, where the second number of bits is greater than the first number of bits.

Abstract: A reference voltage sub-system that allows fast power up after spending extended periods in an ultra-low power standby mode. The reference voltage sub-system includes a reference voltage buffer, a reference voltage keeper, an active calibration facility for selectively adjusting the reference voltage keeper output to match the reference voltage buffer output, and a selection means for selecting between the reference voltage buffer output and the reference voltage keeper output.

Abstract: Disclosed is a successive approximation register (SAR) quantizer and a continuous-time sigma-delta modulator (CTSDM) using the SAR quantizer. The SAR quantizer is capable of generating M highly-significant bits as a digital output signal, and generating L lowly-significant bit(s) for the execution of noise shaping operation. Therefore, the SAR quantizer and the CTSDM can reduce the demand for the circuit area of a digital-to-analog converter and lower the delay of a critical path, so as to improve the performance and cut the cost.

Abstract: A voltage detector includes a comparison unit which is equipped with a plurality of comparators and which is configured to compare a threshold voltage and determination voltages corresponding to each comparator and output a first result of High or Low for each comparator and configured to compare an input voltage and the determination voltages and output a second result of High or Low for each comparator, and a determination unit configured to determine based on the first result and the second result whether or not the input voltage is less than or equal to the threshold voltage.

Abstract: A variable resistor may be coupled between a reference voltage source and components of an integrated circuit to reduce issues relating to thermal noise from a reference voltage signal generated by the reference voltage source. The variable resistor may be set to a low level during a first time period and a high level during a second time period, in which the time periods correspond to a sampling period of a switched-capacitor circuit. The low resistance time period may allow quick settling of an input reference voltage signal, whereas the high resistance time period may reduce a bandwidth of noise on a sampling capacitor coupled to the reference voltage signal. The variable resistor and switched-capacitor network may be used in an analog-to-digital converter (ADC), such as in audio circuits.

Abstract: An analog-to-digital converter ADC and a method to convert an analog input signal into a digital output signal comprising N bits on, n?{0, . . . , N?1} is presented. The ADC contains a controller, a digital-to-analog converter DAC, and a comparator. The comparator generates a binary signal by comparing the analog input signal with an analog output signal of the DAC. The controller receives the binary signal generated by the comparator and generates, based on the binary signal, a digital control signal comprising N bits cn, n?{0, . . . , N?1}. The DAC generates the analog output signal based on the digital control signal generated by the controller. The controller has a register which stores a previous sum value and an adder to determine a test sum value by adding.

Abstract: The present disclosure provides a digital to analog conversion (DAC) circuit and a data source circuit chip, the DAC circuit includes: first MOS tubes with the same number of the inputted digital bits; a second resistance, one end of the second resistance connects to the reference voltage, another end of the second resistance connects to the output terminal of the circuit; a second MOS tube, the drain of the second MOS tube connects to the output terminal of the circuit, the gate of the second MOS tube receives a row blank signal; and a capacitor, one end of the capacitor connects to the output terminal, another end of the capacitor is grounded. Using the above circuit and data source circuit chip, can greatly reduce the number of the MOS tube used in the DAC circuit, to effectively reduce the volume of the data source circuit chip and cost.

Abstract: An A/D converter includes an analog input terminal, a successive approximation A/D converter connected to the analog input terminal, the successive approximation A/D converter for generating an upper conversion result at an upper conversion result terminal, the successive approximation A/D converter having an internal D/A converter generating an internal reference voltage at an internal reference voltage terminal, and a delta-sigma A/D converter connected to the analog input terminal and the internal reference voltage terminal, the delta-sigma A/D converter for generating a lower conversion result at a lower conversion result terminal.

Abstract: A variable gain amplifier utilizing positive feedback and time-domain calibration includes an integration phase and a regeneration phase. A current source provides a bias current that increases linearity in the integration phase and reduces common-mode voltage dependence. The circuit includes a timing control loop, wherein a variable gain of a residue amplifier is proportional to a first time that a timing control loop signal is kept high, as determined by an on or off status of respectively paired inverter assemblies each having an input voltage determined by an amplifier output voltage during the regeneration phase. A strong-arm latch structure acts as a positive feedback latch until the first time is de-asserted.

Abstract: An SAR ADC combined with a flash ADC includes a clock generator, a DAC and a comparator. The SAR ADC combined with the flash ADC further includes an SAR logic unit using a successive approximation register control to determine, while a clock signal is a first state that is either high or low, a part of digital bits of the input signal based on a signal outputted from the comparator and control the DAC to generate a first analog signal based on the first determined digital bits and a flash ADC using a flash control to determine, during a second state switched from the first state, a remaining part of the digital bits of the input signal based on the first analog signal and control the DAC to generate a second analog signal based on the second determined digital bits in the second state.

Abstract: An example apparatus for converting a plurality of analog signals to a plurality of digital signals includes: a plurality of successive approximation (SAR) analog-to-digital converters (ADCs) each including a first input configured to receive a respective one of the plurality of analog signals, a second input configured to receive a reference signal, and an output configured to provide a respective one of the plurality of digital signals; and a shared cycle LSB generator coupled to the plurality of SAR ADCs and configured to provide the reference signal shared by the plurality of SAR ADCs.

Abstract: The disclosure includes an analog to digital converter (ADC). The ADC includes a comparator to compare sample values of an analog signal in an analog domain to reference values to determine digital values in a digital domain. The digital values correspond to the analog signal and may be determined according to successive approximation. The ADC also includes chop switches to modulate the analog signal to increase a frequency of flicker noise in the analog domain. The ADC also includes an un-chop switch to demodulate the digital values in the digital domain prior filtration of the flicker noise by a digital filter.

Abstract: An A/D converter is provided with: an integrator that includes an operational amplifier provided with a first input terminal and an output terminal, and an integration capacitor; a quantizer that outputs a quantization result obtained by quantizing an output signal from the operational amplifier; and a DAC that is connected to the first input terminal and determines DAC voltage. The integrator has a feedback switch between the integration capacitor and the output terminal of the operational amplifier. An analog signal as an input signal is inputted between the integration capacitor and the feedback switch. The integration capacitor samples the analog signal. The quantizer performs the quantization based on the output of the operational amplifier. The DAC sequentially subtracts electric charge accumulated in the integration capacitor to thereby change the analog signal to a digital value.

Abstract: A signal processing apparatus includes an input voltage selector configured to select an input voltage from a plurality of input voltages; an input element connected to the input voltage selector; and an input current controller configured to control an inflow of an input current in conjunction with an operation of the input voltage selector.

Abstract: A comparator includes a first input stage coupled to a first signal input and a first reference input, wherein the first input stage is coupled between a first node and a second node. A second input stage is coupled to a second signal input and a second reference input, wherein the second input stage is coupled between a third node and the second node. An output stage generates at least one output signal in response to the first and second input signals. First switching circuitry is coupled between the first node and the output stage. The first switching circuitry is for coupling the first node to a fourth node in response to a reset signal. Second switching circuitry is coupled between the third node and the output stage. The second switching circuitry is for coupling the third node to a fifth node in response to the reset signal.

Abstract: An analog-to-digital conversion method may include: generating an initial comparison signal by comparing a pixel signal of a comparison column to a pixel signal of an adjacent column; generating a control signal for selecting a ramp signal according to the generated initial comparison signal; and performing data conversion by comparing the ramp signal selected according to the generated control signal to a difference between adjacent first and second pixel signals.

Abstract: Certain aspects of the present disclosure are directed to a circuit for driving a signal at an output node. The circuit generally includes a voltage divider network having a first terminal coupled to the output node. The circuit also includes a first transistor having a gate coupled to a second terminal of the voltage divider network and a plurality of transistors. A gate of each of the plurality of transistors may be coupled to a respective tap node of the voltage divider network, and the plurality of transistors may include a third transistor having a source coupled to a drain of the first transistor. The circuit may also include a second transistor coupled to the first transistor and having a gate coupled to an input node of the circuit.

Abstract: Certain aspects of the present disclosure are directed to a circuit for driving a signal at an output node. The circuit generally includes a voltage divider network having a first terminal coupled to the output node. The circuit also includes a first transistor having a gate coupled to a second terminal of the voltage divider network and a plurality of transistors. A gate of each of the plurality of transistors may be coupled to a respective tap node of the voltage divider network, and the plurality of transistors may include a third transistor having a source coupled to a drain of the first transistor. The circuit may also include a second transistor coupled to the first transistor and having a gate coupled to an input node of the circuit.

Abstract: A semiconductor memory device includes a reference voltage generation block suitable for selecting and outputting one of a plurality of reference voltages in response to a voltage division enable signal, as an input reference voltage, in response to a selection enable signal; and a control signal generation block suitable for generating the voltage division enable signal and the selection enable signal in response to a reference voltage information.

Abstract: A non-linear gamma compensation current mode digital-analog converter includes: a first digital-analog converter block configured to: receive a digital signal, a first reference voltage, and a gamma adjustment voltage, and provide a reference current to a ground, wherein a first current flowing to a first current output terminal is determined according to the digital signal and the gamma adjustment voltage; and a second digital-analog converter block configured to: receive the digital signal, a second reference voltage, and a ground voltage, and provide the first current to the first digital-analog converter, wherein a second current flowing to a second current output terminal is determined according to the digital signal and the first current.

Abstract: An analog-to-digital converter includes a comparator, a capacitive digital-to-analog converter (DAC), and calibration circuitry. The capacitive DAC is coupled to the comparator, and includes a plurality of capacitors. The calibration circuitry is configured to adjust a value of each of the capacitors, and includes binary search circuitry and error correction circuitry. The binary search circuitry applies a binary search over a first number of bits of a multi-bit adjustment value used to adjust the value of one of the capacitors, and averages a first number of comparator output samples to determine each of the first number of bits. The error correction circuitry applies an error correction to the multi-bit adjustment value generated by the binary search, and averages a second number of comparator output samples for the error correction. The second number of comparator output samples is greater than the first number of comparator output samples.

Abstract: Systems, methods, and circuitries for converting an analog voltage to a digital signal are provided. In one example a method to convert an analog voltage into a binary sequence that represents the voltage includes two modes. In the first mode, in each cycle, values for a next two or more of consecutive most significant bits (MSBs) in the sequence are determined using M comparators, wherein M is equal to or greater than 3. In a second mode, in each cycle, M redundant comparison results are determined using the M comparators. A value for the LSB is determined based on the M redundant values. At an end of conversion, the sequence of N bit values is generated based on the MSBs and the LSB.

Abstract: Methods and systems for network devices are provided. One method includes receiving a serial data stream at a network interface of a network device coupled to a network link to communicate with other networked devices, the data stream including an alignment marker with a bit pattern for recovering a bit stream used by network device logic for processing the received serial data stream; using a plurality of comparators for simultaneously comparing within a single clock cycle, portions of a parallel data stream generated after converting the serial data stream by a de-serializer of the network device; detecting the bit pattern of the alignment marker in the parallel data stream by one of the plurality of comparators; storing a starting bit position of the alignment marker in the parallel data stream; and reordering the parallel data stream based on the stored starting bit position of the alignment marker.

Abstract: The present invention provides a high-precision analog-to-digital converter, includes a redundant weight capacitor array, a comparator, a code reestablishment circuit, a weight storage circuit and a control logic circuit. The redundant weight capacitor array collects input voltages and generates output voltages in a sampling stage. The comparator compares the output voltages of the redundant weight capacitor array. The code reestablishment circuit calculates an output code of the successive approximation type analog-to-digital converter according to the comparator output result and a capacitor weight in the weight storage circuit. The weight storage circuit stores the capacitor weight. The control logic circuit controls the sampling and conversion stages of the redundant weight capacitor array. The present invention also provides a DNL-based performance improvement method adapted to the analog-to-digital converter.

Abstract: There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.

Abstract: Various embodiments of the present technology may comprise a method and apparatus for an analog-to-digital converter (ADC). The ADC may convert an analog signal to a digital signal utilizing a two-phase conversion process to convert the signal into coarse bits and fine bits. The ADC may generate a time-residue signal and utilize the time-residue signal to determine the fine bits.

Abstract: An information processing apparatus includes a storage device, an arithmetic processing unit, a first converting device, and a second converting device. The storage device outputs data in accordance with a memory access request. The arithmetic processing unit performs an arithmetic operation on the data. The first converting device converts a memory access request issued by the arithmetic processing unit to a memory access signal and sends to the storage device. The second converting device converts a memory access request issued by the arithmetic processing unit to a memory access signal, acquires the memory access signal sent by the first converting device, and compares the content of a memory access performed by using the converted memory access signal with the content of a memory access performed by using the acquired memory access signal, and determines whether the first converting device has failed.