Abstract: A digital oscilloscope comprises a sampling unit configured to sample an input signal received from an oscilloscope probe to produce a first stream of digital samples, a first acquisition system configured to store and process the stream of digital samples to produce a first data set, a second acquisition system configured to store and process the first stream of digital samples independent of the first acquisition system to produce a second data set, and a display system configured to concurrently display the first data set in a first format and the second data set in a second format different from the first format.

Abstract: According to one embodiment, a temperature sensor includes: a voltage generating part generating (2N?1)-midpoint voltages (N is a natural number equal to or larger than 2) based on a reference voltage which does not depend on a temperature; a sense part generating a temperature sensing voltage which depends on the temperature; and an arithmetic part is configured to generate N-bit temperature data by executing first to N-th operations each comparing the temperature sensing voltage with one of the (2N?1)-midpoint voltages.

Abstract: Electronic apparatus and methods of operating the electronic apparatus include less than a frequency associated with a generated waveform. In various embodiments, an apparatus using a differential analog-to-digital converter can perform low frequency noise rejection that can be implemented in a variety of applications. Additional apparatus, systems, and methods are disclosed.

Abstract: An analog-digital converting device includes a successive approximation register (SAR) analog-digital converting circuit suitable for resolving upper N-bits for an input signal, a single-slope (SS) analog-digital converting circuit suitable for resolving lower M-bits for the input signal after the SAR analog-digital converting circuit resolves the upper N-bits, and a combining circuit suitable for combining the upper N-bits and the lower M-bits.

Abstract: The present invention provides a small-sized inexpensive solid-state imaging apparatus. A D/A converter included in a successive comparison type A/D converter of the solid-state imaging apparatus includes a multiplexer which selects any of reference voltages VR0 to VR16 and sets it as an analog reference signal when coarse A/D conversion is performed, and which selects reference voltages VR (n?1) to VR (n+2) of the reference voltages VR0 to VR16 when fine A/D conversion is performed, and a capacitor array which generates an analog reference signal, based on the reference voltages VR (n?1) to VR (n+2) when the fine A/D conversion is performed. It is thus possible to reduce settling errors in reference voltage without using redundant capacitors.

Abstract: A processing speed can be improved while the accuracy of AD conversion is enhanced. An AD converter includes: a higher-order DAC that samples an analog input signal and performs DA conversion corresponding to higher-order bits of a digital output signal; an extension DAC that performs DA conversion to positive and negative polarities on an extension bit for expanding bits of the higher-order DAC; a lower-order DAC that performs DA conversion corresponding to lower-order bits of the digital output signal; a comparator that compares a comparison reference voltage with output voltages of the higher-order DAC, the extension DAC, and the lower-order DAC; and a successive approximation logic that controls successive approximation performed by the higher-order DAC, the extension DAC, and the lower-order DAC based on a comparison result of the comparator and generates the digital output signal.

Abstract: The present invention relates to a successive approximation register analog-to-digital converter (SAR ADC) for providing a digital approximation of a sampled differential input signal as a result of a successive approximation operation. The SAR ADC comprises a first comparison stage configured to perform a first set of decision steps of the successive approximation operation and a second comparison stage configured to perform a second set of decision steps of the successive approximation operation. Furthermore, the SAR ADC comprises a regulation circuit configured to adjust the common mode of the input signal towards a target common mode before the second comparison stage performs the second set of decision steps. The present invention further relates to a corresponding method and a corresponding design structure.

Abstract: An organic light-emitting display apparatus including a display including pixels arranged in an array, a sensor for detecting respective current characteristics of the pixels, a current sensor for receiving a first current from a first pixel of the pixels, for outputting a first voltage corresponding to the first current, for receiving a second current from a second pixel of the pixels, and for outputting a second voltage corresponding to the second current, a level shifter for receiving the first and second voltages and for generating first and second shift voltages respectively corresponding to the first and second voltages, an intermediate voltage of the first and second voltages being equal to a conversion reference voltage, and an analog-to-digital converter for receiving the first and second shift voltages and for outputting a digital value corresponding to a difference between the first and second shift voltages based on the conversion reference voltage.

Abstract: A switched current pipeline analog-to-digital converter (ADC) integrated circuit. The integrated circuit comprises a track and hold circuit (T/H) and a residue amplifier. The T/H is configured to generate a differential output of the T/H based on an analog input. The residue amplifier is coupled to the T/H, configured to capture a sample of a common mode signal of the differential output of the T/H during a periodic pulse interval, wherein the pulse interval is less than half of the time duration of the period of the pulse, configured to generate a corrected input common mode feedback signal based in part on the sample of the common mode signal of the differential output of the T/H, and configured to generate a differential output of the residue amplifier based on the differential output of the T/H and based on the corrected input common mode feedback signal.

Abstract: An analog input voltage is converted to a digital code by, generating a first set of confirmed bits based on a first series of comparisons of an output of a digital-to-analog converter with the analog input voltage and generating a second set of confirmed bits based on a second series of comparisons of the output of the digital-to-analog converter with the analog input voltage. The first set of confirmed bits is independent of the second series of comparisons. The bits of the digital output code corresponding to the analog input voltage are generated based on the first set of confirmed bits, the second set of confirmed bits and a constant value representative of a voltage shift introduced in the digital-to-analog converter between the first series of comparisons and the second series of comparisons.

Abstract: An electronic apparatus includes: a reference-signal output section that outputs a reference signal; a comparator that compares an electrical signal output from a pixel with the reference signal; a counter that obtains a count value as an AD conversion result of the electrical signal, the count value being obtained by counting time taken for the reference signal to change until the electrical signal and the reference signal match each other; and an auto-zero control section that performs control so that auto zero processing for setting the comparator is completed in a reset period, in which the pixel is reset, so that a comparison result indicating that two input signals supplied to the comparator match each other.

Abstract: In a conventional calibration method of an analog to digital converter, it has been difficult to easily derive a plurality of correction coefficients. A semiconductor apparatus according to an embodiment includes a plurality of unit elements that are provided to correspond to the total number of weights for each bit of the digital intermediate value b[1:0] output from a sub ADC, and the same capacitance, the same resistance value, or the same current value being set to the plurality of unit elements. Further included is a corresponding bit switching unit configured to switches the bits of the digital intermediate value based on which the plurality of unit elements generate analog values. At the time of calibration, combinations of the plurality of unit elements and the bits are rotated, and correction coefficients are derived by digital intermediate values obtained according to each combination.

Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.

Abstract: A solid-state imaging device having an analog-digital converter, and an analog-digital conversion method are described herein. An example of a solid-state imaging device comprises a bit inconsistency prevention section configured to prevent bit inconsistency between output of a low-level bit latch section and a high-level bit counting section.

Abstract: An efficient analog to digital converter is disclosed. The efficient analog to digital converter includes a coarse analog to digital converter coupled to an input analog signal. The coarse analog to digital converter is configured to provide an approximate digital representation of the input analog signal. The efficient analog to digital converter also includes a fine analog to digital converter coupled to the input analog signal. The output of the coarse analog to digital converter is coupled to the fine analog to digital converter. The fine analog to digital converter is configured to set input range of the fine analog to digital converter as a function of the output of the coarse analog to digital converter.

Abstract: An analog-to-digital converter circuit for a radar apparatus, the analog-to-digital converter circuit including analog-to-digital converters that are electronically reconfigurable to operate in a multi-channel mode with a first bandwidth by clocking the ADCs in phase with one another, or a single-channel mode with a second bandwidth higher than the first bandwidth by clocking the ADCs out of phase with one another and optimizing the intermediate frequency for the respective mode.

Abstract: A charge transfer circuit has a charge transfer unit including an input charge holding element holding an input charge, an output charge holding element holding an output charge, and a charge transfer element, provided between a first node of the input charge holding element and a second, node of the output charge holding element, to transfer the charge held by the input charge holding element to the output charge holding element, an error sensing circuit detecting a third voltage corresponding to a first voltage of the first node when the charge transfer element finished transferring the charge from the input charge holding element to the output charge holding element, and an error correction unit correcting a second voltage of the second node when the charge transfer finished based on the third voltage and eliminate an error included in the second voltage of the second node.

Abstract: An analog-to-digital converter circuit includes a digital-to-analog converter circuit, a voltage stabilization circuit, and a comparator circuit. The digital-to-analog converter circuit generates an analog signal based on digital signals and a reference voltage. The voltage stabilization circuit reduces variations in the reference voltage in response to at least one of the digital signals. The comparator circuit generates a comparison output based on the analog signal. The digital signals are generated based on the comparison output.

Abstract: A successive approximation register analog to digital converter (SAR ADC) receives an input voltage and a plurality of reference voltages. The SAR ADC includes a charge sharing DAC. The charge sharing DAC includes an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit) capacitors. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A coarse ADC (analog to digital converter) receives the input voltage and generates a coarse output. A predefined offset is added to a residue of the coarse ADC. A successive approximation register (SAR) state machine is coupled to the coarse ADC and the zero crossing detector and, generates a plurality of control signals. The plurality of control signals operates the charge sharing DAC in a sampling mode, an error-correction mode and a conversion mode.

Abstract: Multi-stage parallel super-high-speed ADC and DAC of a logarithmic companding law has a voltage follower switch having zero voltage drop, and also has a lossless threshold switch group, wherein a quantization voltage of A/D conversion or D/A conversion is directly obtained through voltage-dividing resistance thereof. The ADC and DAC simplify a conversion process and reduce a conversion error. The ADC and DAC provide multi-stage multi-bit parallel super-high-speed A/D conversion and D/A conversion with logarithmic companding law of a high conversion rate and the low conversion error.

Abstract: A parallel-type AD converter includes: a plurality of comparators that receive comparison reference potentials different from one another and compare the comparison reference potentials and received analog input signals; an encoder that encodes outputs of the plurality of comparators to output digital signals; and a resistor ladder circuit that resistance-divides a reference voltage to generate the comparison reference potentials and supplies the comparison reference potentials to the comparators through output nodes each positioned between resistors, and is designed to supply a correction current corresponding to noise currents that the comparators generate to the output nodes of the comparison reference potentials in the resistor ladder circuit, and thereby the noise currents that the comparators generate are offset by the correction current, a bias current in the resistor ladder circuit can be decreased, and accuracy deterioration in AD conversion can be suppressed.

Abstract: Method and device for converting analog signals, of a plurality of pathways, into digital signals. A common circuit (2, 3) generates first analog signals corresponding to high-order bits of digital signals. For each pathway, a first means compares the first analog signals with the signal to be converted. A first means (18) stores high-order bits corresponding to the value of a first analog signal close to the signal to be converted. A means (9) stores the deviation between the analog signal to be converted and said first detected value. A generator means (11, 12) generates a predetermined number of second analog signals. A second means compares by successive approximations said second analog signals with said deviation. A means (20) stores said low-order bits corresponding to the results arising from said second means of comparison. A means (22) assembles said high-order bits and said low-order bits.

Abstract: A circuit including first and second reference ladders, a selection circuit, first and second analog to digital converters (ADCs), and a summer. The first reference ladder is configured to provide first reference voltages via first taps. The selection circuit is configured to select one of the first reference voltages. The second reference ladder is configured to, based on the selected one of the first reference voltages, provide second reference voltages via second taps. The first ADC is configured to convert the first version of the analog input signal to a first digital signal. The second ADC is configured to, based on the second reference voltages, convert the second version of the analog input signal to a second digital signal. The summer is configured to generate a digital output signal based on the first and second digital signals.

Abstract: Various embodiments of the invention provide for cancellation of a residue amplifier output charging current at the reference voltage source of the reference buffer thereby preventing the charging current from altering the effective reference voltage of a reference buffer. In certain embodiments, current cancellation is accomplished by subtracting a current of the same magnitude.

Abstract: Embodiments of the present invention may provide accuracy enhancement techniques to improve ADC SNRs. For example, regular bit trials from a most significant bit (MSB) to predetermined less significant bit of a digital word and extra bit trials may be performed. The results of the regular and extra bit trials may be combined to generate a digital output signal. A residue error may be measured, and the digital output signal may be adjusted based on the measured residue error.

Abstract: A multistage analog-to-digital data conversion, including: a first stage unit configured to process an analog input signal into a first number of most significant bits using a first reference signal, and to output a first stage residue signal; a second stage unit configured to receive and process the first stage residue signal into a second number of remaining least significant bits using a second reference signal; a sampling unit configured to sample the first stage residue signal received from the first stage unit onto the second stage unit with a passive element; and an output unit configured to output a digital value that is a combination of the first number of most significant bits and the second number of remaining least significant bits.

Abstract: An SAR analog-to-digital conversion circuit includes: first and second CDACs; first to third comparators respectively comparing outputs of the first and second CDACs, output levels of the first and third CDACs with a reference level; an arithmetic operation circuit; and an SAR control circuit, wherein the SAR control circuit: at each step, determines in which of four ranges output levels of the sampled and held signals of the first and second CDACs are included, the four ranges corresponding to the conversion range being quartered, determines two bits of the digital data and adjusts the output levels of the first and second CDACs so that a level at ¼ or ¾ of the voltage range agrees with the intermediate level, and controls first and second switches so that the voltage range is set to be a conversion range at a next step.

Abstract: Imagers may include analog-to-digital converter circuitry that produces a digital output code from an analog input voltage. The analog-to-digital converter circuitry may include a series of capacitors including a first set of binary-mapped capacitors. The analog-to-digital converter circuitry may include a second set of one or more capacitors that have capacitances that are less than binary-mapped capacitance values. The digital output code may include bits having respective bit positions within the digital output code. During successive-approximation operations performed by the analog-to-digital converter circuitry, each bit of the digital output code may be produced using a corresponding capacitor. Digital processing circuitry such as an image processor may produce a digital value from the digital output code by multiplying the bits of the digital output code with respective weights determined based on the capacitance of the corresponding capacitors.

Abstract: A method utilized in an analog-to-digital conversion apparatus, for converting an analog input signal into a digital output signal including a first portion and a second portion, includes: using a comparator circuit to compare the analog input signal with at least one first reference level to generate a preliminary comparison result, the at least one first reference level being used for determining the first portion; estimating the first portion according to the preliminary comparison result; based on the preliminary comparison result, performing the successive approximation procedure to obtain a posterior comparison result according to a plurality of second reference levels, the second reference levels being used for determining the second portion; and, estimating the second portion according to the posterior comparison result. The preliminary and posterior comparison results are generated by the comparator circuit.

Abstract: The present invention provides a small-sized inexpensive solid-state imaging apparatus. A D/A converter included in a successive comparison type A/D converter of the solid-state imaging apparatus includes a multiplexer which selects any of reference voltages VR0 to VR16 and sets it as an analog reference signal when coarse A/D conversion is performed, and which selects reference voltages VR (n?1) to VR (n+2) of the reference voltages VR0 to VR16 when fine A/C conversion is performed, and a capacitor array which generates an analog reference signal, based on the reference voltages VR (n?1) to VR (n+2) when the fine A/D conversion is performed. It is thus possible to reduce settling errors in reference voltage without using redundant capacitors.

Abstract: According to an embodiment, an analog-to-digital (AD) converter includes a first AD conversion unit, a selector and a second AD conversion unit. The first AD conversion unit performs AD conversion of an analog signal in a first period to generate an upper-bit digital signal. The selector selects not less than one reference voltage based on the upper-bit digital signal to obtain a selected reference voltage group in a voltage range narrower than a full scale. The second AD conversion unit performs AD conversion of the analog signal by using the selected reference voltage group. The first period starts before settling of the analog signal up to an accuracy corresponding to a total resolution of the first AD conversion unit and the second AD conversion unit.

Abstract: According to an embodiment, an analog-to-digital converter includes a first AD (analog-to-digital) conversion circuit and a second AD conversion circuit. The first AD conversion circuit performs AD conversion of a first input signal to generate an upper-bit digital signal. The second AD conversion circuit performs AD conversion of a sampled signal to generate a lower-bit digital signal. The sampled signal is obtained by sampling a residual signal corresponding to a residue of the AD conversion in the first AD conversion circuit. A period during which the second AD conversion circuit performs AD conversion of the sampled signal overlaps a period during which a second input signal subsequent to the first input signal is settled.

Abstract: A method for converting a capacitance of a sensing capacitor (10) to be measured into a digital signal is described, wherein according to a clocking in charging processes an integrating capacitor (5), discharged before a start of conversion, of an integrator circuit is charged by an electric current which is obtained from a charging of the sensing capacitor (10) and in discharge processes by brief current surges in the opposite direction which are obtained from a charging of a reference capacitor (6), with the result that on average no charge builds up, and the number of discharge processes occurring during a particular number of clock pulses is counted, wherein the clocking is paused after a predetermined number of cycles, a residual voltage (VA1), which the integrator circuit emits due to a residual charge of the integrating capacitor (5), is converted by means of analogue-to-digital voltage conversion (25) into a digital value and the counted number of discharge processes and the particular number of clock

Abstract: A system includes a pipeline analog-to-digital converter as a first stage to process an input signal, and a successive approximation register (SAR) analog-to-digital converter as a second stage to process the input signal. The SAR analog-to-digital converter includes a power adjustment element to adjust a reference voltage of the SAR analog-to-digital converter to match a full scale voltage of the pipeline-analog-to-digital converter.

Abstract: An A/D converter system that has a ranging detector that receives and characterizes an input signal. The characterizing sets a coarse range selection based on a level of the input signal. A higher level input signal has a higher level ranging. An A/D converter includes a compression system that compresses based on the ranging output signal by converting different numbers of bits for different level ranging output signal. A higher level input signal is more higher compressed and produces a digital output indicative of the input signal, which is compressed by different amounts based on the ranging output signal. By scaling in this way, the resolution of the A/D converter is scaled on the basis of shot noise level of the image sensor.

Abstract: A solid-state imaging device having an analog-digital converter, and an analog-digital conversion method are described herein. An example of a solid-state imaging device includes a column processing section that includes a low-level bit latching section. The low-level bit latching section receives a comparator output from a comparator and a count output from a counter, and the low-level bit latching section latches a count value.

Abstract: An analog to digital conversion method includes charging a capacitor through an analog signal to sample a voltage of the analog signal; coupling the capacitor and a plurality of reference voltages to a comparator when a voltage of the capacitor is equal to the voltage of the analog signal, to compare the voltage of the capacitor with the reference voltages and generate a first comparison result; coupling the capacitor to a ramp generator when a status of the first comparison result changes, to compare a ramp signal of the ramp generator with a voltage difference of a first reference voltage and the voltage of the capacitor and generate a second comparison result; obtaining a voltage of the ramp signal when a status of the second comparison result changes; and obtaining a digital code of the analog signal according to the first reference voltage and the voltage of the ramp signal.

Abstract: An analog to digital conversion method includes charging a capacitor through an analog signal to sample a voltage of the analog signal; coupling the capacitor and a plurality of reference voltages to a comparator when a voltage of the capacitor is equal to the voltage of the analog signal, to compare the voltage of the capacitor with the reference voltages and generate a first comparison result; coupling the capacitor to a ramp generator when a status of the first comparison result changes, to compare a ramp signal of the ramp generator with a voltage difference of a first reference voltage and the voltage of the capacitor and generate a second comparison result; obtaining a voltage of the ramp signal when a status of the second comparison result changes; and obtaining a digital code of the analog signal according to the first reference voltage and the voltage of the ramp signal.

Abstract: A received plurality of signals may be filtered to select an in-band signal and/or an out-of-band. A signal strength of the selected signal(s) may be measured. A resolution of an analog-to-digital converter may be controlled based on the measured signal strength(s). The selected in-band signal may be converted to a digital representation via the analog-to-digital converter. The resolution may be decreased when the strength of the in-band signal is higher, and increased when the strength of the in-band signal is lower. The resolution may be increased when the strength of the out-of-band signal is higher, and decreased when the strength of the out-of-band signal is lower. A signal-to-noise ratio and/or dynamic range of the selected signal(s) may be determined based on the measured signal strength(s), and may be utilized to adjust the resolution of the analog-to-digital converter.

Abstract: An analog-to-digital converter (ADC) and a receiver that includes the ADC is disclosed. The ADC includes a first filter configured to receive a signal in an I-signal path of the receiver and a second filter configured to receive a signal in a Q-signal path of the receiver. The ADC further includes a quantizer alternatingly in connection with the first and second filters, and at least one DAC alternatingly in connection with the first and second filters. Switches in the ADC are configured to alternate connection between an input of the quantizer and outputs of the first and second filters, and are also configured to alternate connection between an output of the at least one DAC and inputs of the first and second filters.

Abstract: A continuous-time delta-sigma digital-to-analog converter (DAC) includes a first delta-sigma modulator configured to quantize a most significant bit or bits of a digital input signal and produce a first quantization error signal, and a second multi-stage delta-sigma modulator configured to quantize less significant bits of the digital input signal. A first DAC is coupled to an output of the first delta-sigma modulator, and a second DAC is coupled to an output of the second noise-shaping filter. The second DAC has a greater resolution than the first DAC. A low pass output filter is coupled to a sum of an output of the first DAC and an output of the second DAC.

Abstract: A comparison circuit is provided and includes first and second comparators and a first time-to-digital comparator. The first comparator with a first offset voltage receives an input signal and generates a first comparison signal and a first inverse comparison signal. The second comparator receives the input signal and generates a second comparison signal and a second inverse comparison signal. The first offset voltage is larger than the second offset voltage. The first time-to-digital comparator receives the first comparison signal and the second inverse comparison signal and generates first and second determination signals according to the first comparison signal and the second inverse comparison signal. The first and second determination signals indicate whether a voltage of the input signal is larger than a first middle voltage. The first middle voltage is equal to a half of the sum of the first offset voltage and the second offset voltage.

Abstract: A multistage analog-to-digital data conversion, including: a first stage unit configured to process an analog input signal into a first number of most significant bits using a first reference signal, and to output a first stage residue signal; a second stage unit configured to receive and process the first stage residue signal into a second number of remaining least significant bits using a second reference signal; a sampling unit configured to sample the first stage residue signal received from the first stage unit onto the second stage unit with a passive element; and an output unit configured to output a digital value that is a combination of the first number of most significant bits and the second number of remaining least significant bits.

Abstract: A system and method for low-power digital signal processing, for example, comprising adjusting a digital representation of an input signal.

Abstract: Measures are provided for performing direct radio-frequency to digital conversion. A radio-frequency input signal is compared with a plurality of reference voltages to generate a plurality of comparison signals, each comparison signal corresponding to one of the plurality of reference voltages. One or more of the plurality of generated comparison signals are first filtered to generate a first filtered signal. One or more of the plurality of generated comparison signals are second filtered to generate a second filtered signal. A digital output signal is generated at least on the basis of the first filtered signal and the second filtered signal.

Abstract: An analog-to-digital converter (ADC) for a multi-channel signal acquisition system, a signal acquisition system, a method of generating a digital output code from an analog input signal, and a method of converting a plurality of analog signals to a digital signal are provided. The ADC comprises a sample-and-hold (S/H) circuit operable to receive an analog input signal for each input channel; a digital-to-analog converter (DAC) common to all input channels; a comparator for each input channel configured to receive an output signal from the S/H circuit of the respective input channel, and an output signal from the DAC, for generating a comparison result of the two signals at each conversion cycle of the comparator; and a successive approximation register (SAR) common to all input channels and configured to generate, for each input channel, a digital output code based on the comparison results received from the respective comparator.

Abstract: A method, comprising: receiving a plurality of 2-tuples of asynchronously sampled inputs at an asynchronous to synchronous reconstructor; performing a coarse asynchronous to synchronous conversion using the plurality of 2-tuples to generate a plurality of low precision synchronous outputs; generating a high precision synchronous output, z0, using a plurality of asynchronous 2-tuples, low precision synchronous outputs after it, and its own high precision outputs from previous steps; calculating c0 and c?1 by summing future low precision outputs and the past high precision outputs after they are weighted with the appropriate windowed sinc. values and then subtracted from appropriate asynchronous samples; calculating, the four quantities “s?11”, “s01”, “s00” and “s?10” based on particular values of the windowed sinc. function; and using c0, c?1, s?11, s01, s00 and s?10, the high precision synchronous output of interest, z0 is generated.

Abstract: An A/D conversion circuit in which a counter is made to be capable of performing counting at both edges of a clock, up/down count values can be switched while the up/down count values are held, and the duty of the counting operation is difficult to be distorted even with the both-edge counting, a solid-state image sensor, and a camera system.

Abstract: Aspects of the present disclosure relate to floating point timers and counters that are used in a variety of contexts. In some implementations, a floating point counter can be used to generate a wave form made up of a series of pulses with different pulse lengths. An array of these floating point counters can be used to implement a pool of delays. In other implementations, an array of floating point counters can be used to analyze waveforms on a number of different communication channels. Analysis of such waveforms may be useful in automotive applications, such as in wheel speed measurement for example, as well as other applications.

Abstract: Some embodiments of the present invention provide a method and apparatus for a Vernier ring time to digital converter having a single clock input and an all digital circuit that calculates a fixed delay relationship between a set of slow buffers and fast buffers. A method for calibrating a Vernier Delay Line of a TDC, comprising the steps of inputting a reference clock to a slow buffer and to a fast buffer, determining a delay ratio of the slow buffer and fast buffer; and adjusting the delay ratio of the slow buffer and fast buffer to a fixed delay ratio value wherein an up-down accumulator generates control signals to adjust the slow buffer.