Abstract: An analog-to-digital converting method for converting an analog signal to a digital signal is disclosed. The analog-to-digital converting method includes decomposing the analog signal into a major analog signal and a minor analog signal, converting the major analog signal to a major digital signal, determining to which of a plurality of default sections the minor analog signal belongs to generate a minor digital signal correspondingly, and combining the major digital signal and the minor digital signal to form the digital signal.

Abstract: An ADC is disclosed which has, as a first stage, a successive approximation converter, or other compensated, direct comparison converter, followed by a sigma delta modulation converter as a second stage. The sigma delta converter may beneficially be a first order modulator. The resulting ADC combines accuracy with low power consumption per conversion, and thus is particularly suited for use in temperature sensors for applications such as RFID transponders. Such a temperature sensor and an RFID transponder are also disclosed. There is also disclosed a method of analog-to-digital conversion, comprising a first successive approximation register or other compensated, direct comparison conversion stage followed by a sigma delta modulation stage, which, further, may be combined with providing a proportional-to-absolute-temperature (PTAT) signal, for low-power, accurate temperature sensing.

Abstract: The present invention provides a pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) circuit with decoupled flip-around MDAC, capacitive attenuation solution and self-embedded offset cancellation. The flip-around MDAC architecture is built for low inter-stage gain implementation. A capacitive attenuation solution is provided for minimizing the power dissipation and optimizing conversion speed. The design reuses SAR ADC to perform offset cancellation, which significantly saves calibration area, power and time.

Abstract: Correcting phase error in a two-channel TIADC system in a manner that is independent of the Nyquist zone(s) occupied by the input signal. In the preferred approach this is done using the gradient of a phase error estimate. The gradient may be determined from a simplified expression of linear regression; the direction of the adaptation is then controlled by the sign of the gradient. The adaptive algorithm converges to the optimal value regardless of the Nyquist zone occupied by the input signal.

Abstract: A data acquisition system for converting an analog input signal to a digital output signal includes a programmable gain amplifier (PGA), an analog to digital converter (ADC), and an averaging module. The PGA generates first and second amplified signals during respective first and second conversion cycles. The first and second amplified signals include respective first and second amplified input signals and first and second sets of offset and noise signals. The first and second amplified input signals have the same polarities, and the first and second sets of offset and noise signals have opposite polarities. The ADC generates first and second digital samples corresponding to the first and second amplified signals respectively and the averaging module averages the first and second digital samples to eliminate the first and second sets of offset and noise signals from the digital output signal.

Abstract: An analog-to-digital converter comprises a first set of comparators configured for generating a coarse digital measurement of an analog input signal, and a second set of comparators for performing a fine digital measurement of the analog input signal. The second set comprises a plurality of dynamic comparators, wherein each dynamic comparator is configurable for being activated by a clock signal. An activation circuit processes the coarse measurement and an input clock signal for generating a set of activation signals, which activate a subset of the dynamic comparators to generate the fine digital measurement.

Abstract: An apparatus implements analog-to-digital conversion with released requirement on the reference settling errors and improved immunity to the noise originated from the power supply, ground and the positive and negative references. It includes a comparator comparing the specified reference levels with the analog input, multi DAC sub-circuits with separate non-binary search schemes applied to and a digital control logic controlling the reference search process. No cross-talk occurs among the different non-binary search algorithms. Each redundancy scheme is localized in a respective DAC sub-circuit and covers the reference levels only in the current DAC. The non-binary search algorithms are fulfilled in the digital domain and trade the non-binary search step sizes with the number of the search steps to introduce redundancy to the reference levels.

Abstract: Providing for a two-stage single-slope analog to digital converter (ADC) exhibiting high resolution in conjunction with reduced power consumption is described herein. The ADC can achieve a digital resolution of at least 13 bits according to one or more disclosed embodiments, with significantly lower power consumption than conventional high resolution analog to digital converters. In operation, bias current supplied to one or more components of the ADC can be ramped up to a high magnitude during high accuracy or high speed processes of the ADC. Upon completion of these processes, the bias current can be sharply reduced for at least a portion of a clock cycle. During a residue amplification process associated with a second stage of the ADC, bias current can be increased to a moderate level. Average power consumption can be reduced significantly, while maintaining peak power requirements.

Abstract: A continuous-time delta-sigma Analog to Digital Converter (ADC) includes: a loop filter, for receiving and noise-shaping an analog input signal, and outputting a first loop voltage; a first summing resistor, for transforming a first feedback current to be a first feedback voltage, and summing the first loop voltage and the first feedback voltage so as to generate a first summing voltage, wherein the first summing voltage is equal to a sum of the first loop voltage and the first feedback voltage; a quantizer, for outputting a digital output signal according to the first summing voltage; and a current Digital to Analog Converter (DAC), for generating the first feedback current according to the digital output signal.

Abstract: A hybrid ADC having a successive approximation register (SAR) ADC mode for generating a bit of a digital signal and a ramp ADC mode for generating an additional bit of the digital signal is disclosed. When in the SAR ADC mode, a control circuit is configured to disable a ramp signal generator; disable a counter; and enable a register to control an offset stage to set the magnitude of an offset voltage that is provided to an input of a comparator of the ADC. When in the ramp ADC mode, the control circuit is configured to enable the ramp signal generator to provide a ramp signal to the input of the comparator; enable the counter to begin providing the digital count in response to the output of the comparator; and disable the register so that the offset stage is not providing the offset voltage.

Abstract: The present invention is related to a pipelined analog-to-digital converter, ADC, for converting an analog input signal into a digital signal comprising—a plurality of comparing means having tuneable thresholds for comparing an input signal with; at least two of said given thresholds being different and—a plurality of amplifying circuits,—wherein said plurality of comparing means is configured to form a hierarchical tree structure, said hierarchical tree structure having a plurality of hierarchical levels, wherein at least one of said hierarchical levels is associated with at least one amplifying circuit of said plurality of amplifying circuits, said at least one amplifying circuit generating the input of at least one comparing means at the next hierarchical level and—wherein said plurality of hierarchical levels comprises means for setting said tuneable thresholds in accordance to the output of previous hierarchical level so that non-linear distortion of the preceding hierarchical level is removed.

Abstract: A current sensing circuit includes a current sensing unit, a feedback control unit and a digital output unit. The current sensing unit senses a current and produces a pulse signal according to at least one reference signal and at least one feedback signal. The current sensing unit includes a first capacitor set and a second capacitor set. The current sensing unit selects at least one capacitor in the first capacitor set and at least one capacitor in the second capacitor set according to the current value so as to adjust the precision of the current sensing circuit. The feedback control unit is coupled to the current sensing unit and produces the feedback signals according to a clock signal and the pulse signal. The digital output unit is coupled to the current sensing unit and outputs a digital signal according to the pulse signal.

Abstract: A low-power and high-speed ADC includes: a successive approximation converter circuit configured to sequentially compare and coarsely convert the analog input signal voltage into a digital signal with a number of higher-order bits, and also to output a residual voltage; a fixed-quantity change time measurement converter circuit configured to finely convert the residual voltage into a digital signal with a number n of lower-order bits by changing the residual voltage at a fixed rate of change and by measuring the time until a predetermined value is reached; and an encoder circuit configured to generate a digital signal with the predetermined number of bits by combining the digital signal with the number of higher-order bits output from the successive approximation converter circuit and the digital signal with the number of lower-order bits output from the fixed-quantity change time measurement converter circuit.

Abstract: A controlling console for moving elements such as trusses and winches. A console body has a display screen, and a processor which is programmed to produce an output screen on the display screen which accepts controls for controlling at least one movable device. The output screen includes a plurality of different logical blocks which are connected together. Values and conditions such as true, false, rising edge or error can be entered. The console arranges this into a flow arrangement.

Abstract: In plural analog circuits that can operate in parallel and are coupled to a common analog power supply terminal, one analog circuit is controlled in the analog operation start according to timing control data that specifies an interval for suppressing the analog operation start of the one analog circuit in the analog operation cycle of the other analog circuit that has already started the analog operation. The control is conducted so that when the operation of one analog circuit starts, timing when the operation of the one analog circuit is influenced by the analog operation start of the other analog circuits in the operation cycle of the one analog circuit is retained as timing control data in advance, and the analog operation start of the other analog circuits is delayed or temporarily suppressed in synchronization with the operation start of the one analog circuit according to the timing control data.

Abstract: A multiplying digital-to-analog converter suited to maintain impedance balancing during phases. In an embodiment, an input signal may be sampled onto nodes of impedance elements during an initial phase. In a second phase the impedance elements are directly coupled either to a non-inverting reference input or the inverting reference input of an amplifier depending on an output of a related flash ADC output. The determination as to which capacitor is to be coupled to inverting or non-inverting input nodes may be directly programmed into the MDAC using switches, such that a thermometric to binary converter is not required in an example embodiment. Thus, the number of impedance elements coupled to the non-inverting reference input or inverting reference input REFM remains constant in each cycle such that there is no need to settle the non-inverting reference input or inverting reference input to full accuracy.

Abstract: A folded reference voltage flash analog-to-digital (ADC) converter and a method thereof are provided. The flash ADC of the present invention determines the most significant bit (MSB) of an analog input signal, varies a reference voltage input to a plurality of comparators in accordance with the MSB determination result, and determines the remaining bits. Accordingly, input capacitance can be reduced while maintaining the size and power consumption of the ADC.

Abstract: An apparatus comprises: a coarse voltage level comparator that generates a coarse voltage level comparison; a folder, a fine analog to digital (ADC) comparator coupled to an output of the folder, wherein an output of the fine ADC is cyclical; an up encoder coupled to an output of the fine ADC encoder, the up encoder configured to output a first value if the cyclical output of the fine ADC is in a defined downward transition; and a fold information generator coupled to an output of the up encoder, wherein the fold information generator is configured to generate a determination as to in which fold an analog voltage occurs.

Abstract: A pipelined Analog-to-Digital Converter (ADC) stage includes a main sampling path having a first filter in series with a first sample and hold circuit and a sub-ADC sampling path having a second filter in series with a second sample and hold circuit driving a sub-ADC connected to a sub-Digital-to-Analog Converter (DAC). The frequency response of the main sampling path is matched to a frequency response of the sub-ADC sampling path such that a residue signal of the pipelined ADC stage stays within range.

Abstract: An analog-to-digital conversion device which converts an analog input signal into a digital signal and output it includes a signal characteristic detection unit for detecting a predetermined characteristic of the input signal; a control signal generation unit for setting a resolution based on the signal characteristic detected by the signal characteristic detection unit, generating a control signal that indicates only an operation required for performing the analog-to-digital conversion at the resolution, and outputting it; and an analog-to-digital conversion unit for restricting the operation based on the control signal and converting the input signal into the digital signal at the set resolution.

Abstract: A digital equalizer with a reduced number of multipliers for correction of the frequency responses of an interleaved ADC is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes a composite ADC including M time interleaved sub-ADC, a demultiplexer, samples repositioning unit, a first PreFIRs transformer, a second PreFIRs transformer, K double buffer FIR filters, a PostFIRs transformer, a samples sequence restoration unit, and a multiplexer, coupled in series and providing an equalized, frequency response-corrected output.

Abstract: An analog to digital converter by using an exponential-logarithmic model includes an exponential circuit which acquires an analog input voltage and generates an analog output voltage that is an exponential function of the input voltage. A positive feedback circuit that succeeds the exponential circuit exhibits a natural logarithmic characteristic. A comparator is connected to the positive feedback circuit to compare an output voltage of the positive feedback circuit with a reference voltage. Via the exponential-logarithmic conversion technique, the time interval or pulse produced by the positive feedback circuit is a linear function of the magnitude of the input voltage. Based on the comparator output, a counter is employed to translate the analog input signal to its digital representation.

Abstract: Provided is an analog digital converter (ADC). The ADC includes: a capacitor array generating a level voltage; a comparator outputting a compare signal by comparing the level voltage; and a logic circuit determining digital bits of an analog signal based on the compare signal, wherein the logic circuit determines at least one digital bit among digital bits of the analog signal while a sampling operation of the analog signal is performed in the capacitor array.

Abstract: An AD converting device includes a resistance-voltage conversion circuit which changes a first integrated voltage in proportion to a product of a varied resistance of a variable resistance and an electrical current applied to the variable resistance and changes a second integrated voltage and a reference voltage in proportion to a product of a total resistance of the variable resistance and the electrical current.

Abstract: Disclosed herein is a differential amplifier including: an input terminal configured to receive an input signal; an output terminal configured to output an output signal obtained as a result of amplifying the input signal; an amplification part configured to amplify the input signal to generate the output signal; a load circuit which is connected between the amplification part and a power-supply terminal, and is provided with a first-conduction transistor, and a changeover switch configured to switch a connection between a gate electrode of the first-conduction transistor and a drain electrode of the first-conduction transistor to a connection between the gate electrode and the output terminal or vice versa; and a leak cancel switch configured to generate a leak cancel current for reducing an off leak current flowing through the changeover switch.

Abstract: There is provided a solid-state image sensing device including a pixel section in which cells are arrayed, each cell including a photoelectric conversion unit, a reading circuit reading out, to a detection unit, signal charges obtained by the photoelectric conversion unit, an amplifying circuit amplifying and outputting a voltage corresponding to the signal charges, and a reset circuit resetting the signal charges, an exposure time control circuit controlling an exposure time and controlling the exposure time to be equal for all cells, an A/D conversion circuit A/D-converting a signal output from the pixel section by changing a resolution of a signal level, line memories storing an A/D-converted signal, and a signal processing circuit processing output signals from the line memories to have a linear gradient with respect to an optical input signal amount by controlling an amplification factor in accordance with a resolution of a pixel output signal after A/D-conversion.

Abstract: A comparison circuit is provided and includes first and second comparators and a first time-to-digital comparator. The first comparator with a first offset voltage receives an input signal and generates a first comparison signal and a first inverse comparison signal. The second comparator receives the input signal and generates a second comparison signal and a second inverse comparison signal. The first offset voltage is larger than the second offset voltage. The first time-to-digital comparator receives the first comparison signal and the second inverse comparison signal and generates first and second determination signals according to the first comparison signal and the second inverse comparison signal. The first and second determination signals indicate whether a voltage of the input signal is larger than a first middle voltage. The first middle voltage is equal to a half of the sum of the first offset voltage and the second offset voltage.

Abstract: A solid-state image sensing device comprises a pixel which outputs a pixel signal, a first conversion unit which converts the pixel signal into a digital signal with a first bit length, and a second conversion unit which converts, into a digital signal with a second bit length, an analog signal obtained by subtracting, from the pixel signal, an analog signal corresponding to the digital signal with the first bit length. The second conversion unit comprises a current source, a first capacitance, and a switching unit for switching a supply destination of a current supplied from the current source to one of the first capacitance and a reference potential. The second conversion unit performs the conversion based on comparison between a reference voltage and the analog signal which is charged in the first capacitance and is obtained as a subtraction result.

Abstract: There is provided a solid-state image sensing device including a pixel section in which cells are arrayed, each cell including a photoelectric conversion unit, a reading circuit reading out, to a detection unit, signal charges obtained by the photoelectric conversion unit, an amplifying circuit amplifying and outputting a voltage corresponding to the signal charges, and a reset circuit resetting the signal charges, an exposure time control circuit controlling an exposure time and controlling the exposure time to be equal for all cells, an A/D conversion circuit A/D-converting a signal output from the pixel section by changing a resolution of a signal level, line memories storing an A/D-converted signal, and a signal processing circuit processing output signals from the line memories to have a linear gradient with respect to an optical input signal amount by controlling an amplification factor in accordance with a resolution of a pixel output signal after A/D-conversion.

Abstract: An analog-to-digital converting (ADC) apparatus is disclosed. The ADC apparatus includes a coarse comparing module, at least one pre-switching detection module, at least one fine comparing module, and an encoder. The coarse comparing module compares an input signal and a plurality of first reference signals to generate a previous comparing result and a coarse comparing result in sequence. The pre-switching detection module generates a plurality of previous selecting signals according to the received previous comparing result. The encoder generates a previous encoding result according to the coarse comparing result. The fine comparing module selects a selected reference signal to be compared with the input signal from a plurality of second reference signals according to the previous selecting signals and the previous encoding result, so as to generate a fine comparing result.

Abstract: An apparatus comprises: a coarse voltage level comparator that generates a coarse voltage level comparison; a folder, a fine analog to digital (ADC) comparator coupled to an output of the folder, wherein an output of the fine ADC is cyclical; an up encoder coupled to an output of the fine ADC encoder, the up encoder configured to output a first value if the cyclical output of the fine ADC is in a defined downward transition; and a fold information generator coupled to an output of the up encoder, wherein the fold information generator is configured to generate a determination as to in which fold an analog voltage occurs.

Abstract: An analog-to-digital (A/D) converter includes: a coarse A/D converter configured to convert, when converting an analog input signal into an N-bit digital signal, the analog input signal into a high-order m-bit digital signal; a fine A/D converter configured to convert the analog input signal into a low-order n-bit (where n=N?m) digital signal based on a conversion result of the coarse A/D converter; and a track-and-hold (TH) circuit configured to sample the analog input signal, to supply a comparison voltage compared with a coarse reference voltage to the coarse A/D converter, and to supply a comparison voltage compared with a fine reference voltage based on a conversion result of the fine A/D converter to the fine A/D converter. The TH circuit is configured to share a sampling capacitor in a selective input path for the analog input signal, the coarse reference voltage, and the fine reference voltage.

Abstract: An analog to digital converter with increased sub-range resolution and method for using the analog to digital converter is described herein. The device includes an analog front end that produces an analog communication signal, a digital front end that receives a digital communication signal, and an Analog to Digital Converter (ADC) that samples the analog communication signal across a full-range. The ADC includes a plurality of sub-range ADCs, each sub-range ADC measuring the analog communication signal across at least one respective sub-range of the full-range, the plurality of sub-ranges extending across the full-range, a central sub-range ADC having greater quantization accuracy than at least one other sub-range ADC. The ADC also includes signal combining circuitry operable to process outputs of the plurality of sub-range ADCs to create the digital communication signal.

Abstract: An RF transceiver apparatus comprises transmitter circuitry arranged to convert signals from a baseband frequency to RF transmission frequencies and receiver circuitry arranged to convert signals from RF reception frequencies to the baseband frequency. The transmitter and receiver circuitry each comprise three mixers arranged to convert a signals between the baseband frequency, a first intermediate frequency; a second intermediate frequency that is higher than the transmission frequencies; and a second intermediate frequency to the transmission frequency.

Abstract: An analog-to-digital converting (ADC) apparatus is disclosed. The ADC apparatus includes a coarse comparing module, at least one pre-switching detection module, at least one fine comparing module, and an encoder. The coarse comparing module compares an input signal and a plurality of first reference signals to generate a previous comparing result and a coarse comparing result in sequence. The pre-switching detection module generates a plurality of previous selecting signals according to the received previous comparing result. The encoder generates a previous encoding result according to the coarse comparing result. The fine comparing module selects a selected reference signal to be compared with the input signal from a plurality of second reference signals according to the previous selecting signals and the previous encoding result, so as to generate a fine comparing result.

Abstract: An analog-to-digital converter with a resolution booster is provided. The analog-to-digital converter may include a successive approximation analog-to-digital converter, a resolution booster, and an output combiner. The successive approximation analog-to-digital converter may be configured to convert an analog signal into digital data. The resolution booster may be selectively activated to enhance the resolution of the successive approximation analog-to-digital converter, and the output combiner may be configured to combine the respective outputs of the successive approximation analog-to-digital converter and the resolution booster.

Abstract: Various embodiments of this disclosure may describe a two-stage ADC circuit, and a time-interleaved system based on the two-stage ADC circuit. The two-stage ADC circuit may include a SAR converter for the first stage and a charge based TDC for the second stage. The two-stage ADC circuit may be used in high performance serial I/O applications. Other embodiments may be disclosed and claimed.

Abstract: A time-interleaved Analog-to-Digital Converter (ADC) includes a set of sub-ADC circuits. Each sub-ADC circuit comprises a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a sample mode and a hold mode. Each sample and hold circuit also includes a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects an ON state intrinsic resistance of the switch by affecting the voltage level.

Abstract: An AD conversion apparatus includes: a first AD converter for converting an input analog signal into a first digital signal; a second AD converter for converting an analog signal obtained as a result of multiplying the input analog signal by a coefficient ? into a second digital signal; a first computing unit for multiplying the first digital signal output by the first AD converter by ?2 obtained as a result of squaring the coefficient ?; a second computing unit for multiplying the second digital signal output by the second AD converter by ??1 which is the reciprocal of the coefficient ?; and a third computing unit for computing a difference between a first computation result output by the first computing unit and a second computation result output by the second computing unit and outputting the difference as a result of AD conversion carried out on the input analog signal.

Abstract: A novel analog-to-digital converter (ADC) system using a two-step conversion is disclosed. The ADC system is capable of achieving high sampling rate, low power consumption and low complexity. The new proposed ADC is formed by cascading a flash ADC having high sampling rate and low resolution with a successive approximation (SA) ADC having low power consumption and low sampling rate.

Abstract: An A/D conversion circuit in which a counter is made to be capable of performing counting at both edges of a clock, up/down count values can be switched while the up/down count values are held, and the duty of the counting operation is difficult to be distorted even with the both-edge counting, a solid-state image sensor, and a camera system.

Abstract: An analog-to-digital conversion apparatus includes: a first analog-to-digital converter and a second analog-to-digital converter that are configured to convert an input analog signal into a digital signal; a difference imparting part configured to provide a difference of at least a fixed signal ? between input analog signals to the first and second analog-to-digital converters, to input the input analog signals thereto; a first non-linear compensation part and a second non-linear compensation part that are configured to compensate non-linear distortions of a first output signal and a second output signal depending on the control variable signal to be supplied; and a non-linear detection part configured to estimate how much the non-linear distortions are compensated by the first and second non-linear compensation parts depending on a first signal by the first non-linear compensation part and a second signal by the second non-linear compensation part.

Abstract: A delta sigma analogue to digital converter comprising: an integrator having first and second differential inputs for receiving an input analogue signal, the integrator having differential outputs; a quantiser having first and second differential inputs which receive signals output by the integrator, and an output which provides a digital output signal of the delta sigma analogue to digital converter, and a digital to analogue converter. The digital to analogue converter has an input which is connected to an output of the delta sigma analogue to digital converter, and first and second differential outputs. The first output of the digital to analogue converter is connected to the first input of the integrator such that if the second output of the digital to analogue converter is not connected to the second input of the integrator and the second input of the integrator is connected to a fixed reference voltage the delta sigma analogue to digital converter is able to operate in a single-ended mode.

Abstract: Method and apparatus for generating a target frequency having an over-sampled data rate using a system clock having a different frequency are disclosed. In one aspect of the present disclosure, the circuit includes, a digital phase locked loop coupled to the system clock. The digital phase locked loop including an oscillator output and an oscillator input. The circuit further comprises an extra pulse eliminator coupled to the oscillator output. The extra pulse eliminator includes an extra pulse eliminator output. One or more frequency dividers may be coupled to an extra pulse eliminator output.

Abstract: Provided are a successive approximation register analog-to-digital converter and an operation method thereof. The method includes latching input signals which respectively correspond to bits of a first series of bits as digital data by directly transmitting the input signals to a latch; latching input signals which respectively correspond to bits of a second series of bits as digital data by transmitting the input signals to the latch after amplifying the input signals during a first period of amplification by using a preamplifier; and latching input signals which respectively correspond to bits of a third series of bits as digital data by transmitting the input signals to the latch after amplifying the input signals during a second period of amplification by using the preamplifier.

Abstract: An analog-to-digital converter comprises a first set of comparators configured for generating a coarse digital measurement of an analog input signal, and a second set of comparators for performing a fine digital measurement of the analog input signal. The second set comprises a plurality of dynamic comparators, wherein each dynamic comparator is configurable for being activated by a clock signal. An activation circuit processes the coarse measurement and an input clock signal for generating a set of activation signals, which activate a subset of the dynamic comparators to generate the fine digital measurement.

Abstract: A method for converting an analog signal to a digital signal is provided. Initially, a digital representation of a portion of an analog signal is generated. Residue of the analog signal is then sampled at a sampling instant so as to generate a residue sample. A signal having a frequency that is proportional to the voltage of the residue sample is generated, and the signal is measured to generate coarse and fine measurements of the frequency. A digital representation of the residue sample from the coarse and fine measurements is then generated.

Abstract: A method of calibrating a pipelined analog to digital converter having a plurality of DAC elements and an additional calibration DAC element is provided. In the method as provided herein, a combination of positive, negative and zero reference voltages are applied to the element under calibration and positive and negative reference voltages are applied to the additional calibration DAC element to obtain four calibration states. An error of the DAC element under calibration is extracted by calculating an average of the difference between the four calibration states.

Abstract: A system and method for processing an analog signal output by a sensor. The system and method converting, using at least one analog-to-digital converter (ADC), the analog output signal to a digital signal, the digital signal including a plurality of samples at a predetermined resolution, detecting whether a trigger condition is met by analyzing the digital signal, detecting an event based on trigger information from the detecting whether a trigger condition is met, generating event information having time information included therein when the event is detected, defining one or more time windows based on the time information included in the event information, performing decimation on the digital signal based on the defined one or more time windows to generate a decimated signal, and outputting the decimated signal.

Abstract: A comparator including a preamplifier amplifying a first signal and a second signal to produce a first amplified signal on a first output terminal and a second amplified signal on a second output terminal. The comparator also includes a capacitor, a clamp and a latch coupled in parallel to the first output terminal and the second output terminal of the preamplifier. A control circuit is coupled to the variable capacitor and the clamp and is configured to close the clamp during a first time period to cause the first amplified signal and the second amplified signal to bypass the capacitor and the latch, and open the clamp during a second time period following the first time period to cause the first amplified signal and the second amplified signal to be coupled to the capacitor and the latch. The capacitor filters the amplified signals, and the latch produces a digital output signal of the comparator based on the filtered signals.