Abstract: To obtain accurate digital data while using a successive approximation system when performing analog-to-digital conversion processing in a plurality of steps, an AD converter includes: a signal generation unit that generates a ramp voltage based on a count signal; a signal conversion unit including a circuit that holds an input signal voltage, a successive approximation capacitance group that outputs bias voltages according to a connection combination of capacitances having different capacitance values, and a unit that compares one of the ramp voltage and the bias voltage with the signal voltage; and a control unit generating a digital signal of the signal voltage based on a comparison result of the bias voltage and the comparison result of the ramp voltage while acquiring data for calibration of the capacitance group based on the connection combination and the ramp voltage.

Abstract: Electronic devices may include image sensors having image sensor pixels that are coupled to analog-to-digital converters (ADCs). Each ADC may be a sub-ranged ramp ADC that uses a first set of reference voltages to determine a coarse code and a second set of ramping voltages to determine a fine code. In the presence of parasitic capacitances, the reference voltages and the ramp voltages exhibit mismatch that causes the ADC to exhibit non-idealities such as missing codes. Calibration operations may be performed that involve obtaining a first code at a first predetermined input voltage level and obtaining a second code at a second predetermined input voltage level. A code correction value can then be computed based on the first and second codes. The code correction value can be selectively applied to the final ADC code to correct for missing codes.

Abstract: A higher-order DAC and a lower-order DAC each have a plurality of capacitive elements having capacitance values weighted with a binary ratio and are configured so that a first terminal of each of the capacitive elements is connected to a common node and a second terminal thereof is connected to either a first or second voltage selectively. The higher-order DAC and the lower-order DAC are coupled by a coupling capacitor. A higher-order DAC control circuit outputs either a correction control signal or a digital signal output from a successive approximation circuit selectively to the higher-order DAC. The lower-order DAC has at least one variable capacitive element of which a first terminal is connected to the common node and a second terminal is connected to either the first or second voltage selectively depending on a higher-order bit of the digital signal output from the successive approximation circuit to the higher-order DAC.

Abstract: An analog/digital converter includes: a first analog/digital conversion unit that performs digital conversion on received first analog input voltage in a first time period; a second analog/digital conversion unit that performs digital conversion on received second analog input voltage in a second time period that is different from the first time period; and a first coupling capacitor that connects the first analog/digital conversion unit and the second analog/digital conversion unit, and wherein the second analog/digital conversion unit receives, through the first coupling capacitor, first residual voltage that is remaining voltage of the first analog input voltage on which digital conversion is performed in the first analog/digital conversion unit, as the second analog input voltage.

Abstract: A counter circuit includes a first counter and a second counter. The first counter is configured to count a first counter clock signal which toggles with a first frequency to generate upper (N?M)-bit signals of N-bit counter output signals, in response to a first counting enable signal based on a first comparison signal during a coarse counting interval. N and M are natural numbers, N is greater than M, and M is greater than or equal to 3. The second counter is configured to count a second counter clock signal which toggles with a second frequency which is higher than the first frequency to generate lower M-bit signals of the N-bit counter output signals, in response to a second counting enable signal based on the first comparison signal and a second comparison signal during a fine counting interval which follows the coarse counting interval.

Abstract: A medical device and associated method convert an analog signal using an adaptable number of comparisons between the analog signal and a reference signal. The medical device includes an analog-to-digital (A/D) converter for receiving an analog signal. The A/D converter has a full scale range and a total number of bits spanning the full scale range. The A/D converter converts the analog signal to a digital signal over conversion cycles using an adaptable number of comparisons. For at least one of the conversion cycles, the adaptable number of comparisons is less than the total number of comparisons required to convert the analog signal over the full scale range of the A/D converter.

Abstract: Method and device for converting analogue signals, of a plurality of pathways, into digital signals. A common circuit (2, 3) generates first analogue signals corresponding to high-order bits of digital signals For each pathway, a first means compares the first analogue signals with the signal to be converted. A first means (18) stores high-order bits corresponding to the value of a first analogue signal close to the signal to be converted. A means (9) stores the deviation between the analogue signal to be converted and said first detected value. A generator means (11, 12) generates a predetermined number of second analogue signals. A second means compares by successive approximations said second analogue signals with said deviation. A means (20) stores said low-order bits corresponding to the results arising from said second means of comparison. A means (22) assembles said high-order bits and said low-order bits.

Abstract: A hybrid ADC having a successive approximation register (SAR) ADC mode for generating a bit of a digital signal and a ramp ADC mode for generating an additional bit of the digital signal is disclosed. When in the SAR ADC mode, a control circuit is configured to disable a ramp signal generator; disable a counter; and enable a register to control an offset stage to set the magnitude of an offset voltage that is provided to an input of a comparator of the ADC. When in the ramp ADC mode, the control circuit is configured to enable the ramp signal generator to provide a ramp signal to the input of the comparator; enable the counter to begin providing the digital count in response to the output of the comparator; and disable the register so that the offset stage is not providing the offset voltage.

Abstract: Methods and systems for analog-to-digital conversion applicable to an image sensor, such as a CMOS image sensor, in which an ADC comprises built-in redundancy such that the ADC can start its conversion cycle before the ADC input settles to a desired resolution and the ADC can yet accurately convert the ADC input to a digital value with the desired resolution. In a CMOS image sensor, such an ADC configuration enables the pixel readout time to overlap with the ADC conversion time, reducing the total time needed to convert the pixel signal value to a digital value with the desired resolution.

Abstract: An amplifier includes a common load suitable for outputting an output signal, a coarse input differential stage, coupled to the common load, suitable for amplifying a difference between an input signal and a coarse ramping signal to output a coarse conversion signal as a first output signal, when the coarse ramping signal is lower than the input signal, and a fine input differential stage, coupled to the common load, suitable for amplifying a difference between a fine ramping signal and a bias signal and compensating the first output signal to output a fine conversion signal as the output signal, when a zero crossing occurs by the compensated first output signal.

Abstract: An amplifier includes a common load suitable for outputting an output signal, a coarse input differential stage, coupled to the common load, suitable for amplifying a difference between an input signal and a coarse ramping signal to output a coarse conversion signal as a first output signal, when the coarse ramping signal is lower than the input signal, and a fine input differential stage, coupled to the common load, suitable for amplifying a difference between a fine ramping signal and a bias signal and compensating the first output signal to output a fine conversion signal as the output signal, when a zero crossing occurs by the compensated first output signal.

Abstract: A signal converting device includes: a first converting circuit arranged to receive a first inputting signal; and a first capacitive circuit coupled between an output terminal of the first converting circuit and a reference voltage; wherein the first converting circuit is arranged to generate a first converting signal on the output terminal of the first converting circuit according to the first inputting signal.

Abstract: A successive approximation analog-to-digital converter (SAR ADC) includes a capacitor array and a comparator. The capacitor array has M capacitors which are arranged to perform capacitor switching operations sequentially, wherein a sum of capacitance values of the M capacitors is equal to (2N?1) unit capacitors, M>N, and M and N are both positive integers. The comparator is arranged for comparing an output of the capacitor array and an analog input sequentially.

Abstract: The present disclosure provides a time-to-digital (TDC) converter, comprising: a coarse TDC receiving a start signal and a stop signal, delaying the first start signal in a first time unit to generate n first delayed start signals (where n is an integer equal to or larger than 2), measuring a time difference between the first delayed start signal and the stop signal in the first time unit, and generating second delayed start signals that are obtained by delaying the first delayed start signals in a time unit shorter than the first time unit; and a fine TDC receiving and delaying the second delayed start signal generated from the coarse TDC and receiving the stop signal, and measuring a time difference between the second delayed start signal and the stop signal in a second time unit.

Abstract: A re-circulating time-to-digital converter (TDC) can include a triggered reference ring oscillator (TRRO) and a delay module. The triggered reference ring oscillator can, when triggered by a reference signal edge, generate a periodic ring oscillator signal with a ring oscillator period that is a selected ratio of a voltage-controlled oscillator (VCO) period. The delay module can store, in a plurality of latches, samples of a VCO signal docked by the periodic ring oscillator signal. Each latch can generate an output of the sample, and each latch output can represent a time difference polarity between VCO signal and TRRO signal. In another example, the re-circulating TDC can include the triggered reference ring oscillator, a digital frequency lock module, and a TDC post-process module. The digital frequency lock module can generate a ring oscillator control signal, which sets the ring oscillator period for the triggered reference ring oscillator.

Abstract: The present invention is directed to signal processing systems and methods thereof. In various embodiments, the present invention provides an analog-to-digital conversion (ADC) system that includes a flash ADC portion and a time-interleaved parallel SAR portion. For an n-bit ADC process, the flash ADC portion converts k MSBs of the n bits during a single cycle, and the SAR portion converts n?k LSBs in m number of cycles. The SAR portion includes a number of SAR channels that perform A/D conversion in parallel, and the k MSB from the course flash converter is verified for errors by the SAR portion and allows a net saving of the power consumption by reducing the number of fine resolution SARs. There are other embodiments as well.

Abstract: A method, computer-readable storage medium, and signal processing apparatus for processing a plurality of input signals. The method includes receiving or generating a first intermediate signal and a second intermediate signal. The first and second intermediate signals are summed and the summed signals are output to a signal analog-to-digital converter having a predetermined sampling frequency.

Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.

Abstract: Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. One approach to increasing the dynamic range further is with a subranging architecture, whereby the output of a coarse ADC is converted back to analog and subtracted from the input signal, and the residue signal fed to a fine ADC for generation of additional significant bits. This also requires a high-gain broadband linear amplifier, which is not generally available within superconductor technology. In a preferred embodiment, a distributed digital fluxon amplifier is presented, which also integrates the functions of integration, filtering, and flux subtraction. A subranging ADC design provides two ADCs connected with the fluxon amplifier and subtractor circuitry that would provide a dynamic range extension by about 30-35 dB.

Abstract: In order to minimize noise and current consumption in an EEG monitoring system (40) which can be continuously carried by a person to be monitored, an input converter (44) for an EEG monitoring system is devised. The analog-to-digital converter of the input converter has an input stage, an output stage, and a feedback loop, and the input stage comprises an amplifier (QA) and an integrator (RLF). A voltage transformer (IT) is placed in the input converter upstream of input stage. The transformation ratio of the voltage transformer (IT) has a transformation ratio such that it provides an output voltage larger than the input voltage, thereby multiplying the signal voltage for the input stage by a fixed factor. The voltage transformer (IT) is a switched-capacitor voltage transformer having at least two capacitors (Cx, Cy, Cz). The invention further provides a method of converting an analog signal, and an EEG monitoring system comprising the input converter (44).

Abstract: A data acquisition device incorporates a front end analog-to-digital converter (ADC), which is responsive to an applied analog input signal, sample that signal and provide digital data representative of the sampled signal. The digital data is applied to a data channel connected to a data acquisition memory, which stores data values representative of the sampled analog input signal. The digital data from the ADC is also applied to a real time a trigger channel connected to a composite function trigger equalizer and filter, a trigger processor and to a trigger memory. The trigger channel operates in real time to identify trigger events and store real-time trigger event occurrence signals in the trigger memory. A controller reads out the stored data values from the data acquisition memory by way of a data equalizer, in synchronism with corresponding real-time trigger event occurrence signals from the trigger memory.

Abstract: A method utilized in an analog-to-digital conversion apparatus, for converting an analog input signal into a digital output signal including a first portion and a second portion, includes: using a comparator circuit to compare the analog input signal with at least one first reference level to generate a preliminary comparison result, the at least one first reference level being used for determining the first portion; estimating the first portion according to the preliminary comparison result; based on the preliminary comparison result, performing the successive approximation procedure to obtain a posterior comparison result according to a plurality of second reference levels, the second reference levels being used for determining the second portion; and, estimating the second portion according to the posterior comparison result. The preliminary and posterior comparison results are generated by the comparator circuit.

Abstract: A data processing device includes a clock converter, a data converter, and an error detector. The clock converter is configured to receive a first clock signal, convert the first clock signal into a second clock signal, and output the second clock signal. The data converter is configured to receive first data, convert the first data into second data using the second clock signal, and output the second data. The error detector is configured to check whether the first clock signal is in a first clock state or a second clock state upon the first data transitioning to a first data state, and output an enable signal to the clock converter upon determining that the first clock signal has transitioned to the first clock state from the second clock state.

Abstract: A low-power and high-speed ADC includes: a successive approximation converter circuit configured to sequentially compare and coarsely convert the analog input signal voltage into a digital signal with a number of higher-order bits, and also to output a residual voltage; a fixed-quantity change time measurement converter circuit configured to finely convert the residual voltage into a digital signal with a number n of lower-order bits by changing the residual voltage at a fixed rate of change and by measuring the time until a predetermined value is reached; and an encoder circuit configured to generate a digital signal with the predetermined number of bits by combining the digital signal with the number of higher-order bits output from the successive approximation converter circuit and the digital signal with the number of lower-order bits output from the fixed-quantity change time measurement converter circuit.

Abstract: The present disclosure provides a time-to-digital (TDC) converter, comprising: a coarse TDC receiving a start signal and a stop signal, delaying the first start signal in a first time unit to generate n first delayed start signals (where n is an integer equal to or larger than 2), measuring a time difference between the first delayed start signal and the stop signal in the first time unit, and generating second delayed start signals that are obtained by delaying the first delayed start signals in a time unit shorter than the first time unit; and a fine TDC receiving and delaying the second delayed start signal generated from the coarse TDC and receiving the stop signal, and measuring a time difference between the second delayed start signal and the stop signal in a second time unit.

Abstract: A circuit including first and second reference ladders, a selection circuit, first and second analog to digital converters (ADCs), and a summer. The first reference ladder is configured to provide first reference voltages via first taps. The selection circuit is configured to select one of the first reference voltages. The second reference ladder is configured to, based on the selected one of the first reference voltages, provide second reference voltages via second taps. The first ADC is configured to convert the first version of the analog input signal to a first digital signal. The second ADC is configured to, based on the second reference voltages, convert the second version of the analog input signal to a second digital signal. The summer is configured to generate a digital output signal based on the first and second digital signals.

Abstract: An A/D conversion device generates a control clock signal having a cycle that is an integral multiple of a cycle of a reference clock signal. A shift voltage is generated which varies every cycle of the reference clock signal while the cycle of the control clock signal is taken as one cycle. An analog signal is offset by the shift voltage. The offset analog signal is converted to a digital signal every cycle of the reference clock signal. Outputs from the A/D converter are averaged every cycle of the control clock signal.

Abstract: A system and method is disclosed for an imaging device and/or an analog to digital converter which converts an analog input signal to a digital data signal using a comparator which compares the analog input signal to a first ramped reference signal to determine an operating point and then uses the same comparator to compare the analog input signal to a second ramped reference signal multiple times about the determined operating point.

Abstract: A circuit arrangement for detecting and digitizing an analog input signal and to a field device for process instrumentation, wherein the field device comprises such a circuit arrangement which includes a first electronics unit, a second electronics unit, and an interface by which the two electronics units are galvanically separated from each other. A first signal is generated at a first frequency in the second electronics unit. A voltage frequency converter, to which the analog input signal is routed, uses a reference frequency to generate a second signal at a second frequency that corresponds to the level of the analog input signal. After the second signal has been transmitted to the second electronics unit using an optical coupler, a ratiometric measurement of the second frequency is performed in the second electronics unit dependent on the first frequency using a capture timer.

Abstract: Systems, methods, and devices for obtaining data from a data location. The method may include generating a first value by sensing a data location under a first condition and generating a second value by sensing the data location under a second condition. The method may further include combining the first value with the second value to identify data conveyed by the data location.

Abstract: Representative implementations of devices and techniques provide analog to digital conversion of time-discrete analog inputs. A redundant split-capacitor arrangement using a successive approximation technique can provide a fast and power efficient ADC. For example, a successive approximation capacitor arrangement may include multiple arrays with non-binary bit weights.

Abstract: An input circuitry for an ADC constituted of: a first resistor coupled to an input of the ADC; a second resistor coupled to the input of the ADC and arranged to provide a current path; an electronically controlled switch coupled to the first resistor and arranged to provide a parallel current path through the first resistor; and a control circuitry; wherein the control circuitry is arranged to operate in a high current mode in the event that the input current exhibits an intensity within a first predetermined range and is arranged to operate in a low current mode in the event that the input current exhibits an intensity within a second predetermined range, different than the first predetermined range, wherein, in the high current mode the control circuitry is arranged to close the electronically controlled switch and in the low current mode is arranged to open the electronically controlled switch.

Abstract: Time-to-digital converter system including: an event detector configured for detecting an event and generating an event detection signal upon detection of the event; and a time-to-digital converter coupled or connectable to the event detector and including a fine resolution part configured for counting fine time intervals, organized such that the fine resolution part is activated in response to the event detection signal and deactivated in response to a reference clock. 3D imager including an array of pixels, with in each pixel such a time-to-digital converter system, and further including a reference clock generator.

Abstract: An analog to digital converter (ADC) can include a multi-input comparison unit configured to compare a pixel voltage from an image sensor, a comparison voltage comprising a stepped voltage modified during a coarse mode of operation, and a ramp voltage comprising a ramped voltage modified to one another during a fine mode of operation, to provide a comparison result signal that indicates whether the comparison voltage combined with the ramp voltage is greater than or less than the pixel voltage. A selection control signal generation unit can receive the comparison result signal and a mode control signal, to indicate the coarse or fine mode, to provide a selection control signal allowing modification of the comparison voltage in the coarse mode and to hold the comparison voltage constant in the fine mode. A reference voltage selection unit can receive the selection control signal to control modification of the comparison voltage.

Abstract: A hand-held device having a touch sensitive surface uses a relative distance from an origin location to each of a plurality of touch zones of the touch sensitive surface activated by a user to select a one of the plurality of touch zones as being intended for activation by the user.

Abstract: An analog to digital converter that comprises a successive approximation register (SAR) having an n bit binary output, a first capacitor array connected to receive some of the bits of the binary output, a second capacitor array connected to receive the remaining bits of the binary output, and a comparator including an output connected to the SAR. The first and second capacitor arrays each have an analog output indicative of the charge stored by capacitors of that array. The comparator includes a pair of inputs, one of which is connected to the analog output of the first capacitor array and the other of which is connected to the analog output of the second capacitor array.

Abstract: In one embodiment, an integrated circuit includes a pin and a current source for driving current through the pin into an external resistor such as a resistor on a circuit board to generate a pin voltage. The integrated circuit includes an analog-to-digital converter for converting the pin voltage into a digital value, such as an address for the integrated circuit.

Abstract: A data converter module is provided with an analog interface to receive analog signals, a digital interface to transmit digital signals, and a configuration interface to accept configuration signals. The data conversion module also includes a data conversion array (DCA) with selectively engageable data conversion circuits for the conversion of analog input signals to digital output signals, where the data conversion circuits are responsive to the configuration signals. The DCA's data conversion circuits include configurable data resolution circuits and configurable data conversion speed circuits. For example, the configurable data resolution circuits may be selected from averaging, oversampling, and multi-stage pipelining circuits. The DCA configurable data speed circuit may interleave the outputs from multiple parallelly connected ADCs operating at different clock phases. In one aspect, the number of clock phases is selectable. Also provided are methods for configurable data conversion.

Abstract: An analog to digital converter in accordance with the inventive concept may include a reference voltage generation circuit outputting first and second reference voltages; a decompression part decompressing amplitude of an analog input signal and the first and second reference voltages; a flash ADC converting the decompressed analog input signal into a first digital signal with reference to the decompressed first and second reference voltages; and a successive approximation ADC converting the analog input signal into a second digital signal according to a successive approximation operation with reference to the first digital signal and the first and second reference voltages.

Abstract: A solid-state image sensing device comprises a pixel which outputs a pixel signal, a first conversion unit which converts the pixel signal into a digital signal with a first bit length, and a second conversion unit which converts, into a digital signal with a second bit length, an analog signal obtained by subtracting, from the pixel signal, an analog signal corresponding to the digital signal with the first bit length. The second conversion unit comprises a current source, a first capacitance, and a switching unit for switching a supply destination of a current supplied from the current source to one of the first capacitance and a reference potential. The second conversion unit performs the conversion based on comparison between a reference voltage and the analog signal which is charged in the first capacitance and is obtained as a subtraction result.

Abstract: An integrated circuit with a pipeline analog-to-digital (A/D) converter and associated calibration circuitry is provided. The A/D converter may include multiple series-connected pipeline stages at least some of which are implemented using a switched capacitor configuration. The calibration circuitry may include an analog error correction circuit, a digital error correction circuit, and a calibration control circuit for coordinating the operation of the analog and digital error correction circuits. During calibration operations, the analog error correction circuit may be used to suitably adjust a gain setting for each pipeline stage, whereas the digital error correction circuit may be used to compute a code offset value for each pipeline stage. Calibration may proceed from a least-significant-bit pipeline stage towards a most-significant-bit pipeline stage, one stage at a time.

Abstract: A method of configuring an analog-to-digital converter (ADC) includes configuring the ADC to operate in one of a low-pass filter mode and a band-pass filter mode according to a value of a control signal. In at least one embodiment, the method further includes configuring an integrator gain of the ADC and a feed-forward gain of the ADC based on selection of one of a low-intermediate frequency (LIF) mode and a zero-intermediate frequency (ZIF) mode.

Abstract: First and second track and hold stages track and store an input voltage for a sample of an analog input signal. A coarse reference ladder provides a plurality of coarse references. The coarse reference ladder includes a first coarse reference and a second coarse reference ladder. A coarse ADC performs a first comparison of the input voltage and the coarse references and outputs a coarse output based on the first comparison. A switch matrix includes switches and is configured to close a switch corresponding to a coarse reference based on the coarse output. A fine reference ladder provides fine references. A fine ADC performs a second comparison of the input voltage and the fine references and outputs a fine output based on the second comparison. Logic outputs a digital output for the sample of the analog input signal based on the coarse output and the fine output.

Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

Abstract: A clock generation circuit includes first and second logic circuits and a switch circuit. The first logic circuit has a first circuit threshold value lower than a circuit threshold value of a front-stage circuit, receives an input clock output from the front-stage circuit, and outputs a first output signal in accordance with a logic state of the input clock and the first circuit threshold value. The second logic circuit has a second circuit threshold value higher than the circuit threshold value of the front-stage circuit, receives the input clock output from the front-stage circuit, and outputs a second output signal in accordance with the logic state of the input clock and the second circuit threshold value. The switch circuit receives the first and second output signals and outputs, as an output clock, one of first and second voltages corresponding to different logic states.

Abstract: A data converter module is provided with an analog interface to receive analog signals, a digital interface to transmit digital signals, and a configuration interface to accept configuration signals. The data conversion module also includes a data conversion array (DCA) with selectively engageable data conversion circuits for the conversion of analog input signals to digital output signals, where the data conversion circuits are responsive to the configuration signals. The DCA's data conversion circuits include configurable data resolution circuits and configurable data conversion speed circuits. For example, the configurable data resolution circuits may be selected from averaging, oversampling, and multi-stage pipelining circuits. The DCA configurable data speed circuit may interleave the outputs from multiple parallelly connected ADCs operating at different clock phases. In one aspect, the number of clock phases is selectable. Also provided are methods for configurable data conversion.

Abstract: An analog to digital converter with increased sub-range resolution. The device includes an analog front end that produces an analog communication signal, a digital front end that receives a digital communication signal, and an Analog to Digital Converter (ADC) that samples the analog communication signal across a full-range. The ADC includes a full-range ADC having a first quantization accuracy configured to sample the analog communication signal across the full-range and a central sub-range ADC having a second quantization accuracy greater than the first quantization accuracy and configured to sample the analog communication signal across a central sub-range of the full-range. The ADC also includes signal combining circuitry configured to process outputs of the full-range ADC and the central sub-range ADC to create the digital communication signal.

Abstract: A switched capacitor amplifier having an amplification unit adapted to amplify a differential signal; a first switched capacitor block including a first plurality of capacitors operable to sample a first differential input signal during a first sampling phase and to drive the amplification unit during a first drive phase; and a second switched capacitor block including a second plurality of capacitors operable to sample a second differential input signal during a second sampling phase and to drive the amplification unit during a second drive phase.

Abstract: An AD conversion circuit includes a reference signal generation unit, which generates a reference signal, a comparison unit, which ends a comparison process at a timing at which the reference signal has satisfied a predetermined condition with respect to the analog signal, a first path in which a signal is transferred through each of n delay units, a clock signal generation unit, which outputs a lower-order phase signal, a latch unit, which latches the lower-order phase signal, a higher-order count unit including a first counter circuit, which acquires a higher-order count value by performing a count operation using a signal output from any one of the delay units, a calculation unit, which generates a lower-order count signal, and a lower-order count unit, which acquires a lower-order count value by performing the count operation using the lower-order count signal.

Abstract: A random estimation analog-to-digital converter for converting a first analog signal into a digital signal includes a random bit generator, a digital-to-analog converter, a summer, an M-bit analog-to-digital converter, and a digital combiner. The random bit generator generates random least significant bits (LSBs) and the digital-to-analog converter then converts the random LSBs into a second analog signal. The summer subtracts the second analog signal from the first analog signal in the analog domain. The M-bit analog-to-digital converter then converts the modified first analog signal into the most significant bits (MSBs) of the digital image signal. The digital combiner combines the random LSBs with the MSBs in the digital domain to generate the digital signal. In one example, the random LSBs are extra bits that are beyond the maximum resolution of the M-bit analog-to-digital converter.