Single Comparator And Counter Patents (Class 341/164)
  • Patent number: 10825336
    Abstract: Systems, methods, and computer-readable media are presented herein for providing lower level physical-layer gateway functionalities and upper-level application functionalities; a system designed with flexible configurations in order to support a wide range of connected applications. The system includes a processor that executes machine instructions to perform operations. The operations comprise: receiving sensor data from a sensor device located in a building; converting the sensor data from a raw state to a physical measurement; and activating an abatement device situated in the building as a function of the physical measurement.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: November 3, 2020
    Assignee: INTWINE CONNECT, LLC
    Inventor: David Martin
  • Patent number: 10630309
    Abstract: A signal receiver includes a multiplexer, a sub-sample analog-to-digital converter (ADC) and a received signal strength indicator (RSSI) estimator for a signal receiver with multiple stage cascade amplifiers architecture. The multiplexer may select one of the input signal of each stage of cascade amplifiers or the last stage output signal of cascade amplifiers as a selected signal according to a selection signal. The sub-sample ADC may perform a sub-sampling operation using the selected signal to generate sampled data. The RSSI estimator may calculate a RSSI value corresponding to the selected signal according to the sampled data.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: April 21, 2020
    Assignee: Uniband Electronic Corp.
    Inventors: Yiping Fan, Li-Feng Chen
  • Patent number: 10582138
    Abstract: An image sensor may include an array of dual conversion gain image pixels arranged in rows and columns. The image pixels arranged along the same column may be coupled to a column line. The column line may be coupled to anti-eclipse control circuitry. In one suitable arrangement, the anti-eclipse control circuitry may include a comparator that compares the output signal on the column line to an anti-eclipse bias voltage. If, during a reset sampling period, the output signal on the column line is less than the anti-eclipse bias voltage, a current source may be used to charge the bottom plate of a dual conversion gate capacitor in the selected image pixel to help restore the voltage of the floating diffusion node in the selected pixel.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: March 3, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Pawan Gilhotra, Nirav Dharia
  • Patent number: 10530380
    Abstract: An image detector includes an array of detector unit cells including a plurality of unit cells and a plurality of single slope analog to digital converters (SSADCs). Each of the plurality of SSADCs is coupled to an output of a different one of the unit cells. Each each of the plurality of SSADCs includes: a comparator having a positive input and a negative input and a comparator output, the comparator being contained in a first layer; and a counter coupled to the comparator output and contained in a second layer. The counter is electrically coupled to the comparator with a through a silicon via.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: January 7, 2020
    Assignee: RAYTHEON COMPANY
    Inventors: Eric J. Beuville, Matthew T. Kuiken, Joshua J. Cantrell, Mark A. Massie
  • Patent number: 10057528
    Abstract: A circuit for reading a pixel matrix array comprises, for each column of pixels of the matrix array: voltage-to-delay converting circuits receiving, on an input, a voltage value representative of the voltage of a read conductor of a respective column of pixels of the matrix array and delivering as output a binary signal called a comparative signal, this signal switched at a time dependent on the input voltage value; frequency-multiplying circuits, one for each of the voltage-to-delay converting circuits, receiving as input a primary clock signal and delivering as output secondary clock signals of multiplied frequency; and binary counters, receiving, on a first input, a the secondary clock signal, and, on a second input, a the binary comparative signal and counting at a rate dictated by the secondary clock signal until the binary comparative signal switches. An image sensor comprising a matrix array of pixels, in particular active pixels, and a read circuit is also provided.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: August 21, 2018
    Assignee: PYXALIS
    Inventor: Christian Liabeuf
  • Patent number: 9859910
    Abstract: An analog to digital converter includes a first DAC unit configured to vary a level of a reference voltage output through a first node according to a first code, a second DAC unit coupled in parallel to the first DAC unit on the basis of the first node and configured to vary the level of the reference voltage according to a second code, a comparator configured to generate a comparison result signal by comparing an input voltage and the reference voltage, and at least one register array configured to store the first code and the second code with initial values and store the first code and the second code by varying values of the first code and the second code according to the comparison result signal.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: January 2, 2018
    Assignee: SK hynix Inc.
    Inventors: Dong Hyun Kim, Soon Ku Kang, Kwan Su Shon, Yo Han Jeong, Eun Ji Choi
  • Patent number: 9608693
    Abstract: A signal reception arrangement includes a receiver circuit having a receiver input configured to be coupled to a secondary winding of a transformer of a first communication channel, a first output for providing a data output signal, and a second output. The receiver circuit is configured to evaluate a signal level at the receiver input and to detect a signal transmission when the signal level reaches a given threshold, and generate a feedback signal dependent on a detection of the signal transmission.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: March 28, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Marcus Nuebling, Jens Barrenscheen
  • Patent number: 9514713
    Abstract: A timing controller, a source driver, and a display driver integrated circuit (DDI) having improved test efficiency and a method of operating the DDI are provided. The timing controller includes a code generation unit for generating a first code from display data, a protocol encoder for generating a data sequence including the display data and the first code, and a transmission unit for providing the data sequence to a source driver through a link.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: December 6, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Myung Lee, Young-Min Choi, Jae-Youl Lee, Han-Su Pae, Dong-Hoon Baek, Young-Hun Lee, Kil-Hoon Lee
  • Patent number: 9496884
    Abstract: System and method of calibrating the DC offsets of alternate comparators in an ADC in the background based on the digital outputs of the ADC. In parallel with A/D conversion of a plurality of samples, the calibration logic uses two counters to count the occurrences of the ADC outputs that represent samples falling in a first analog range and a second analog range, respectively. The two ranges are symmetric about the MSB reference voltage and in combination cover the nominal voltage range of the bit. The DC offset is derived based on a ratio of the difference between the two counts and a sum of the two counts. The calibration logic may alternately calibrate the comparators. Each comparator may be calibrated successively based on various bits associated therewith.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: November 15, 2016
    Assignee: Applied Micro Circuits Corporation
    Inventors: Yehuda Azenkot, Nanda Govind Jayaraman
  • Patent number: 9417734
    Abstract: A module operates in a proximity detection mode and a gesture detection mode. The module includes an illumination source, radiation sensors and a controller. When in proximity detection mode, the illumination source emits radiation, the radiation sensors measure the radiation level, and the controller adjusts the measured radiation level to substantially cancel the contribution attributable to ambient radiation to determine the presence of a proximate object by. When in the gesture recognition mode, the level of radiation incident on the sensors is individually sampled, and the controller determines object movement by comparing the changes in the measured radiation levels over a plurality of the samples. Ambient radiation contribution is not removed from the sampled radiation levels during the gesture recognition mode.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: August 16, 2016
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventors: Jeffrey M. Raynor, Andrew Scott
  • Patent number: 9325335
    Abstract: A comparator circuit suitable for use in a column-parallel single-slope analog-to-digital converter comprises a comparator, an input voltage sampling switch, a sampling capacitor arranged to store a voltage which varies with an input voltage when the sampling switch is closed, and a local ramp buffer arranged to buffer a global voltage ramp applied at an input. The comparator circuit is arranged such that its output toggles when the buffered global voltage ramp exceeds the stored voltage. Both DC- and AC-coupled comparator embodiments are disclosed.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: April 26, 2016
    Assignee: TELEDYNE SCIENTIFIC & IMAGING, LLC
    Inventor: Mihail M. Milkov
  • Patent number: 9285465
    Abstract: An analog-digital conversion circuit (ADC1) includes: a capacitor (C1); a charge and discharge control section (6) that puts, into the capacitor (C1), an electric charge corresponding to an input current of a first period and that causes an electric charge corresponding to an input current of a second period to be discharged from the capacitor (C1); and a digital conversion section (5) that converts an amount of electric charge of the capacitor (C1) into a digital signal.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: March 15, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hideki Sato, Takahiro Inoue
  • Patent number: 9204075
    Abstract: A solid-state imaging device and a camera system are provided. The solid-state imaging device capable of performing an intermittent operation includes a pixel unit and a pixel signal readout unit for reading out a pixel signal from the pixel unit in units of a plurality of pixels for each column. The pixel signal readout circuit includes a plurality of comparators and a plurality of counters whose operations are controlled by outputs of the comparators. Each of the comparators includes an initializing switch for determining an operating point for each column at a start of row operation, and is configured so that an initialization signal to be applied to the initializing switch is controlled independently in parallel only a basic unit of the initialization signal used for a horizontal intermittent operation, and the initializing switch is held in an off-state at a start of non-operating row.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: December 1, 2015
    Assignee: Sony Corporation
    Inventor: Kenichi Tanaka
  • Patent number: 9191011
    Abstract: A double data rate (DDR) counter includes a clock selection unit suitable for selectively inverting a first counting clock based on a control signal and for outputting a second counting clock, a first latch stage suitable for latching the second counting clock based on a counting enable signal and for outputting the least significant bit (LSB) of the DDR counter, a determination unit suitable for generating the control signal based on the last bit state of the LSB in a reset counting period, and a second latch stage suitable for receiving the LSB as a clock input to generate a higher bit of the LSB at least in a main counting period.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: November 17, 2015
    Assignee: SK Hynix Inc.
    Inventor: Won-Seok Hwang
  • Patent number: 9184753
    Abstract: A double data rate (DDR) counter includes a first control block suitable for toggling a counter clock according to a count mode signal and a previous state value of a sampling block; a second control block suitable for determining whether to toggle a clock signal inputted to a counting block corresponding to an (LSB+1) bit or higher; a third control block suitable for determining an enable period of the counting block; the sampling block suitable for sampling a state of the clock signal and outputting an LSB value, when an input signal transits; and the counting block suitable for performing counting according to output signals of the second and third control blocks and outputting a counter output signal having the (LSB+1) bit or higher.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: November 10, 2015
    Assignee: Sk Hynix Inc.
    Inventor: Min-Seok Shin
  • Patent number: 9083376
    Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: July 14, 2015
    Assignee: MAXLINEAR, INC.
    Inventors: Kaveh Moazzami, Pawan Tiwari, Gaurav Chandra
  • Patent number: 9041581
    Abstract: An analog-to-digital conversion apparatus 10 comprises a plurality of analog-to-digital converters 30 and a ramp generator 20. Each of the analog-to-digital converters 30 comprises an analog signal input for receiving an analog signal level and a ramp signal input. A control stage is arranged to compare the ramp signal with the analog signal level and, based on the comparison, to enable a counter provided at the analog-to-digital converter or to latch a digital value received from a counter. The control stage comprises a comparator in the form of a first differential amplifier with a first branch connected to the input for receiving the ramp signal, a second branch connected to the analog signal input and an output, and a biasing current source for biasing the first differential amplifier. A feedback circuit controls the biasing current source.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: May 26, 2015
    Assignee: CMOSIS BVBA
    Inventor: Bram Wolfs
  • Patent number: 9041579
    Abstract: An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N?2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.
    Type: Grant
    Filed: January 18, 2014
    Date of Patent: May 26, 2015
    Assignee: CMOSIS BVBA
    Inventors: Guy Meynants, Bram Wolfs, Jan Bogaerts
  • Publication number: 20150123832
    Abstract: A comparator includes a first amplification unit suitable for differentially amplifying a pixel signal and a ramp signal, a second amplification unit suitable for amplifying a signal outputted from the first amplification unit and outputting a comparison result, a current control unit suitable for controlling a current flow in response to the comparison result and a current compensation and noise removal unit suitable for compensating for current and removing noise under control of the current control unit.
    Type: Application
    Filed: December 15, 2013
    Publication date: May 7, 2015
    Applicant: SK hynix Inc.
    Inventor: Young-Chul SOHN
  • Patent number: 9019138
    Abstract: A solid-state imaging device having an analog-digital converter, and an analog-digital conversion method are described herein. An example of a solid-state imaging device includes a column processing section that includes a low-level bit latching section. The low-level bit latching section receives a comparator output from a comparator and a count output from a counter, and the low-level bit latching section latches a count value.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: April 28, 2015
    Assignee: Sony Corporation
    Inventor: Hiroyuki Iwaki
  • Patent number: 9019137
    Abstract: A charge canceling multiplying digital-to-analog converter (MDAC) is provided with a reference block having inputs to accept reference voltages each sample clock cycle. The MDAC includes a sampling block having inputs to accept differential analog input voltage signals each sample clock cycle. A differential amplifier has a negative input and positive input connected to the reference block and sampling block to receive differential amplifier input signals, and a positive output and a negative output to supply differential output voltage signals each amplify clock cycle. The sampling section includes a first pair of feedback capacitors connected between the differential amplifier negative input and positive output, and a second pair of feedback capacitors connected between the differential amplifier positive input and negative output each amplify clock cycle. A capacitor from the first pair of parallel feedback capacitors is swapped with a capacitor from the second pair prior to each sample clock cycle.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: April 28, 2015
    Assignee: IQ-Analog Corporation
    Inventors: Mikko Waltari, Michael Kappes
  • Patent number: 9015394
    Abstract: Chip select (‘CS’) multiplication in an SPI system that includes an SPI master, a CS multiplier, a plurality of SPI slaves, and a fall time detection circuit, where the SPI master is coupled to the CS multiplier and the fall time detection circuit by a CS signal line, the CS multiplier includes a plurality of CS outputs with each CS output coupled to an SPI slave, and CS multiplication includes: receiving, from the SPI master, the CS signal on the CS signal line; detecting fall time of the CS signal; and, if the fall time of the CS signal is less than a predefined threshold, configuring, by the fall-time detection circuit, the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: April 21, 2015
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Michael DeCesaris, Steven C. Jacobson, Luke D. Remis, Gregory D. Sellman
  • Patent number: 9000968
    Abstract: An analog to digital converter (ADC) includes a clock-halting circuit that is enabled by an externally generated trigger signal. The clock-halting circuit halts an input clock signal to the ADC for a predetermined time period and resumes the input clock signal to the ADC when the predetermined time period ends.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: April 7, 2015
    Assignee: Freescale Semiconductor, Inc
    Inventors: Sunny Gupta, Kumar Abhishek, Nitin Pant
  • Patent number: 8988267
    Abstract: According to an embodiment, a signal processing device includes an integrator, a setting unit, and an analog-to-digital converter. The integrator is configured to integrate an electrical charge corresponding to electromagnetic waves. The integrator includes a capacitor configured to store the electrical charge corresponding to the electromagnetic waves and a discharging circuit configured to discharge the capacitor. The setting unit is configured to set a period of integration of the electrical charge with respect to the integrator. The analog-to-digital converter includes a comparator configured to compare an integration output and a threshold value and a counter configured to output, as digital data of the electrical charge, the number of times for which a value of the integration output becomes not less than the threshold value. The converter is configured to discharge the capacitor during the period of integration by supplying a comparison output of the comparator to the discharging circuit.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shunsuke Kimura, Hideyuki Funaki, Go Kawata, Tetsuro Itakura, Masanori Furuta
  • Patent number: 8981983
    Abstract: An A/D conversion circuit in which a counter is made to be capable of performing counting at both edges of a clock, up/down count values can be switched while the up/down count values are held, and the duty of the counting operation is difficult to be distorted even with the both-edge counting, a solid-state image sensor, and a camera system.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: March 17, 2015
    Assignee: Sony Corporation
    Inventor: Yasuaki Hisamatsu
  • Publication number: 20150029372
    Abstract: Provided is an image sensor including a sensor array including a plurality of pixels arranged in rows and columns. The image sensor may include a ramp signal generator which may generate a ramp signal. The intensity of the ramp signal may increase or decrease in response to a ramp enable signal. The image sensor may include an analog-digital converter electrically connected to one of the columns of the pixels. The analog-digital converter may be configured to compare an output signal from the one of the columns of the pixels with the ramp signal, thereby generating time information. The analog-digital converter may be configured to convert the time information to digital information in response to a counter enable signal. An activation of the counter enable signal may be delayed by a predetermined time delay, compared with that of the ramp enable signal.
    Type: Application
    Filed: June 20, 2014
    Publication date: January 29, 2015
    Inventors: Hyeokjong Lee, Jinho Seo, Seogheon Ham
  • Publication number: 20150001379
    Abstract: In the field of imaging devices comprising a detector generating electric charges in response to incident photon radiation, and an analog-to-digital conversion circuit forming means for reading the quantity of electric charges generated, an analog-to-digital conversion circuit comprises: a comparator which can switch depending on the comparison between a potential on an integration node and a predetermined threshold potential, a counter incrementing with each switch of the comparator, a counter-charge injection circuit injecting a quantity Qc of counter-charges on the integration node with each switch of the comparator, and control means which determine the quantity Qc of counter-charges injected. The analog-to-digital conversion circuit is characterized in that the control means determine the quantity Qc of counter-charges injected as a function of a value of the counter.
    Type: Application
    Filed: November 14, 2012
    Publication date: January 1, 2015
    Inventor: Jean-Luc Moro
  • Patent number: 8902092
    Abstract: An analog-digital conversion circuit includes a comparator that receives an analog input signal. A controller generates an N1-bit first signal and an N2B-bit second signal in accordance with an output signal from the comparator. A first digital-analog converter generates a first reference signal from the first signal. A second digital-analog converter generates a second reference signal from the second signal. A correction circuit corrects the first and second signals to generate a digital output signal. The N2B-bit second signal is acquired by adding a Kbit correction signal to an N2A-bit signal. The controller sequentially sets bit values of the first signal and bit values of the second signal in accordance with the output signal of the comparator. The correction circuit generates the (N1+N2A)-bit digital output signal based on a sum of a value acquired by multiplying the N1-bit first signal by 2^N2A and a value of the N2B-bit second signal.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: December 2, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hidetaka Haneda
  • Patent number: 8873644
    Abstract: Self-monitoring reset circuitry is presented for use in analog-to-digital converters and other modulator circuitry with capacitively coupled isolation barriers in which the modulator output data is monitored for inactivity by a reset circuit synchronized to the modulator clock, and extra pulses are selectively introduced into the data prior to transmission across the isolation barrier if no modulator state changes occur within a predetermined number of clock cycles to provide a predictable data output value for each end of the analog input range and to reset the output to the correct state in situations where transient noise toggles the output and the modulator output is static.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: October 28, 2014
    Assignees: Texas Instruments Deutschland GmbH, Texas Instruments Incorporated
    Inventors: James Lee Todsen, Caspar Petrus Laurentius van Vroonhoven
  • Patent number: 8847809
    Abstract: An A/D converter suitable for use in a system in which the signal power of noise increases with the signal power of the signal, such as an imaging system, utilizes a variable quantization system for converting analog signals into digital signals. The variable quantization is controlled so that low signal levels the quantization is similar or identical to conventional A/D converters, while the quantization level is increased at higher signal levels. Thus, higher resolution is provided at low signal levels while lower resolution is produced at high signal levels.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: September 30, 2014
    Assignee: Round Rock Research, LLC
    Inventor: Alexander I. Krymski
  • Patent number: 8836840
    Abstract: An A/D converter includes: a first comparator that compares an input signal, with a first reference signal which is a ramp wave having a predetermined polarity, and that when the input signal matches the first reference signal, reverses an output signal thereof; a second comparator that compares the input signal, with a second reference signal which is a ramp wave having a different polarity from the first reference signal, and that when the input signal matches the second reference signal, reverses an output signal thereof; and a counter capable of counting up so as to measure the comparison times taken by the first comparator and second comparator, wherein when either of the output signal of the first comparator and the output signal of the second comparator is first reversed, the counter ceases a counting action.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: September 16, 2014
    Assignee: Sony Corporation
    Inventor: Manabu Kukita
  • Patent number: 8830105
    Abstract: Systems, methods, and devices for obtaining data from a data location. The method may include generating a first value by sensing a data location under a first condition and generating a second value by sensing the data location under a second condition. The method may further include combining the first value with the second value to identify data conveyed by the data location.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: September 9, 2014
    Assignee: Micron Technology, Inc.
    Inventor: R. Jacob Baker
  • Patent number: 8803725
    Abstract: A single slope AD converter circuit includes a comparator that compares a ramp voltage varying with a predetermined slope as time elapses with an analog input voltage, a counter that counts a predetermined clock in parallel with the comparing process of the comparator, and a controller that outputs a clock count value corresponding to elapsed time when the ramp voltage is smaller than the analog input voltage, as an AD converted first digital value. The comparator compares the ramp voltage with a predetermined first reference voltage, the counter counts the clock in parallel with the comparing process, and the controller outputs the clock count value corresponding to the elapsed time as an AD converted second digital value.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: August 12, 2014
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Yuji Osaki, Tetsuya Hirose
  • Publication number: 20140218224
    Abstract: Methods and circuits for controlling an automatic gain control (AGC) circuit wherein the AGC circuit is used to adjust the gain of a signal input to an analog to digital converter. The method includes obtaining a plurality of samples from the output of the analog to digital converter and determining whether the amplitude of each sample is greater than a threshold amplitude value. If the amplitude of a sample is greater than the threshold amplitude value then a counter value is incremented. The target average amplitude of the automatic gain control circuit is then periodically adjusted based on the counter value.
    Type: Application
    Filed: January 17, 2014
    Publication date: August 7, 2014
    Applicant: IMAGINATION TECHNOLOGIES, LTD.
    Inventors: Hugh Jackson, Paul Rowland
  • Publication number: 20140203956
    Abstract: An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N?2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.
    Type: Application
    Filed: January 18, 2014
    Publication date: July 24, 2014
    Applicant: CMOSIS NV
    Inventors: Guy Meynants, Bram WOLFS, Jan BOGAERTS
  • Patent number: 8773552
    Abstract: According to one embodiment, a pixel outputs a photoelectrically converted signal. A reference ramp generating circuit generates a first ramp wave and a second ramp wave having a step width smaller than that of the first ramp wave. A column ADC circuit performs switching between the first ramp wave and the second ramp wave on the basis of the signal level of the signal from the pixel, compares the ramp wave with the signal level, and detects a signal component of the pixel by CDS.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: July 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshitaka Egawa
  • Publication number: 20140183336
    Abstract: A reference signal generating circuit, an AD conversion circuit, and an imaging device are provided. A clock generating unit includes a delay section including delay units, each of which delays an input signal and outputs a delayed signal, and outputs a low-order phase signal based on a signal output from the delay section. A high-order current source cell unit includes high-order current source cells, each of which generates the same constant current. A low-order current source cell unit includes low-order current source cells weighted to generate constant currents having current values that differ by a predetermined proportion of a current value of the constant current generated by the high-order current source cell. Selection of the high-order current source cell is performed based on a clock obtained by dividing a clock based on the low-order phase signal.
    Type: Application
    Filed: November 26, 2013
    Publication date: July 3, 2014
    Applicant: OLYMPUS CORPORATION
    Inventor: Yoshio Hagihara
  • Patent number: 8766842
    Abstract: An analog to digital detector circuit includes a comparator circuit and a counter that generates a digital counter value. A digital to analog converter receives an inverse of the digital counter value of the counter and generates a first voltage. A variable current source receives the digital counter value of the counter and generates a first current.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: July 1, 2014
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Luca Bertolini, Andrea Milanesi, Paolo Boi
  • Publication number: 20140167999
    Abstract: An analog to digital conversion device and method utilizing an array of state sensitive cells. A gate timing component selectively exposes each cell to an analog input signal to effect a change in the exposed cell's state. Upon shielding the cell from exposure, the state change is ascertained by a cell measurement component to determine a digital value representative of the input signal amplitude at exposure.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Inventor: Charles Cullen Moore
  • Patent number: 8735796
    Abstract: A solid-state imaging device includes: a column comparison circuit which compares a pixel signal with ramp waves and detects a timing at which the pixel signal and the ramp waves match; a counter circuit which is disposed for each of the pixel columns and measures the timing in the column comparison circuit by being supplied with a clock signal; and M first inverters which are equidistantly connected in series, wherein the counter circuit belongs to one of M groups corresponding to each of the M first inverters disposed in the upper clock stage, the odd-numbered group has second inverters disposed between the output terminal of the first inverter corresponding to the group and the counter circuit of the group, and the even-numbered group has buffers disposed between the output terminal of the first inverter corresponding to the group and the counter circuit of the group.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: May 27, 2014
    Assignee: Panasonic Corporation
    Inventors: Yusuke Shimizu, Kenichi Shimomura
  • Patent number: 8723998
    Abstract: A solid-state image pickup device includes plural pixels, a voltage generator that generates a reference voltage, plural comparators that are aligned in one direction, and compare respective voltages output from the pixels with the reference voltage, a counter that counts in tandem with a change in the reference voltage generated by the voltage generator, plural buffer circuits that are connected in series with the counter, and each sequentially receives an output of the counter; plural latch circuits that take in a value input to an input terminal thereof according to respective trigger signals output from the comparators, a common signal line that is commonly connected to respective inputs of the latch circuits, and plural signal lines that are connected to respective outputs of the buffer circuits, and allow the output of the counter to propagate therethrough.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: May 13, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Masanao Maruta, Mitsuo Magane
  • Publication number: 20140124651
    Abstract: A comparator compares a pixel signal from a pixel with a reference signal an offset level of which is changed in a stepwise manner and performs auto zero to set the pixel signal at the offset level of the reference signal in accordance with one of a plurality of auto zero signals having different timings for instructing the auto zero.
    Type: Application
    Filed: September 26, 2013
    Publication date: May 8, 2014
    Applicant: SONY CORPORATION
    Inventor: Tatsunori Nakahara
  • Patent number: 8717218
    Abstract: A regular expression pattern matching circuit based on a pipeline architecture is proposed, which is designed for integration to a data processing system, such as a computer platform, a firewall, or a network intrusion detention system (NIDS), for checking whether an input code sequence (such as a network data packet) is matched to specific patterns predefined by regular expressions. The proposed circuit architecture includes an incremental improvement on an old combination of a comparator circuit module and an NDFA (non-deterministic finite-state automata) circuit module, where the incremental improvement comprises a data signal delay circuit module installed to the comparator circuit module and an enable signal delay circuit module installed to the NDFA circuit module to thereby constitute a multi-sage pipeline architecture that allows a faster processing speed than the prior art.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: May 6, 2014
    Assignee: National Taiwan University
    Inventors: Ching-Liang Jhang, Sheng-De Wang
  • Publication number: 20140098271
    Abstract: An AD conversion circuit may include: a reference signal generation unit generating a reference signal increasing or decreasing with passage of time; a comparison unit including a first comparison circuit and a second comparison circuit comparing an analog signal to be subjected to an AD conversion with the reference signal; a clock generation unit including a delay circuit in which a plurality of delay units are connected to one another, and outputting a first lower phase signal and a second lower phase signal based on clock signals output from each of the plurality of delay units; a latch unit including a first latch circuit latching a logical state of the first lower phase signal and a second latch circuit latching a logical state of the second lower phase signal; and a counting unit performing counting based on the second lower phase signal output from the clock generation unit.
    Type: Application
    Filed: September 26, 2013
    Publication date: April 10, 2014
    Applicant: OLYMPUS CORPORATION
    Inventor: Yoshio Hagihara
  • Patent number: 8681032
    Abstract: There is a need to provide an AD converter capable of reducing occurrence of a noise. An AD converter includes an operational amplifier and a clip circuit. The operational amplifier receives ramp voltage and voltage for an analog signal and allows output terminal voltage to transition from an H level to an L level when a change in the ramp voltage reaches the voltage for the analog signal. The clip circuit fixes an output terminal of the operational amplifier to clipping voltage after output voltage for the operational amplifier reaches threshold voltage for a latch circuit. Therefore, the AD converter can limit a range of output voltage, as a source of noise, for the operational amplifier and eliminate an unnecessary change in the output voltage after the threshold voltage for the latch circuit is reached.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: March 25, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Osamu Nishikido, Yasutoshi Aibara, Hirokazu Shimizu, Satoshi Tatsukawa, Takayoshi Shigekura
  • Publication number: 20140078362
    Abstract: An apparatus for acquiring an i-bit digital code by a first stage AD conversion and a j-bit digital code by a second stage AD conversion includes a comparing unit which compares a reference signal and an analog signal in the first stage AD conversion; and an amplifying unit for outputting an amplified residual signal acquired by amplifying a difference between the analog signal and an analog signal corresponding to the i-bit digital code. The comparing unit compares the amplified residual signal and the reference signal in the second stage AD conversion.
    Type: Application
    Filed: November 18, 2013
    Publication date: March 20, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Daisuke Yoshida
  • Publication number: 20140077065
    Abstract: An AD conversion circuit and a solid-state imaging apparatus reduce the occurrence of errors in encoding a lower phase signal while securing a degree of freedom of selection of a count clock. A detection circuit performs an operation of detecting logic states of m (m is a natural number of 2 or more) lower phase signals in a signal group that a plurality of lower phase signals latched by the latch unit is arranged, while selecting the m lower phase signals in a predetermined order so that the order thereof becomes the same as the order of the signal group and outputs a state detection signal at the time of detecting that the logic states of the m lower phase signals are in a predetermined logic state in the detection operation. The predetermined order is defined depending on a predetermined signal and an encoding method.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 20, 2014
    Applicant: OLYMPUS CORPORATION
    Inventor: Yoshio Hagihara
  • Patent number: 8648740
    Abstract: The invention provides a testing apparatus. In one embodiment, the testing apparatus receives a plurality of bit signals output by an analog-to-digital converter, and comprises a plurality of frequency counters and a comparison module. The frequency counters respectively calculate a plurality of transition frequencies of the values of the bit signals. The comparison module respectively compares the transition frequencies with a plurality of ideal transition frequencies to obtain a plurality of error frequencies. The performance analysis module estimates a performance value of the analog-to-digital converter according to the error frequencies.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: February 11, 2014
    Assignee: Silicon Motion, Inc.
    Inventor: Hung-Sheng Chang
  • Publication number: 20140036122
    Abstract: An AD conversion circuit may include: a reference signal generation unit; a comparison unit; a clock generation unit; a latch unit; a counting unit; and an encoding unit including a detection circuit and an encoding circuit, the detection circuit performing a first detection operation of detecting logic states of n lower phase signals in a signal group that a plurality of lower phase signals latched in the latch unit are arranged in the same order as those of the signal group when the plurality of lower phase signals output from the clock generation unit are arranged to be the signal group the detection circuit outputting a state detection signal when the logic state of the n lower phase signals is detected to be a predetermined logic state in the first detection operation, the encoding circuit performing encoding based on the state detection signal output from the detection circuit.
    Type: Application
    Filed: July 29, 2013
    Publication date: February 6, 2014
    Applicant: OLYMPUS CORPORATION
    Inventor: Yoshio Hagihara
  • Patent number: 8643528
    Abstract: An analog-to-digital converter (ADC) comprises a plurality of time-interleaved integrating ADCs having feedback from an integrated output signal. In variations, the time-interleaved integrating ADCs have feedback compensation from at least one measure of quantization error. The time-interleaved integrating ADCs may also share a single comparator and may also share a single current source.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: February 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Yue Hu, Ajay Kumar