Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.

Abstract: A sigma-delta technique is used to generate a digital representation of the incoming analog signal amplitude. The integration stage of the converter holds an analog error term relative to the ratio of an incoming analog input signal to a reference voltage. The incoming analog signal is disconnected at the end of the conversion. The error term is monitored through a comparator as charge packets are applied to the input of the integration stage. The number of charge packets needed to have the error term cross zero provides information which can be used to extend the resolution of the analog to digital converter.

Abstract: An integrating D-A/A-D converter includes a reference value generation circuit for generating at least one reference value relating to voltage or current, a control circuit for carrying out switching between a digital or analog input and the reference value every predetermined time to connect a switched one to thereby control an integral time, and an integration circuit for respectively integrating an analog value corresponding to the digital or analog input and the reference value switched in sequence every predetermined time and delivered through the control circuit to output an integral value for providing a digital or analog output.

Abstract: A multi-mode analog to digital converter is described for converting an analog input into a digital value according to a linear or a companding transfer function. The converter comprises a comparator, a successive approximation register and a charge redistribution device. The comparator compares the input voltage and a generated voltage. The successive approximation register generates a provisional binary word responsive to the output of the comparator. The charge redistribution device generates the generated voltage according to the provisional binary word and to a selected transfer function. The transfer function may be selected from the group consisting of linear and companding.

Abstract: In a circuit arrangement for deriving a binary signal from an alternating voltage (U), in which the alternating voltage can be delivered via a capacitor to the input of a threshold value circuit and a reference voltage obtained by integration serves to adjust the operating point at the input, an up/down counter is provided for deriving the reference voltage, its counting direction being controllable by the binary signal. From the output signal of the up/down counter, a further binary signal is derived, which after integration forms the reference voltage. The circuit is suitable for use in evaluating the data subcarrier component of a Radio Data System (RDS) signal, as defined by European Broadcasting Union (EBU) Technical Standard 3244-E.

Abstract: A microcontroller based analog-to-digital converter is disclosed. The microcontroller is coupled to an output of a comparator. The comparator includes an input for receiving an unknown analog voltage and an input coupled to a capacitor. The capacitor is also coupled to the microcontroller through a resistor. Based upon the output of the comparator, the microcontroller provides a pulsed input signal with a predetermined duty cycle to the capacitor. The duty cycles for "high" pulses and "low" pulses are individually set to match a selected input voltage range. The rate at which pulses are applied to the capacitor is adjusted until the voltage on the capacitor matches the input voltage being measured. The pulsed input signal is monitored to establish a pulse count. Based upon the pulse count, the unknown analog voltage value is converted to a corresponding digital voltage value.

Abstract: Analog electrical signals are converted to digital form by analog to digital sampling in accordance with a variable successive approximation technique that permits extremely wide dynamic range coupled simultaneously with extremely high bandwidth capabilities, low power consumption, and low cost. Each of multiple data (sample) points of the input analog signal are digitally compared to a variable reference generated according to the successive approximation process and changeable modes of that process so as to permit optimum efficiency of conversion at varying rates of acquisition of the input signal.

Abstract: An integrated circuit analog-to-digital converter for use on the focal plane of an infrared detector array. The analog-to-digital converter has a sample and hold circuit, a comparator circuit, and a latch circuit. A single slope conversion technique is used to generate digital signals representative of the amplitude of the input analog signal.

Abstract: A successive comparison type analog-to-digital (AD) converter having a successive comparing circuit which is implemented by two successive comparators, and having a parallel two sequence AD conversion capability while adapting itself to another conversion system at the same time as needed. The successive comparators are not expensive and are, therefore, sucessful in constituting an inexpensive successive comparison type AD converter.

Abstract: An arrangement for integrating an analog voltage signal and for converting it into a corresponding digital signal, whereby during a measuring cycle, the analog signal is fed via a comparator to a counting circuit, which to provide the time-related control of the operation of the counter is connected to a variable clock frequency generator device controlled by the analog signal. The comparator is connected to a "D"-flipflop, which is connected to an up-down counter with a digital-to-analog converter, on whose counting input is provided the Q-output of the variable clock frequency generator, which changes its clock frequency according to the absolute value of the voltage to be integrated.

Abstract: A sliding scale averaging technique is employed for an analog-to-digital converter. An analog signal is summed with a varying number prior to conversion. This causes repeated input voltage signals of the same value to be converted in different bins of the ADC converter thereby minimizing errors due to unequal bin widths. The present invention includes a comparator technique for ensuring that the summed signal does not exceed the full dynamic range of the ADC.

Abstract: A method and apparatus for removing the effects of mismatched components in an A/D converter is described. The present invention dynamically rearranges the capacitors of an A/D converter so that physical mismatch is averaged out. In the preferred embodiment of the present invention, an array of equally-sized capacitors is coupled to a switching network. A successive approximation scheme is implemented in which the input signal is coupled through SAR switches to the capacitor array. Each switch is coupled to 2.sup.N-1 capacitors where N is the switch number. For example, in an 8-bit scheme, there are 3 switches with switch 1 coupled to one capacitor, switch 2 coupled to two capacitors, and switch 3 coupled to four capacitors. In this manner, eight levels of capacitance values can be defined. The present invention adds a scramble control code to control the switching array so that the physical capacitors themselves are coupled to different SAR switches at different times.

Abstract: A waveform encoder/decoder includes an encoder having an input for an audio signal to be encoded, and an output whereby the digitally encoded signal is passed to a transmission link and then to a corresponding decoder. The encoder includes detectors for monitoring the digital output signal for slope overload and idle pattern respectively and setting a corresponding value in a state machine. The value stored in the state machine is used to control a pulse width generator which in turn controls the enable time of a tri-state gate connected in the feedback path from the output back to the input. An R.C. filter is used to reconstruct the digital output from the gate to form an estimate of the audio input signal, and this estimated signal is compared with the actual input signal in a comparator. A D-type flip-flop is used to digitize the output from comparator to generate the signal to be output to the transmission link.

Abstract: This invention relates to a flash-successive approximation analog-to-digital converter combining the low speed, high resolution successive approximation method of conversion with the high speed, low resolution flash method of conversion, which provides the advantages of higher conversion speed with no increased conversion error.

Abstract: Method and apparatus for sampling an analog voltage and providing a digital representation of the sampled voltage by binary switching individual resistive networks in parallel with a reference leg of a comparator circuit and combining binary switching signals with the comparator output signal.

Abstract: In a device for coding analog image signals from an image sensor into binary image signals, there is provided a feed back circuit for averaging the image signal derived from the image sensor. A comparator compares the signal derived from the image sensor and the averaged signal for coding the analog image signal into binary image signal.

Abstract: Analog-to-digital converter is particularly for digital systems requiring a fast and accurate high resolution conversion of an analog input signal into a corresponding digital output code. A comparator compares the input signal against a ramp signal. A plurality of counters is responsive to the comparator for providing the output code. Each counter has a weight and counts subsequently to the counting of the counter having a higher weight. A digital-to-analog converter converts the output code from the counters into a reference signal prior to the counting of each counter. An integrator provides the ramp signal in reference to the reference signal and at a rate corresponding to the weight of the counter currently counting. A switch zeroes the integrator prior to the counting of each counter. An optional flash analog-to-digital converter estimates the input signal and determines an initial count of the counters.

Abstract: An analog-to-digital converter quantizer and bidirectional counter using superconducting quantum interference devices (SQUD's) as the principal elements. A double-junction non-latching SQUID is used as a quantizer to produce unipolar output pulses on two different output lines, indicative of positive and negative increments of change in an analog signal current. The unipolar pulses are then counted in a bidirectional counter that employs double-junction non-latching SQUID's as counter stages and as logic gates for the propagation of carry and borrow signals from stage to stage.

Abstract: An analog-to-digital converter macrocell architecture is provided with digital logic for accumulating code-density data for dynamic characterization of the converter. Each macrocell includes an A/D converter (10), a comparator (12), a bin counter (14), a clock counter (16), and a histogram counter (18). the code output of the A/D converter (10) is compared in the comparator (12) with the output of the bin counter (14) and each match increments the histogram counter (18). The histogram counter (18) accumulates code-density data for A/D converter dynamic characterization, these data being read once for every cycle of the clock counter (16).

Abstract: A circuit samples and stores high frequency transient events that affect low frequency steady state signals. The circuit digitizes the high frequency transient signal and samples the digital signals. The present and previously stored data samples are compared, and if the difference exceeds a threshold, the present sample is stored in memory, if the memory is not full, and simultaneously the internal counter is reset. If a number of successive samples do not exceed the threshold and are not stored within a defined interval, the last sample of the interval is stored and an interval counter is reset to zero. A logic circuit controls the timing and operation of the counter and storage of the sampled data.