Abstract: A signal detection circuit detects, as a detection target signal, a signal of a main terminal of a switching element by comparing the detection target signal with a reference signal. The signal detection circuit includes: a signal generation unit generating the reference signal; a first capacitor having a first terminal connected with the main terminal of the switching element; a second capacitor having a first terminal connected with an output terminal of the signal generation unit; and a detection circuit receiving, as input signals, a signal output from a second terminal of the first capacitor and a signal output from a second terminal of the second capacitor, and the detection circuit detecting the detection target signal based on the input signals.

Abstract: Disclosed are a power-aware method, a power-aware system and a converter. The power-aware method includes: receiving an input signal, wherein the input signal is a capacitive type, a resistive type, a voltage type or a current type, coarsely quantizing the input signal and outputting a numerical control code, the numerical control code indicating size information of the input signals, and turning on a corresponding number of power-consuming modules based on the numerical control code. By the power-aware method, the power-aware technical effect of a circuit may be provided and turned-on power-consuming modules always have the most suitable number regardless of the size of the input signals, which may ensure normal operation, and will not waste power consumption due to too many power-consuming modules and energy efficiency is improved as a whole.

Abstract: A multi-instance time-interleaving (TI) system and method of operation therefor. The system includes a plurality of TI devices, each with a plurality of clock generation units (CGUs) coupled to an interleaver network. Within each TI device, the plurality of CGUs provides a plurality of clock signals needed by the interleaver network. A phase detector device is coupled to the plurality of TI devices and configured to determine any phase differences between the clock signals of a designated reference TI device and the corresponding clock signals of each other TI device. To determine the phase differences, the phase detector can use a logic comparator configuration, a time-to-digital converter (TDC) configuration, or an auto-correlation configuration. The phases of the clock signals of each other TI device can be aligned to the reference TI device using internal phase control, retimers, delay cells, finite state machines, or the like.

Abstract: A semiconductor device of an embodiment includes a main circuit configured to perform a predetermined operation to an input signal to output an output signal, an inverse operation circuit configured to receive the output signal of the main circuit as an input, and perform an inverse operation of the predetermined operation by using the output signal to output an inverse operation result signal, and a comparison circuit configured to compare the input signal and the inverse operation result signal, and output a predetermined signal when the input signal and the inverse operation result signal do not coincide with each other.

Abstract: A multi-instance time-interleaving (TI) system and method of operation therefor. The system includes a plurality of TI devices, each with a plurality of clock generation units (CGUs) coupled to an interleaver network. Within each TI device, the plurality of CGUs provides a plurality of clock signals needed by the interleaver network. A phase detector device is coupled to the plurality of TI devices and configured to determine any phase differences between the clock signals of a designated reference TI device and the corresponding clock signals of each other TI device. To determine the phase differences, the phase detector can use a logic comparator configuration, a time-to-digital converter (TDC) configuration, or an auto-correlation configuration. The phases of the clock signals of each other TI device can be aligned to the reference TI device using internal phase control, retimers, delay cells, finite state machines, or the like.

Abstract: A system includes an analog-to-digital converter configured to convert an analog signal generated by a digital sensor into a digital signal, and a testing apparatus configured to be enabled after the analog-to-digital converter operates in a testing mode, wherein the testing apparatus comprises a filter configured to receive the digital signal from the analog-to-digital converter, and apply a filtering process to the digital signal, a control circuit configured to terminate the filtering process after an output of the control circuit reaches a predetermined reference value, and a result register configured to receive a result generated by the filter after the control circuit terminates the filtering process.

Abstract: Provided is an AD converter including a first AD converting unit in which pixel columns of a pixel array are divided into at least two groups, and that compares a first ramp signal and a first pixel signal output from a first group of the pixel columns and performs AD conversion on the first pixel signal; and a second AD converting unit that compares a second ramp signal and a second pixel signal output from a second group of the pixel columns and performs AD conversion on the second pixel signal, in which the first ramp signal is a signal of which a level is decreased with a constant slope over time in a D-phase period for detecting a signal level of a pixel signal, and the second ramp signal is a signal of which a level is increased with a constant slope over time in the D-phase period.

Abstract: In an architecture for processing data comprising a control unit and converters CNj to be synchronized to an active front of a common reference clock CLK, the synchronizing method makes provision for the converters to be arranged in at least one series chain, and for a procedure for synchronizing the converters by propagating a synchronizing signal SYNC-m emitted by the control unit, said signal being retransmitted as output OUT by each converter, after resynchronization to a clock active front, to a synchronization input IN of a following converter in the chain. Each converter comprises a synchronization configuration register REG containing at least one polarity parameter Sel-edgej that sets the polarity of the reference-clock front for reliable detection of a synchronizing signal received via the input of the converter.

Abstract: An analog/digital conversion device that performs analog/digital conversion on an analog signal having different levels using different analog/digital conversion circuits, and a control method therefor are provided. In a case where an analog signal is greater than a threshold value, an output terminal of a first changeover switch is turned on. The analog signal is converted into digital data in a single slope type analog/digital conversion circuit. In a case where the analog signal is smaller than the threshold value, an output terminal of the first changeover switch is turned on. The analog signal is converted into digital data in a hybrid type analog/digital conversion circuit of which precision of conversion of the analog signal greater than the threshold value into digital data is lower than the precision of a single slope type analog/digital conversion circuit.

Abstract: Image sensors using multiple-ramp single slope analog to digital converters (ADCs) and method of their operation are disclosed. The images sensors use additional column ADCs to detect offset errors in the fine ramp signals and feedback in the analog domain to correct the errors. Averaging errors over multiple analog-to-digital conversion cycles allows for improved error correction.

Abstract: A ramp voltage generator may include: a correction block suitable for generating a slope correction signal for first and second periods based on a period signal for distinguishing the periods; a common bias voltage generation block suitable for generating a common bias voltage based on the slope correction signal and a source bias voltage; and a first ramp voltage generation block suitable for generating a first ramp voltage having a predetermined slope during the first period based on the common bias voltage and a first ramp group control signal; and a second ramp voltage generation block suitable for generating ramp voltages having the predetermined slope during the second period based on the common bias voltage and a second ramp group control signal.

Abstract: The present disclosure provides for split-path data acquisition chains and associated signal processing methods. An exemplary integrated circuit for providing a split-path data acquisition signal chain includes an input terminal for receiving an analog signal; an output terminal for outputting a digital signal; and at least two frequency circuit paths coupled with the input terminal and the output terminal, wherein the at least two frequency circuit paths are configured to process different frequency components of the analog signal and recombine the processed, different frequency components, thereby providing the digital signal.

Abstract: In this solid-state imaging device, an output signal of any one of a plurality of delay units that output signals of logic states in accordance with a level of a pixel signal is input to an input terminal of a latch circuit that latches a logic state of the output signal. A NAND circuit and an INV circuit stop until a control signal output timing at which a control signal in accordance with the level of the pixel signal is output, and operate after the control signal output timing. A switch circuit outputs the output signal of the one of the plurality of delay units through a signal line from an output terminal until the control signal output timing, and switches a connection at a latch timing after a predetermined time elapses from the control signal output timing such that the NAND circuit and the INV circuit latch the logic state of the output signal of the one of the plurality of delay units.

Abstract: A charge canceling multiplying digital-to-analog converter (MDAC) is provided with a reference block having inputs to accept reference voltages each sample clock cycle. The MDAC includes a sampling block having inputs to accept differential analog input voltage signals each sample clock cycle. A differential amplifier has a negative input and positive input connected to the reference block and sampling block to receive differential amplifier input signals, and a positive output and a negative output to supply differential output voltage signals each amplify clock cycle. The sampling section includes a first pair of feedback capacitors connected between the differential amplifier negative input and positive output, and a second pair of feedback capacitors connected between the differential amplifier positive input and negative output each amplify clock cycle. A capacitor from the first pair of parallel feedback capacitors is swapped with a capacitor from the second pair prior to each sample clock cycle.

Abstract: To decrease the burden of digital processing, provided is an AD conversion apparatus comprising a pattern generating section that, for each target bit specified one bit at a time moving downward in the output data, generates a pattern signal having a pulse width or number of pulses corresponding to a weighting of the target bit; an integrating section that integrates the pattern signals according to a judgment value for judging a value of the target bit each time a pattern signal is generated, and outputs a reference signal obtained by accumulating the integrated value of each pattern signal; a comparing section that, each time generation of a pattern signal is finished, compares the input signal to the reference signal; and an output section that outputs the output data to have values corresponding to the comparison results obtained after each generation of a pattern signal corresponding to a bit is finished.

Abstract: Aspects of the disclosure provide an analog-to-digital converter (ADC). The ADC includes a comparator module and a digital-to-analog converter (DAC). The comparator module is configured to compare a first voltage sampled from an analog signal and a second voltage output from the digital-to-analog converter (DAC), and output a pulse to indicate a result of the comparison. The DAC is configured to enable a switching unit corresponding to a digital bit to switch a state based on the pulse, and settle the second voltage.

Abstract: One or more techniques and/or systems described herein implement, among other things, a parabolic curve for a ramp signal in a data acquisition component, where the curve can be effectively calibrated and used to provide a settling period to mitigate noise. That is, a ramp generator can generate a ramp signal that has a parabolic voltage curve with two substantially mirroring halves. A comparator can compare a first portion of the parabolic voltage curve with a voltage signal indicative of a number of photons detected by a detection array. A second portion of the parabolic voltage curve is used as a temporal delay so that circuitry, such as the ramp generator, can settle.

Abstract: An analog-digital conversion circuit includes a comparator that receives an analog input signal. A controller generates an N1-bit first signal and an N2B-bit second signal in accordance with an output signal from the comparator. A first digital-analog converter generates a first reference signal from the first signal. A second digital-analog converter generates a second reference signal from the second signal. A correction circuit corrects the first and second signals to generate a digital output signal. The N2B-bit second signal is acquired by adding a Kbit correction signal to an N2A-bit signal. The controller sequentially sets bit values of the first signal and bit values of the second signal in accordance with the output signal of the comparator. The correction circuit generates the (N1+N2A)-bit digital output signal based on a sum of a value acquired by multiplying the N1-bit first signal by 2^N2A and a value of the N2B-bit second signal.

Abstract: In a time-to-digital conversion stage, a time-to-digital conversion circuit outputs an n-bit digital signal, which represents an integer value ranging from ?(2n-1?1) to +(2n-1?1), based on a phase difference between a first and a second signals input thereto; a time difference amplifier circuit amplifies the phase difference between the first and the second signals 2n-1 times, and outputs two signals having an amplified phase difference therebetween; a delay adjustment circuit adds a phase difference dependent on the digital signal to the two signals output from the time difference amplifier circuit, and outputs another two signals; an output detection circuit detects that the delay adjustment circuit has output the another two signals, and outputs a detection signal; and a storage circuit latches the digital signal in synchronism with the detection signal. Multi-stage coupling of the time-to-digital conversion stages forms a pipeline time-to-digital converter.

Abstract: An A/D converter suitable for use in a system in which the signal power of noise increases with the signal power of the signal, such as an imaging system, utilizes a variable quantization system for converting analog signals into digital signals. The variable quantization is controlled so that low signal levels the quantization is similar or identical to conventional A/D converters, while the quantization level is increased at higher signal levels. Thus, higher resolution is provided at low signal levels while lower resolution is produced at high signal levels.

Abstract: Methods for reading a data location coupled to an electrical conductor. A counter receives a signal from an analog-to-digital converter coupled to the electrical conductor. The counter produces two or more counts, and in some embodiments, the counts are based in part on a variable reference voltage. An interfuser may be coupled to an output of the counter. The interfuser receives the two or more counts from the counter and reads data conveyed by the data location based on the two or more counts.

Abstract: A regular expression pattern matching circuit based on a pipeline architecture is proposed, which is designed for integration to a data processing system, such as a computer platform, a firewall, or a network intrusion detention system (NIDS), for checking whether an input code sequence (such as a network data packet) is matched to specific patterns predefined by regular expressions. The proposed circuit architecture includes an incremental improvement on an old combination of a comparator circuit module and an NDFA (non-deterministic finite-state automata) circuit module, where the incremental improvement comprises a data signal delay circuit module installed to the comparator circuit module and an enable signal delay circuit module installed to the NDFA circuit module to thereby constitute a multi-sage pipeline architecture that allows a faster processing speed than the prior art.

Abstract: The present invention provides an analog-to-digital converter, which comprises an integration circuit, a threshold signal generating circuit, a main comparison circuit, a sub comparison circuit, a counter, and a decoder. The integration circuit integrates an input signal and produces an integration signal. The threshold signal generating circuit generates a main threshold signal and a plurality of sub threshold signals. The main comparison circuit produces a plurality of main comparison signals according the integration signal and the main threshold signal. The sub comparison circuit produces a plurality of sub comparison signals according to the integration signal and the plurality of sub threshold signals. The counter counts the plurality of main comparison signals and produces a first counting signal. The decoder decodes the plurality of sub comparison signals and produces a second count signal. The first count signal and the second count signal are used for producing a digital signal.

Abstract: An A/D converter 101 comprises a first cyclic A/D converter circuit 103 and an A/D converter circuit 105. The A/D converter 101 includes a record circuit 107 for storing conversion results from the A/D converter circuits 103, 105. The record circuit 107 includes an upper-bit record circuit 107a and a lower-bit circuit 107b. The cyclic A/D converter circuit 103 receives an analog value SA and generates a first digital value SD1 indicating the analog value SA and a residue value RD. The A/D converter circuit 105 receives the residue value RD and generates a second digital value SD2 having lower M bits indicating the residue value RD. The conversion accuracy in the A/D converter circuit 105 can be lowered to ½L that in the A/D converter circuit 103.

Abstract: Disclosed is an analog-digital converter which includes a pre-amplifier configured to output a comparison result between a sampled analog input signal and a reference signal and to control a power supply operation in response to a power control signal; a digital signal processor configured to generate a digital signal based on the comparison result; a power controller configured to generate an amplifier operation clock signal for controlling the pre-amplifier; and a counter configured to count the number of falling edges of the amplifier operation clock signal and to detect a power interruption point of time of the pre-amplifier according to the counted falling edge number. The power controller generates the power control signal for interrupting a power to be supplied to the pre-amplifier when the power interruption point of time of the pre-amplifier is detected.

Abstract: A system for signal processing comprising a cyclic analog to digital converter structure having a first stage and a second stage, wherein the first stage is configured to receive an input signal to perform 1.5 bits/stage ADC and to generate a first stage output signal, and the second stage is configured to receive the first stage output signal and to perform fine offset tuning using a final conversion phase. The second stage further configured to perform 1.5 bits/stage ADC and to generate a second stage output that is fed back to the first stage to iteratively generate a next 1.5 bits, until (N?3) most significant bits of N bits of data are generated. A third stage configured to generate a three least significant bits of the N bits of data using a flash ADC sampling circuit that samples a residue signal at the output of the first stage.

Abstract: Examples are provided for converting an analog signal to a digital signal by processing more than one bit per cycle in a number of successive approximation cycles. A system may include capacitive sub-DAC circuits and comparators. Switches may isolate the capacitive sub-DAC circuits during one or more first cycles, and merge the sub-DAC circuits during one or more last cycles. A successive approximation register (SAR) may generate digital output signals or DAC digital signals. In another example, a system may include a DAC circuit. An input capacitor may be pre-charged to at least one of an analog input signal and a DAC analog signal. A programmable gain amplifier may amplify an error signal. A multi-bit ADC may convert the amplified error signal to a multi-bit digital signal. An SAR may use the multi-bit digital signal to generate a DAC digital signal or a digital output signal.

Abstract: A current sensing circuit includes a current sensing unit, a feedback control unit and a digital output unit. The current sensing unit senses a current and produces a pulse signal according to at least one reference signal and at least one feedback signal. The current sensing unit includes a first capacitor set and a second capacitor set. The current sensing unit selects at least one capacitor in the first capacitor set and at least one capacitor in the second capacitor set according to the current value so as to adjust the precision of the current sensing circuit. The feedback control unit is coupled to the current sensing unit and produces the feedback signals according to a clock signal and the pulse signal. The digital output unit is coupled to the current sensing unit and outputs a digital signal according to the pulse signal.

Abstract: Examples of systems and methods are provided for converting an analog input signal to a digital output signal. A system may include a current mode (CM) digital-to-analog converter (DAC) circuit to provide a DAC current. A comparator circuit may be configured to generate a comparator signal in response to an error signal determined based on the DAC current and the analog input signal. A successive approximation register circuit may be configured to generate at least one of a DAC-code signal or the digital output signal, in response to the comparator signal. The DAC-code signal may be used by the CM DAC circuit to control the DAC current.

Abstract: A main digital-to-analog converter (DAC) receives at least one input and generates an adjusted input. A SAR unit generates a code for controlling the main DAC based on a comparison output of a comparing unit that receives the adjusted input. A reference generator, under control of the generated code, generates at least one reference voltage, which is then forwarded to the comparing unit in each corresponding cycle for defining a search range of each cycle, wherein an absolute value of the reference voltage of a latter cycle is less than the reference voltage of a former cycle such that the search range of the latter cycle is smaller than the search range of the former cycle, and search ranges of all the cycles are centered at a base voltage.

Abstract: A comparator includes a first amplifier, a second amplifier, and a level holding part. The first amplifier includes differential-pair transistors and outputs a signal of a level corresponding to a comparison result from a first output node. The differential-pair transistors compare a reference voltage with a potential of an input signal. The second amplifier gain up the signal output from the first output node of the first amplifier and outputs the signal from a second output node. The level holding part holds a level of the second output node at a predetermined level. The second amplifier includes a transistor for amplification and a transistor for a current source. The level holding part holds the level of the second output node of the second amplifier such that the transistor for the current source does not fall into a level at which a saturated operation condition is not satisfied.

Abstract: An AD converter includes: AD conversion stages configured to generate digital data having a value corresponding to a relationship between two analog signals being input and amplifying two analog residual signals with a first amplifier and a second amplifier with gain to be controlled to output the signals; and a gain control part configured to control gain of the first amplifier and the second amplifier on the basis of a monitoring result of the output signals of the first amplifier and the second amplifier. The first amplifier and the second amplifier are formed of open-loop amplifiers, and the gain control part takes out amplitude information of the output signals of the first amplifier and the second amplifier in at least one of the AD conversion stages and performs gain control so that amplitude of the analog signals being output from the stage converges on setting amplitude being set.

Abstract: An analog-to-digital converter including a comparator configured to compare a pixel signal received at a first input terminal of the comparator with a ramp signal received at a second input terminal of the comparator and generate a comparison signal as a result of the comparison; and a ramp signal supply circuit configured to provide the ramp signal to the comparator, wherein the ramp signal supply circuit generates a first signal as part of the ramp signal in response to the comparison signal and a first clock signal being received at the ramp signal supply circuit, wherein a slope of the first signal sequentially changes until the comparison signal makes a transition from one logic level to another and, after the transition, the ramp signal supply circuit generates a second signal as part of the ramp signal, wherein a slope of the second signal sequentially changes, wherein the slope of the second signal is opposite the slope of the first signal.

Abstract: A comparator is provided. In one embodiment, a method of operating a comparator comprises providing a bias current (920); comparing an input signal and a reference signal to determine a difference signal and an inverted difference signal (930); latching the difference signal and the inverted difference signal to generate a first and second latched signals (950); generating a control signal using at least the first and second latched signals (970); and controlling the bias current in response to the control signal (980), wherein the comparing the input signal and the reference signal (930) is activated and deactivated in response to the controlling the bias current (980).

Abstract: An analog-to-digital converter including a comparator, a control module, a voltage adjusting module, and an evaluating module is provided. The comparator compares an analog input voltage with a feedback voltage and generates a comparison result. Based on the comparison result, the control module generates a control signal. The voltage adjusting module increases or decreases the feedback voltage toward the analog input voltage according to the control signal. The voltage increase amount and decrease amount provided by the voltage adjusting module are corresponding to a first digital value and a second digital value, respectively. The evaluating module generates the first digital value and the second digital value based on the control signal. According to the first digital value and the second digital value, a digital signal corresponding to the analog input voltage is generated.

Abstract: A comparator is provided. In one embodiment, a method of operating a comparator comprises providing a bias current (920); comparing an input signal and a reference signal to determine a difference signal and an inverted difference signal (930); latching the difference signal and the inverted difference signal to generate a first and second latched signals (950); generating a control signal using at least the first and second latched signals (970); and controlling the bias current in response to the control signal (980), wherein the comparing the input signal and the reference signal (930) is activated and deactivated in response to the controlling the bias current (980).

Abstract: A tracking analog-to-digital converter “ADC” with a self-controlled variable clock comprises: a digital register; a digital-to-analog converter “DAC” coupled to said digital register providing an analog feedback signal; a comparator coupled to an analog input signal and said analog feedback signal and providing a comparison signal based on a comparison between said analog input signal and said analog feedback signal, said comparison signal being coupled to the digital register; a means for determining comparator readiness to determine if said comparator is ready, indicating that said comparison signal can be reliably read, said means for determining comparator readiness further comprising a determination of a comparison ready indicator; a means for clocking to generate a clock signal to drive said digital register in response to said means for determining comparator readiness determining that said comparator is ready; and said digital register being configured to count in response to said clock signal based o

Abstract: A system and method are provided for adaptively controlling timing in SAR ADC of a sampled analog signal within a conversion period. A state machine maintains a set of SAR states including a sampling state and a plurality of bit conversion states. A reference generator generates a quantization level reference for each of the bit conversion states within a parametric settling time thereof. A comparator compares the sampled analog signal with the quantization level reference over a parametric propagation time for determining a hit value for each hit conversion state. A clock generator adaptively defines signals for clocking the state machine and comparator for each SAR state, thereby adaptively delaying bit determination in each bit conversion state by an integration period not less than the settling time, while adaptively delaying quantization level reference generation for a next bit conversion state by a regeneration period not less than the propagation time.

Abstract: Provided are an analog digital converting device and a reference voltage controlling method thereof. The analog digital converting device includes: a first reference voltage generating circuit generating a first reference voltage; a second reference voltage generating circuit generating a second reference voltage; a first sub analog digital converter receiving an analog input signal and converting the analog input signal into a first digital signal by using the first reference voltage; an amplifier converting the first digital signal into a voltage corresponding to the first digital signal by using the first reference voltage and amplifying a difference between a voltage level of the analog input signal and a voltage level corresponding to the first digital signal to output a residual signal; and a second sub analog digital converter receiving the residual signal and converting the residual signal into a second digital signal by using the second reference voltage.

Abstract: A current sensing circuit including a current sensing unit, a feedback control unit, and a digital output unit is provided. The current sensing unit senses a current and generates a pulse signal according to at least one reference signal and at least one feedback signal. The feedback control unit is coupled to the current sensing unit and generates the at least one feedback signal according to a clock signal and the pulse signal. The digital output unit is coupled to the current sensing unit and outputs a digital signal according to the pulse signal. The digital output unit counts an amount of pulses of the pulse signal in a predetermined time period to output the digital signal, wherein the amount of pulses is positively correlated with a value of the current.

Abstract: A solid-state imaging device includes: a plurality of pixel circuits each including a photoelectric conversion element; reading signal lines connected to the pixel circuits; a reference signal output circuit outputting a reference signal whose voltage level varies; a reference signal line connected to the reference signal output circuit; and comparators each having a first input terminal and a second input terminal and each inverting its output depending on a voltage relation of the first input terminal and the second input terminal, wherein the first input terminals of some of the comparators are connected to the reading signal lines and the second input terminals thereof are connected to the reference signal line, and wherein the first input terminals of the other of the comparators are connected to the reference signal line and the second input terminals thereof are connected to the reading signal lines.

Abstract: In one embodiment, a method receives an analog input voltage. The method also receives a threshold from a plurality of thresholds. A comparator performs a comparison of the input voltage with the received threshold and outputs an output value based on the comparison of the analog input voltage with the received threshold. The output value is for converting the analog input voltage to a digital value. The method determines if the threshold should be adjusted based on the comparison and adjusts the threshold when it is determined the threshold should be adjusted.

Abstract: An information processing apparatus, includes: a plurality of processor means respectively including storage means for storing analog information and comparison means for comparing analog information stored in the storage means with an inputted reference analog value; input means for inputting the reference analog value to the plurality of processor means while changing the reference analog value in synchronization with a clock signal; and counter means for updating a count value in synchronization with the clock signal and outputting the count value when the analog information and the reference analog value become consistent at a corresponding comparison means.

Abstract: Systems, methods, and devices for obtaining data from a data location. The method may include generating a first value by sensing a data location under a first condition and generating a second value by sensing the data location under a second condition. The method may further include combining the first value with the second value to identify data conveyed by the data location.

Abstract: An A/D converter suitable for use in a system in which the signal power of noise increases with the signal power of the signal, such as an imaging system, utilizes a variable quantization system for converting analog signals into digital signals. The variable quantization is controlled so that at low signal levels the quantization is similar or identical to conventional A/D converters, while the quantization level is increased at higher signal levels. Thus, higher resolution is provided at low signal levels while lower resolution is produced at high signal levels.

Abstract: This disclosure relates to analog to digital converter (ADC) component with a comparator function for analog signals.

Abstract: Compression of signal samples output from a parallel, time-interleaved analog to digital converter (TIADC) for a baseband signal, includes calculating first or higher order differences of consecutive signal samples followed by lossless or lossy encoding of the difference samples to produce compressed samples. Compression of a TIADC output signal with a nonzero center frequency, includes calculating sums or differences of pairs of signal samples separated by an appropriate number of sampling intervals followed by lossless or lossy encoding. The sums or differences of the signal samples have lower magnitudes than the original samples, allowing more efficient compression. Lossy compression alternatives produce compressed data with a fixed bit rate or with a fixed quality in the decompressed samples.

Abstract: A microcontroller has an integrating analog-to-digital converter (IADC) with an in-situ autocalibrating functionality. On-chip autocalibrating circuitry supplies a first predetermined analog input voltage to the IADC and obtains a first data value from the IADC. The autocalibrating circuitry supplies a second predetermined analog input voltage to the IADC and obtains a second data value. The first and second data values are used to calibrate the IADC such that if the first input voltage is later supplied to the IADC, then the IADC will output a first predetermined desired digital output value and such that if the second input voltage is later supplied to the IADC, then the IADC will output a second predetermined desired digital output value. The first and second analog input voltages are generated on-chip so the calibration is performed automatically without having to supply external calibrating signals to the microcontroller. Other related methods and circuitry is disclosed.

Abstract: A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit.

Abstract: An analog to digital conversion circuit and method is presented. The analog to digital circuit (100) comprises a first capacitor (103), arranged for being switchably (102) connected on one side to an input voltage (101), at least one successive approximation circuit (104), a comparator (108) arranged for outputting a sign indicative of the difference between the voltage on the first capacitor (103) and a comparison voltage (109), and a control block (110), arranged for converting said comparator's output into steering signals and in a digital output signal. The successive approximation circuit comprises a second capacitive structure (106), switchably connected to a pre-charge circuit (107) arranged for pre-charging the second capacitive structure (106), whereby the second capacitive structure (106) is connected in parallel with the first capacitor (103) via a charge copying circuit (105).