Abstract: There is disclosed an ADC including a comparator which sets, bit-by-bit, a successive approximation binary register. Feedback means for auto-biasing, auto-calibration, and offset compensation within the ADC are provided. The ADC sets itself to a high degree of accuracy automatically by reference to a master voltage reference. A number of identical ADCs are connected in parallel to provide an increased sampling rate. The ADC architecture compensates for component tolerance differences, for common mode noise, and for secondary parasitic effects. The ADC operates with high resolution at high speed (e.g., 10 bits at 50 MHz), and can be implemented in MOS technology with good circuit yield and is compatible with ASICs.

Abstract: In a successive-approximation analog-to-digital conversion application, charge injection offset at the sample input of the comparator resulting from the changing DAC reference voltage, is converted to a fixed, systematic offset. In the comparator differential input stage, the reference or driven input device is turned off during a sample time, prior to beginning the conversion process, so that substantially all of a predetermined bias current flows in the sample side of the comparator. Given this initial condition, the change in input voltage through conversion is a fixed function of the device geometry, bias current and gain, independent of the sample voltage, and therefore may be calibrated out of the system. The comparator input stage includes a differential pair of MOS transistors. A CMOS transmission gate is coupled between the DAC output and the reference comparator input. A switch transistor is coupled between the reference input, i.e. the gate of M2, and Vdd for biasing off M2 during sample time.

Abstract: An analog/digital converter in the present invention compares sequentially with respect to the elapse of time an inputted analog signal with multiple-bit signals corresponding to reference voltages of multiple levels so as to output a digital signal. The analog/digital converter includes a shift register for tracking the termination of the comparisons of each bit signal at every bit with the elapse of time, a selector for sequentially storing in an internal register select shift register bits representing comparison termination signals, and a central processing unit for selecting one of the termination signals stored in the internal register so as to output it to the flag register. The termination signal may be output to the flag register before digital conversion is complete thereby enabling the CPU to prepare to read the final result while digital conversion is still being performed.

Abstract: A cyclic analog-to-digital converter includes two arithmetic circuits and a single comparator. The output of each arithmetic circuit is connected to the input of the other arithmetic circuit. Each arithmetic circuit can modify the analog signal being converted in accordance with output signals from the comparator. Embodiments are disclosed in which the arithmetic circuits include switched capacitors and separate or shared operational amplifiers.

Abstract: An analog-to-digital converter latching circuit functions alternatively in a degenerative mode and a regenerative mode. During degeneration, circuit stray capacitances are substantially discharged for resulting in fast operation. When the circuit switches from degeneration to regeneration, a small signal current is able to start the latch in the proper direction without first having to overcome charge stored in the stray capacitances.

Abstract: In an A-D converter including a reference voltage generator, a D-A converter for outputting analog reference comparison voltage signals in response to digital signals; a comparator for comparing the voltages with an analog input voltage signal to be converted and outputting a reset signal when the voltage is substantially equal to the voltage, and a successive approximation register for successively outputting the digital signals to the D-A converter and an A-D converted signal in response to the reset signal, the D-A converter comprises in particular, at least one decoder block composed of plural array switches for coding any given function. Therefore, the analog input signal can be converted into the corresponding digital output signal in accordance with the coded function, thus providing an A-D converter suitable for use with a fuzzy controller. Further, the reference voltage generator is so configured as to easily change the coded membership function symmetrically or asymmetrically.

Abstract: An apparatus for converting the sum of m digital signals to an analog signal utilizing resistors and switches only. The operating time of the apparatus is the time required to pass the signal through a single switch. This invention can also be utilized in an A/D converter for converting the difference between an analog signal and several digital signals to a digital signal without using extra time to compute the subtraction.

Abstract: A successive comparison type analog-to-digital (AD) converter having a successive comparing circuit which is implemented by two successive comparators, and having a parallel two sequence AD conversion capability while adapting itself to another conversion system at the same time as needed. The successive comparators are not expensive and are, therefore, sucessful in constituting an inexpensive successive comparison type AD converter.

Abstract: An analog/digital converter for converting analog output signals to digital values. The difference between the converted digital value and a reference digital value obtained at the last routine of the program is calculated. In accordance with the difference the closer digital value to the reference value is selected and the closer digital value is set as a proper digital value.

Abstract: An analog-to-digital inverter includes successive approximation control logic for generating ten-bit binary numbers, a digital-to-analog converter (DAC) having a resistor string and a weighted-capacitor array for converting the ten-bit binary output of the control logic to a known analog voltage, and an analog comparator for comparing the output of the DAC to a reference voltage provided via a tap to the mid-point of the DAC resistor string. The unknown analog voltage input to the ADC and the reference voltage are provided to the capacitor array to precharge the array to a voltage equal to the reference voltage minus the unknown analog voltage. The output of the DAC is therefore equal to the known analog voltage plus the reference voltage minus the unknown analog voltage.

Abstract: A sliding scale averaging technique is employed for an analog-to-digital converter. An analog signal is summed with a varying number prior to conversion. This causes repeated input voltage signals of the same value to be converted in different bins of the ADC converter thereby minimizing errors due to unequal bin widths. The present invention includes a comparator technique for ensuring that the summed signal does not exceed the full dynamic range of the ADC.

Abstract: A method and apparatus for removing the effects of mismatched components in an A/D converter is described. The present invention dynamically rearranges the capacitors of an A/D converter so that physical mismatch is averaged out. In the preferred embodiment of the present invention, an array of equally-sized capacitors is coupled to a switching network. A successive approximation scheme is implemented in which the input signal is coupled through SAR switches to the capacitor array. Each switch is coupled to 2.sup.N-1 capacitors where N is the switch number. For example, in an 8-bit scheme, there are 3 switches with switch 1 coupled to one capacitor, switch 2 coupled to two capacitors, and switch 3 coupled to four capacitors. In this manner, eight levels of capacitance values can be defined. The present invention adds a scramble control code to control the switching array so that the physical capacitors themselves are coupled to different SAR switches at different times.

Abstract: A conversion system is disclosed for performing either an analog-to-digital A/D conversion associated with an amplification step or a digital-to-analog D/A conversion associated with an attenuation step. The system includes apparatus (115) for receiving a input digital word to be processed, i.e. converted into analog and then attenuated, and apparatus (165) for receiving a input analog value to be processed, i.e. amplified for scaling purposes and then converted into digital. It also includes a digital-to-analog D/A converter (110), an attenuator (120) for attenuating the analog output of D/A converter (110), and a comparator (150) for comparing the value of the input analog value to be processed and the output of said attenuator (120). The processing of the D/A-attenuation process is performed by both the D/A converter (110) and attenuator (120).

Abstract: A means for correction for DC offset in an analog-to-digital converter which utilizes a hardware implemented iterative digital integration process. During the off time of an analog-to-digital converter thermal noise is digitized by the analog-to-digital converter and a specific number of least significant bits which are sufficient to handle the thermal noise levels are accumulated for a given number of samples. The accumulated sum of thermal noise samples is then converted into an analog signal and scaled by the number of samples taken so as to effectively find the average value from the sample collected. This scaled analog signal is then added to the thermal noise input signal wherein the process is repeated a predetermined number of times. Upon completion of the last iteration, the scaled analog signal which is representative of the DC offset inherent in the particular analog-to-digital converter is added to the true analog signal to be digitized.

Abstract: The same analog signal is inputted to an 8-bit AD converter and to a 4-bit AD converter to obtain an 8-bit digital data and a 4-bit digital data for the same sample value of the analog signal. Values of the 8-bit digital data and 4-bit digital data are compared with each other. The 8-bit digital data is outputted as a digital signal for the sample value of the analog signal when a difference between these values is not greater than one-half the quantity that corresponds to the least significant bit of the 4-bit digital data, and the 4-bit digital data is outputted as a digital signal for the sample value of the analog signal in other cases. There is realized AD conversion which operates apparently at high speeds maintaining high accuracy.

Abstract: A successive approximation type A/D converter of the present invention has a capacitor having a predetermined capacitance value and arranged between an input terminal of a voltage comparator and a fixed potential terminal having a predetermined potential. According to the successive approximation type A/D converter of the present invention, the capacitor arranged between the input terminal of the voltage comparator and the fixed potential terminal having the predetermined potential prevents a potential at the input node of the voltage comparator from being greatly changed to exceed a power source voltage range due the influences of a local D/A converter when the sample mode is switched to the approximation mode. Therefore, the leakage of charges stored in the input side of the voltage comparator can be prevented. Accordingly, even if the amplitude of an analog input voltage is equal to the amplitude of the power source voltage, high-precision A/D conversion can still be performed.

Abstract: An analog-to-digital converter macrocell architecture is provided with digital logic for accumulating code-density data for dynamic characterization of the converter. Each macrocell includes an A/D converter (10), a comparator (12), a bin counter (14), a clock counter (16), and a histogram counter (18). the code output of the A/D converter (10) is compared in the comparator (12) with the output of the bin counter (14) and each match increments the histogram counter (18). The histogram counter (18) accumulates code-density data for A/D converter dynamic characterization, these data being read once for every cycle of the clock counter (16).

Abstract: A semiconductor integrated circuit includes a plurality of comparators for comparing an analog input with reference voltage or voltages, holding means for holding a digital value, and control means for controlling the outputs of the plurality of comparators by a control signal responsive to the digital value to output the multiplication result of the output values of the plurality of comparators and the digital value. Thus, the integrated circuit can construct a circuit having functions of an A/D converter and a multiplier on one chip.

Abstract: A single chip monolithic integrated successive approximation analog-to-digital converter includes a test mode terminal for receiving shift register test mode control signals and successive approximation mode control signals. Digital test data signals are applied to a test data terminal. A trimmable digital-to-analog converter (DAC) is connected to receive digital signals and converts these signals to analog signals of corresponding values. A successive approximation and shift register is coupled to the test mode terminal and the test data terminal. During post-fabrication processing, the successive approximation and shift register operates in a shift register test mode in response to the test mode control signals. Test signals of a known value are serially received and applied in parallel to the DAC. The DAC can then be trimmed to required specifications. The successive approximation and shift register operates in a successive approximation mode in response to successive approximation mode control signals.

Abstract: An analog-to-digital converter system for converting an input analog signal having a wide dynamic range to a digital output has a non-linear function generator for compressing the wide dynamic range input signal to a reduced dynamic range signal, an analog-to-digital converter of limited dynamic range for converting the reduced dynamic range signal to a digitally formatted signal, and a conversion memory for providing a digital value corresponding to the value of the wide range analog input. The digitally formatted signal addresses a word within the conversion memory, the word so addressed containing a digital value corresponding to the magnitude of the analog input signal. Each word of the conversion memory has a sufficient number of bits for expressing the desired dynamic range of the input signal.

Abstract: A clock-controlled analog/digital converter operating according to the weighing method includes a sample-and-hold element with an analog input, a comparator having inputs and a successive approximation register having a data output. The sample-and-hold element, the comparator and the successive approximation register being mutually interconnected in series. The successive approximation register includes memory elements for incrementing a defined logical state for each successive weighing step as well as for writing in and storing in memory the particular result of weighing ascertained by the comparator. A digital/analog converter has an input side connected to the data output and an output side connected to one of the inputs of the comparator. A decoder controls the comparator and the successive approximation register and has an input side connected to the data output.