Abstract: An AD converter includes an analog data storing unit, a first DA converter for converting an input digital data into a first analog reference voltage which varies within a first voltage range in a range of every possible signal voltage of the input analog data, a second DA converter for converting the input digital data into a second analog reference voltage which varies within a second voltage range in the range of every possible signal voltage of the input analog data, a first comparator for comparing the input analog data with the first reference voltage, a second comparator for comparing the input analog data with the second reference voltage and a digital data storing unit for storing a digital data corresponding to a point of time when a change of state occurs in the comparison results of each of the first and second comparators.

Abstract: A comparator with an input stage that selectively powers up an output stage provides an electronic device with a comparator that operates at low power. In an embodiment, an input stage produces a near decision and a true decision, where the near decision is provided to power up an output stage for the comparator to provide an output representative of the true decision.

Abstract: An analog to digital converter (ADC) with interference rejection capability and method thereof are disclosed. The ADC includes a threshold generator, a comparator circuit, a counter and an integrator. By comparing a signal with positive and negative threshold signals from the threshold generator, the comparator circuit converts the signal from analog to digital based on the result of the comparison. The counter counts a percentage of the digital signal and generates a bit signal based on the counted percentage. In response to the bit signal, the integrator supplies a control signal to the threshold generator to regulate the positive and negative threshold signals so as to maintain the counted percentage at a predetermined percentage threshold.

Abstract: A comparator is provided that outputs a comparison result obtained by comparing two signals.

Abstract: A semiconductor integrated circuit includes a differential amplifier circuit receiving first and second input voltages, a latch circuit comparing a voltage received from a first output terminal of the differential amplifier circuit through a first capacitor and a voltage received from the second output terminal of the differential amplifier circuit through a second capacitor and providing a digital signal representing a result of a comparison between the first and second input voltages, and a third capacitor having a first terminal coupled to a second terminal of the first capacitor and a second terminal coupled to a second terminal of the second capacitor.

Abstract: An A/D converter suitable for use in a system in which the signal power of noise increases with the signal power of the signal, such as an imaging system, utilizes a variable quantization system for converting analog signals into digital signals. The variable quantization is controlled so that at low signal levels the quantization is similar or identical to conventional A/D converters, while the quantization level is increased at higher signal levels. Thus, higher resolution is provided at low signal levels while lower resolution is produced at high signal levels.

Abstract: The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.

Abstract: Methods and apparatus to measure a voltage on an integrated circuit are disclosed. An example method to measure a voltage on an integrated circuit provides a reference signal to a first input of an encoder, provides a signal having a first voltage to a second input of the encoder, varies the reference signal from a second voltage to a third voltage, determines a first time value associated with a change in a state of an output of the encoder during the varying of the reference signal, and measures the first voltage based on the first time value.

Abstract: A microcontroller has an integrating analog-to-digital converter (IADC) with an in-situ autocalibrating functionality. On-chip autocalibrating circuitry supplies a first predetermined analog input voltage to the IADC and obtains a first data value from the IADC. The autocalibrating circuitry supplies a second predetermined analog input voltage to the IADC and obtains a second data value. The first and second data values are used to calibrate the IADC such that if the first input voltage is later supplied to the IADC, then the IADC will output a first predetermined desired digital output value and such that if the second input voltage is later supplied to the IADC, then the IADC will output a second predetermined desired digital output value. The first and second analog input voltages are generated on-chip so the calibration is performed automatically without having to supply external calibrating signals to the microcontroller. Other related methods and circuitry is disclosed.

Abstract: Errors in an analog to digital converter that cause generated digital codes to deviate from expected values are corrected. A sample of an analog signal is stored in a storage element. An error signal is then generated, with the error signal representing a deviation of an expected digital code for the strength of a sample of an analog input from a value that would be generated without correction. The error signal is then added to the stored sample. In an embodiment implemented in the context of a SAR ADC, a digital value representing an integral non-linearity error is generated based on a partial digital code (result of a partial conversion of the sample) and an error coefficient. The digital value is converted to analog form by an auxiliary DAC, and added to the stored input sample.

Abstract: A semiconductor integrated circuit includes a differential amplifier circuit receiving first and second input voltages, a latch circuit comparing a voltage received from a first output terminal of the differential amplifier circuit through a first capacitor and a voltage received from the second output terminal of the differential amplifier circuit through a second capacitor and providing a digital signal representing a result of a comparison between the first and second input voltages, and a third capacitor having a first terminal coupled to a second terminal of the first capacitor and a second terminal coupled to a second terminal of the second capacitor.

Abstract: An analog to digital converter (ADC) with interference rejection capability and method thereof are disclosed. The ADC includes a threshold generator, a comparator circuit, a counter and an integrator. By comparing a signal with positive and negative threshold signals from the threshold generator, the comparator circuit converts the signal from analog to digital based on the result of the comparison. The counter counts a percentage of the digital signal and generates a bit signal based on the counted percentage. In response to the bit signal, the integrator supplies a control signal to the threshold generator to regulate the positive and negative threshold signals so as to maintain the counted percentage at a predetermined percentage threshold.

Abstract: A system and method of receiving data is disclosed. The system includes an analog to digital converter, registers to store a plurality of digital samples provided by the analog to digital converter, and a state machine coupled to the registers. The state machine detects jitter or drift in at least one of the digital samples and provides a digital value for the digital sample based on at least one other of the plurality of digital samples. In a particular embodiment, the samples are each comprised of a plurality of data segments, and the state machine applies a virtual frame to the data segments of the digital sample and shifts the virtual frame to include at least one data segment of the other digital sample.

Abstract: Paying attention to the difference between a subsequently inputted analog signal and a reference signal which is an analog signal converted to the digital signal immediately before for instance, changing timing dynamically for converting the analog signal to the digital signal, and converting an analog signal sampled at the timing of changing dynamically to a digital signal.

Abstract: A cardiac rhythm management apparatus may include a monitored energy source, a reference energy source, and a measurement module. The monitored source provides an initial pacing amplitude voltage and a pacing droop voltage, while the reference source provides a substantially fixed reference voltage. The measurement module, coupled to the monitored source and the reference source, provides a measurement related to the lead impedance associated with the rhythm management apparatus that is substantially independent of the reference voltage. Thus, a system may include the apparatus coupled to a lead wire. An article may cause a machine to implement a method which operates to determine a ratio of the actual initial pacing amplitude voltage to the actual pacing droop voltage.

Abstract: A control unit for a transportation device has a processing unit that is supplied with power by a first supply voltage and has a signal converter for converting input analog signals to digital signals. The signal converter has an analog converter stage for generating a modified signal from the analog signal and a digital converter stage for generating a digital signal from the modified signal. The analog converter stage has a signal integration stage connected to a signal amplitude comparator; and the digital converter stage has a scanning stage to whose output the analog-to-digital-converted digital signal is applied. The digital converter stage comprises configurable logic circuits provided on the chip of the processing unit; while the analog converter stage comprises components outside the processing unit. The analog converter stage is supplied with voltage by a second supply voltage different from the first supply voltage.

Abstract: A touch screen display circuit is disclosed which includes means for measuring a voltage at two separate input terminals which represent a location on a touch screen where pressure was applied. The display circuit includes means for defining a time period during which the voltage is measured and means for converting the measured voltage to a digital value. The means for measuring a voltage includes an amplifier and a capacitor which are configured as an integrator. The means for converting comprises a counter that measures an amount of time required for the capacitor to dissipate its charge. A touch screen display system having a touch screen which includes first and second sheets of conductive materials positioned in a spaced apart relationship is disclosed.

Abstract: A state machine is used to remove residual electric charge from a sense line and to sample the voltage of the sense line at multiple pre-determined times to determine the presence of a terminating capacitor and its value. Various values of capacitors identify discrete conditions. These discrete conditions may identify different types of plug-in cards or models of plug-in cards within a group type.

Abstract: A control system and method for simultaneously regulating the operation of a plurality of different types of switching power converters. The system utilizes in regulating the power converters sampled data and nonlinear feedback control loops.

Abstract: A D/A converter including a plurality of potential generating sections. They each receive a 1-bit signal from one of an input terminal and delay circuit, and a clock signal or inverted clock signal from an input section or inverter for inverting the clock signal. When the clock signal or inverted clock signal is at a first signal level, they generate a first reference potential or second reference potential in response to the signal level of the 1-bit signal. When the clock signal or inverted clock signal is at the second level, they generate an intermediate potential between the first and second reference potentials. The potentials generated by the plurality of potential generating sections are combined by a combining section. The D/A converter can improve resistance to jitter, and to simplify the configuration of a post-stage filter circuit.

Abstract: A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in inputs to an Exclusive OR gate. The first and second comparators are separated in the array by a third comparator. The output of the Exclusive OR gate is used to determine if the third comparator is in a metastable condition. If the third comparator is in a metastable condition, the bias current of the latch circuit of the third comparator is increased to increase the rate at which the third comparator transitions to a steady state.

Abstract: A double ramp ADC within an image sensor. The double ramp ADC divides the analog-to-digital conversion process into two steps. During the first step of the conversion, the ADC runs through the potential digital values roughly, using coarse counter steps, and maintains a coarse digital output value. During the second step, the ADC runs through the individual digital values within the range of values associated with the coarse digital value. Thus, the second step runs through the fine digital values associated with the coarse digital value. The coarse and fine digital values are output as the converted digital value of the analog input voltage. The double ramp ADC should reduce the analog-to-digital conversion cycle time by up to 2(n/2−1) times that of the conventional analog-to-digital conversion cycle using ramp ADCs, where n is a number of bits of digital output (i.e., resolution) of the ADCs.

Abstract: A comparator comprises a cross-coupled regenerative latch, a circuit connected to the cross-coupled regenerative latch and a clocking circuit. The cross-coupled regenerative latch regenerates, during a latching mode, a signal which is indicative of a difference between two input signals. The circuit connected to the cross-coupled regenerative latch operates as a voltage follower during an acquisition mode and as a cascode amplifier stage during the latching mode. The clocking circuit switches the comparator from the acquisition mode to the latching mode and vice versa. The comparator eliminates the extraneous loading from the positive feedback when the regeneration takes place, so that a very fast regeneration time constant is obtained.

Abstract: A comparator is used as a microcontroller peripheral and is programmable for either high-speed or low-power operation. High-speed operation requires higher operating current than the operating current required in the low-power mode, but enables much faster response to changes in input signals. When in the low-power mode, the quiescent current of the comparator circuit is minimal but the response is slower to changing input signals. Current control is used on the first input stage, which affects the current consumption of the subsequent stages. The current consumption is adjusted by switching in and out different current sources for the differential input stage of the comparator.

Abstract: There is provided a chopper type voltage comparator for comparing a sampled input voltage with a ramp voltage that is changed with a time, in which a bias voltage is changed according to the ramp voltage, and then the bias voltage comes up to a predetermined voltage value that is able to bring the chopper type voltage comparator into a comparing operation state when the ramp voltage becomes substantially equal to the input voltage. Accordingly, a voltage comparator whose consumption power can be suppressed rather than the prior art and an analog/digital-converter using the same can be provided.

Abstract: There is provided a data storage device concurrently allowing storage of data that can be reproduced in higher quality and storage of data that can be used also in a data transmission path with a lower transfer speed. The data storage device comprises an A/D converter 103 for sampling analog audio signals based on a sampling frequency, a DSP 104 for compressing sample data sequentially output from the A/D converter 103, a storing and reading control unit 107 for storing the compressed data sequentially output from the DSP 104, and a control unit 105 for controlling the DSP 104 and the storing and reading control unit 107 for dividing the sample data sequentially output from the A/D converter 103 into a group under odd number of turns and a group under even number of turns, compressing the groups at each different compression rate and storing them on different storage areas A and B, respectively.

Abstract: A successive approximation A/D converter includes a comparator formed of a plurality of comparators and comparing an analog input voltage with a plurality of voltages output from a digital-to-analog converter so as to output a conversion result including at least 2 bits. A control circuit in the A/D converter performs error correction based on the final result output from the comparator and outputs a final conversion result to a conversion result output terminal.

Abstract: A time domain data converter with output frequency domain conversion. A data conversion circuit is operable to receive a signal in the time domain and provide an output in the frequency domain. It includes a data converter for converting data from an analog format to a digital format in the time domain. It also includes a processor for processing the data in the digital format output from the data converter through a time domain/frequency domain transform to provide data in the digital format in the frequency domain. The output of the frequency domain operation or the time domain operation can be provided for output in response to the generation of a data ready signal.

Abstract: The present invention provides a programmable ADC with bit conversion optimization and method therefor. The programmable ADC includes an amplifier, a programmable clock generator, a comparator, a successive approximation logic, a digital-to-analog converter, and a voltage converter. The amplifier is arranged to sample and hold an input analog signal to be converted into N digital data bits. The programmable clock generator generates a clock signal for each of the N-bits to trigger setting of one of the N-bit digital data bits such that each of the N bits is set during a time optimized for each bit. The comparator is coupled to receive and compare the input analog signal with a successively approximated analog signal to generate a digital output signal. The successive approximation logic is configured to successively set each of the N-bits in response to the digital output signal and the clock signal to generate a successively approximated N-bit digital data.

Abstract: A highly efficient analog-to-digital (A/D) converter circuit that converts an external analog signal sequentially generated from an external analog signal source into an n-bit digital data signal (n is an integer equal to or more than two) includes a digital-to-analog (D/A) converter circuit that converts an n-bit digital data signal into an analog signal and outputting the analog signal from a first output terminal, a comparator that compares a signal level of an external analog signal supplied from an external device with a signal level of the analog signal outputted from the first output terminal, and a digital integrator circuit that digitally integrates a 1-bit digital data signal outputted from the comparator and thereby producing an n-bit digital data signal.

Abstract: A current mode pipelined analogue to digital converter (ADC) has a plurality of serially connected conversion stages. Each conversion stage has an input (40) for receiving a sampled and held current which is connected via a switch (S41) to a first current memory (M42) and via a switch (S40) to a second current memory (M41). The output of the second current memory (M41) is fed via a switch (S44) to one input of a summing junction (46). The output of the first current memory (M42) is fed via a switch (S42) to the input of a comparator (L44) whose output is clocked into a latch (L44) whose Q output is connected to an output (45) as the digital result of the conversion. The Q output of the latch (L44) is also connected to a digital to analogue converter (46) whose analogue output is fed to a second input of the summing junction 46 via a switch (S43) to form the analogue residue signal for application via output (47) to the next conversion stage in the pipeline.

Abstract: An analog-digital converter capable of outputting stable conversion codes even when an analog signal is input in the vicinity of a boundary between adjacent analog-digital conversion regions. The analog-digital converter as described is provided with ignoring regions between the conversion regions. When the signal level of the analog signal is located within one of the ignoring regions, the analog-digital conversion code outputted from the output circuit is maintained in a next period.

Abstract: An analog comparator compares an analog signal to be converted with an analog ramp signal. The output of the comparator enables a digital latch having a binary Gray code counter input. When the analog ramp equals the analog signal, the digital latch captures the state of the Gray code counter. Metastability in the digital latch is resolved by a latch train. The Gray coded output is then decoded by a Gray decoder to a standard binary output. An array of converters are constructed on a monolithic integrated circuit where each converter shares a single analog ramp generator, binary Gray code counter and Gray decoder. A multiplexer selects a particular converter and switches the standard binary output from the selected converter to line drivers to be used off-chip. The two least significant bits of the Gray code are generated with phase shifting circuits.

Abstract: An integrated circuit which includes a successive approximation analog-to-digital converter. The successive approximation analog-to-digital converter employs oppositely coupled comparators and logic circuitry to generate a signal upon a bit determination, with the signal latching the determined bit, resetting the comparators for the subsequent bit determination, and if additional bit(s) are to be determined, commencing the subsequent bit determination. The converter may be configured as a single ended, differential or complimentary circuit.

Abstract: There is disclosed an integrated circuit including a successive approximation analog-to-digital converter. The successive approximation analog-to-digital converter can select which of at least two clock signals of different frequency drive the successive approximation converter for each bit determination. Each bit determination may employ a different clock frequency, or a particular clock frequency could be used for multiple bit determinations. The clock signals may be generated within the analog-to-digital converter, or the clock signal may be provided to the analog-to-digital converter.

Abstract: A digital integrator is disclosed that provides a wide dynamic range and extremely fast clearing of previous integration results. The digital integrator includes an analog-to-digital converter that generates a series of digitized representations of an electrical signal and further includes an ALU that generates an integration result by adding successive digitized representations in the series throughout an integration interval. The digital integrator includes circuitry for clearing the integration result from the ALU after completion of the integration interval in preparation for a subsequent integration interval on the electrical signal.

Abstract: The subject invention relates to a type of multi-bits successive-approximation ADC to convert analog signals into a N-bits digital output code, wherein N is the number of bits of output code. The ADC includes (a) an input sample/hold circuit that takes the sample of analog input signals during the first half of clock cycle, and maintains the analog input signals after the sampling and during a conversion process. The ADC also includes (b) a reference voltage generator, to produce different reference voltages, (c) CLOCK pulse generation circuitry to continuously produce CLOCK pulse signals, (d) several comparators for comparison of the sampled input signals with a rough reference voltage to produce a rough digital output code. The ADC applies a temperature scale to roughly estimate the sampled analog input signals, this to be completed in a second half of the CLOCK cycle.

Abstract: A transmitter for use in a process control setting includes a sensor adapted to couple to a process and provide a sensor output related to a parameter of the process. A modulator coupled to the sensor output responsively provides a digital bit stream output representative of the sensor output. A filter provides a current decimation output. A comparator compares a previous decimation output with the current decimation output. Circuitry is provided for transmitting an output related to the parameter based upon the current decimation.

Abstract: A successive approximation shift register without redundancy for a finite-state machine of the sequential type, is also effective to store the machine states. The shift register comprises a chain of logic circuits of the bistable type (FF0,FF1, . . . ) having an input stage with selectable signal inputs which are feedback connected through logic OR gate circuits (OR0,OR1, . . . ,OR6).

Abstract: Circuitry for reducing charge injection effects in an offset voltage compensation circuit for a switched-capacitor amplifier is provided. The switched-capacitor amplifier circuitry includes an operational amplifier having inverting and noninverting inputs and an output. An initialization circuit provides the inverting input with a voltage close to the offset voltage of the operational amplifier. A feedback circuit ensures that the voltage at the inverting input attains the offset voltage. In order to attenuate the effects of disengaging the feedback circuit after the input voltage attains the offset voltage, an attenuation circuit is provided. The attenuation circuit prevents the voltage at the inverting input from being affected by charge injection effects that arise when the feedback circuit is disengaged. The offset voltage compensation circuit may be used with switched-capacitor amplifiers configured as comparators, amplifiers, or successive approximation A/D converters.

Abstract: A communication receiver (600) utilizes a band-pass sigma-delta converter (100) for receiving a radio signal. The band-pass sigma-delta converter (100) includes a comparator (106) coupled to an adder-filter (101) for making a comparison between a predetermined reference level (110) and an intermediate signal (125), and for generating a comparison result signal (114) responsive to the comparison. A storage element (108) is used for storing the comparison result signal (114) for a predetermined delay period, thereby producing a clocked output signal (118). The adder-filter (101) is coupled to an analog signal (103) and to the clocked output signal (118) for subtracting the clocked output signal (118) from the analog signal (103) to produce a difference signal (120) that is filtered by a commutating filter (400) for generating the intermediate signal (125) responsive to the difference signal (120).

Abstract: A system is provided for digitizing the setting of a potentiometer of the type used in an analog joystick for computer games. The analog output of the potentiometer is applied to one of two inputs of a voltage comparator. When a readout of the joystick position is desired, a "write" input is applied to a counter to permit it to commence counting at a predetermined frequency from an initial or zero count. The digital outputs of the counter are coupled to the inputs of a digital-to-analog converter, the output of which is coupled to the second input of the voltage comparator. When the count in the counter produces a voltage at the output of the digital-to-analog converter corresponding to the voltage setting of the potentiometer, the comparator provides an output signal. The time delay from the time the write pulse occurs until this signal is obtained is representative of the potentiometer setting.

Abstract: An A/D converter includes a three-state comparator for detecting a higher state, a lower state and a equal state of a sampled analog signal with respect to a sequence of reference signals which are supplied from a counter or register after D/A conversion. After the equal state is detected, the D/A converter and the three-state comparator are stopped for power saving. The A/D converter further includes a frame memory and a control section which provide the counter or register with an initial code for each conversion cycle based on the last code of the previous conversion cycle constituting the previous digital output of the A/D converter. The A/D converter well follows the sequential change of the input level between the conversion cycles.

Abstract: An analog-to-digital converter includes a comparator for comparing a voltage output by a digital-to-analog converter with an input analog voltage at each bit of an n-bit word. The input analog voltage and the analog output voltage of the digital-to-analog converter are alternatingly used as the reference in the comparison, i.e., for every other bit of the n bits. A one-bit result-of-comparison signal indicative of the result of the comparison is output for each of the n bits. Only alternating result-of-comparison signals are inverted and the inverted and non-inverted result-of-comparison signals are stored in a successive approximation register as the converted digital signal and are supplied to the digital-to-analog converter for use in the comparison.

Abstract: A multiple channel analog to digital converter utilizing common conversion circuitry for converting multiple analog signals into corresponding digital signals. The converter includes an input stage having a plurality of capacitors, each one corresponding to one of the analog signals. The capacitors sample the respective analog signals and are successively coupled to common conversion circuitry, including a CDAC and a comparator. The CDAC iteratively increments or decrements the voltage of a selected one of the sampled analog signals for comparison to a reference voltage by the comparator. The comparator output is latched by a successive approximation register to provide a parallel output signal which is fed back to control the CDAC.

Abstract: A successive approximation A/D having dual comparators for allowing a larger range of analog input signals to be converted into digital form. One comparator is an N-channel device, and the other comparator is a P-channel device. The A/D switches to either the N-channel device or the P-channel device based upon whether the first two comparisons the determine the most-significant bit and the next-most significant bit are a "11", in which the N-channel device is selected, or anything else, in which the P-channel device is selected. Switching circuitry is included to output the proper comparator based on these two comparisons.Control circuitry is also provided to allow for successive conversions using only a single address read.

Abstract: In an analog/digital converting circuit, when an analog input voltage exceeds a reference voltage, the analog input voltage is modified into analog voltages not exceeding the reference voltage, and comparison voltages generated by dividing the reference voltage are compared with the modified analog voltages.

Abstract: A micropower analog-to-digital converter (ADC) for use in an implantable medical device is disclosed. The ADC achieves a high conversion speed at micropower levels through a number of timing and circuit improvements over the conventional implementation of the successive approximation ADC architecture. The ADC includes a digital-to-analog converter (DAC) that preferably is implemented as a binary-weighted, switched capacitor array that employs top plate charging and performs bipolar conversion. The DAC provides an analog output signal representing array charge to a comparator. During a comparator latch phase, the DAC asynchronously determines a bit of the ADC digital output signal in response to the comparator output, and initiates a test of the next least significant bit during the same latch phase. Further, the DAC analog output signal is timed to settle during the latch phase in response to both the bit update and the next bit test.

Abstract: Method and apparatus for automatic cooking in a microwave oven capable of executing the automatic cooking in an optimal state by detecting an outflow air temperature and a weight of food at an initial stage, calculating an outflow air temperature difference after executing a cooking operation for a predetermined time, calculating an additional value by giving a fuzzy membership function to the outflow air temperature difference and the weight of food, calculating a first stage heating time by executing an operation process according to a fuzzy rule, calculating second to fifth stage heating times by multiplying the first stage heating time by predetermined values, respectively, and executing a cooking operation for the calculated stage heating times.

Abstract: An output circuit for use with an array of high dynamic range analog sensor produces a digital output signal from the array prior to multiplexing, so as to avoid analog multiplexing noise. The analog signals are converted to digital form using a simple, parallel analog-to-digital conversion process at the outputs of low noise array amplifiers. By latching the converted digital output signals into shift registers, the analog multiplex function is obviated and the full dynamic range capability of the detector-amplifier combination is made available.