Abstract: An MB810 encoder and/or decoder, dual mode encoder and/or decoder, and a method for generating MB810 codes are provided. Twelve state points in the form of a 4×3 matrix on a state transition map are formed with binary unit digital sum variation & alternate sum variation (BUDA). A 10-bit code from 8-bit data is generated outputting a 10-bit code from a predetermined state point to form the matrix. Codes forming a complementary pair from a set of codes capable of arriving at state points forming the matrix are selected. Codes forming the 12 state points by supplementing state points lacked in the codes forming a complementary pair are selected. Control codes including IDLE code from the codes forming the 12 state points are selected. Codes generating the IDLE code by a bit string between neighboring codes among the codes forming the 12 state points are removed.

Abstract: A method and apparatus reduces a DC level of an input word. The input word is divided into a plurality of components that include n symbols. The n symbols of the components are summed for each component. The component is encoded into a substitute component if a sum for the component exceeds a threshold. The components having a sum that does exceed the threshold are combined with at least one substitute component into an output word. An output word template is selected based on a number of substitute components and on a position that the substitute components originally occupied in the input word. The substitute components are inserted in the output word template. The components that have a sum that does not exceed the threshold are inserted in the output word template. Address and indicator symbols are inserted in the output word.

Abstract: The present invention relates to an encoding apparatus and a corresponding method for two-dimensionally encoding user data of a user data stream into channel data of a channel data stream along a two-dimensional channel strip of at least two bit rows one-dimensionally evolving along a first direction and being aligned with each other along a second direction, said two directions constituting a two-dimensional lattice of bit positions. According to the invention the apparatus comprises a modulation code encoder for modulation code encoding said user data into said channel data according to a two-dimensional modulation code being adapted to prevent predetermined worst case patterns of channel data in said channel data stream. The worst-case patterns are typical for high-density two-dimensional optical storage channels.

Abstract: A digital sync signal added in a modulator to a train of codes having a digital sum value, and detected in a demodulator. The digital sync signal has a pattern that breaks a maximum run and a pattern that preserves a minimum run and a maximum run. The digital sync signal has a bit that is selectively determined to be a “0” or a “1” for controlling the digital sum value of the train of codes. The minimum run is repeated no more than a predetermined number of times irrespective of whether the digital sync signal includes the minimum run.

Abstract: A communication system includes an encoder that receives user data and includes running digital sum encoding and turbo encoding. The running digital sum encoding is preserved in an encoder output to a channel. A decoder receives a channel output and comprises running digital sum decoding and turbo decoding to reproduce the user data in a decoder output.

Abstract: A block encoder flexibly encodes K codes to produce an encoded data block. The block encoder receives an unformatted block of 10 Gigabit Media Independent Interface (XGMII) data. The unformatted block of data includes data and/or K characters, both of which can be located in any position of the unformatted block. The block encoder inserts data characters into a first set of slots of the encoded data block. The block encoder encodes K characters to produce corresponding encoded K characters. Each encoded K character includes a link field, a position field and a recoded value field. The encoded K characters are inserted into a second set of slots of the encoded data block. A synchronization header is attached to the encoded data block to distinguish control blocks from pure data blocks. The header and encoded data block are subsequently scrambled in preparation for transmission.

Abstract: An apparatus has a conversion circuit, a precoder circuit, and a selection circuit. The conversion circuit converts user data b1, b2, b. . . bk to a coded sequence c0, c1, c2 . . . cq. The selection circuit selects c0 in the coded sequence c0, c1, c2 . . . cq such that the output of the precoder circuit has less than a maximum number q of transitions. The conversion circuit may include an encoder circuit to convert user data b1, b2, b3 . . . bk to a sequence c1, c2 . . . cq, and a transition minimization circuit to add c0 to the sequence c1, c2 . . . cq. The apparatus may have a circuit to add at least one additional bit, which may be a parity bit, to the coded sequence c0, c1, c2 . . . cq.

Abstract: A transmitter for a data communication system that comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a set of codewords representing data in the input data stream, and the members of the set are substantially DC balanced, such as a Manchester encoded symbol set. An integrating circuit on the second integrated circuit integrates codewords by integrating for a first interval with a positive polarity within a particular signaling cell, and integrating for a second interval with a negative polarity within the particular signaling cell, to produce output representing the codewords. A sense circuit produces an output data stream.

Abstract: A SYNC bit inserting section 14 adds a sync signal to a train of codes, after adding a minimum run, said sync signal having a pattern that breaks a maximum run. It is thereby possible to provide a reliable sync signal pattern.

Abstract: The present invention provides a data transformation apparatus for transforming a first data block into a second data block. The first data block comprises a predetermined number of bits. The data transformation apparatus comprises a control bit module, a processing module, and a selection module. The control bit module is used for generating a plurality of control bit sets, wherein each control bit set represents a transformation procedure of the first data block. The processing module is used for receiving the first data block and the plural control bit sets, and accordingly for generating a plurality of first reference values. The selection module connects with the processing module and generates the second data block according to the plural first reference values and a predetermined judgment value.

Abstract: In a data encoding apparatus, when a prefix length calculation and determination units determine that the code length of a variable length code constituted of continuous bits “0” is equal to or greater than the predetermined maximum prefix length max_prefix during Golomb-Rice encoding of encoding subject data having a fixed length of D bits, second encoding is performed in place of the Golomb-Rice encoding. The second encoding is performed by having a prefix generation unit generate a prefix constituted of continuous bits “0” corresponding to the max_prefix, and having a code generation unit attach the prefix to the upper order bits of the encoding subject data. Furthermore, when a control code such as a restart marker is to be attached, a marker generation unit generates, as the control code, a code constituted of continuous bits “0” by the number which is equal to or greater than the length of (max_prefix+2×D).

Abstract: The present invention pertains to a modulation apparatus and method in which the modulation apparatus is realized with a simple circuit structure and is easily applicable to other systems. A pattern conversion unit 32 converts data having a basic data length of 2 bits supplied from a DSV control bit determination and insertion unit 31 into a variable-length code having a basic code length of 3 bits in accordance with a conversion table. A minimum-run-length limitation code detection unit 33 detects, from a data sequence containing a DSV control bit, the position of minimum runs consecutive from a channel bit string converted by the pattern conversion unit 32. A consecutive-minimum-run replacement unit 34 replaces a predetermined portion of the channel bit string supplied from the pattern conversion unit 32 for a predetermined pattern based on the position information supplied from the minimum-run-length limitation code detection unit 33, and limits the minimum run length to a predetermined number or less.

Abstract: A method for encoding and decoding a sequence of words, corresponding signal, encoder, decoder, computer programs and storage means. A method for encoding a sequence of source words includes a step of selecting an encoding function to be applied to a source word to be encoded as a function of the content of the word to be encoded and of at least one preceding source word in the sequence so that the concatenation of two consecutive encoded words has no binary element, called an isolated binary element, sandwiched between two binary elements with a value different from that of the isolated binary element. The method further includes a step of encoding the word to be encoded implementing the selected encoding function.

Abstract: An encoded-bit-string generating unit generates a bit string encoded by scrambling an input bit string. A direct-current-component evaluating unit selects a bit string having a predetermined width in the bit string generated by the encoded-bit-string generating unit, while shifting bits one by one, and evaluates the direct-current component in the selected bit string. A bit-string extracting unit extracts a bit string with suppressed direct-current component, based on a result of an evaluation by the direct-current-component evaluating unit.

Abstract: An error correction compensating ones or zeros string suppression system and method for use in a digital transmission system is herein disclosed. In digital transmission systems utilizing error control coding (ECC)/forward error correction (FEC) to reduce the number of bit errors in a bit stream, long strings of ones and zeros are easily suppressed by detecting a prohibited length of ones or zeros, and flipping a bit in the string of ones or zeros. This method and system removes the violation of the ones or zeros bit string requirement by flipping a bit in the string, while the receiving side utilizes the error correction capability of the ECC/FEC to correct the inverted bit.

Abstract: A recording method, wherein, when a certain portion of main data is recorded by being encoded by a first encoding method and the other portions of the main data is recorded by being encoded by a second encoding method, an encoding process is performed by the first encoding method so that, when data which is recorded in such a manner that the data encoded by the first encoding method is decoded by a decoding method corresponding to the first encoding method, and thereafter, is further encoded by the second encoding method, is decoded by a decoding method corresponding to the second encoding method, the sum value of DC components per unit time increases.

Abstract: A system (100) and method (200) of combining codewords is provided. The system can include a splitter (120) for splitting a first codeword (110) into a most significant bits part MSP (112) and a least significant bits part LSP (114), a combiner (130) for combining the MSP of the first codeword with a second codeword to produce a first group (132), and a concatenator (140) for concatenating the first group with the LSP to produce a second group (134), and multiplexing the first group with the second group to produce a multiplexed codeword (150). Bit-errors in the LSP correspond to decoding errors only in a codeword associated with the LSP, and not to decoding errors in other codewords.

Abstract: The present invention provides a method and system for converting an input code into an output code. The method includes: determining a plurality of input code subsets of the input code; converting the input code subsets into a plurality of output code subsets, respectively; and merging the output code subsets to generate the output code. The system includes a splitter, for determining a plurality of input code subsets of the input code; a mapper, coupled to the splitter, for converting the input code subsets into a plurality of output code subsets, respectively; and a merger, coupled to the mapper, for merging the output code subsets to generate the output code.

Abstract: A coder is fed with precoded data such that the absolute value of the running digital sum (RDS) of the code words as produced by the coder is limited. This is achieved by ensuring that in a group of 2 code words, the RDS of the first code word is compensated by the RDS of the second code word. The RDS at the end of the second code word is then zero and the excursions of the RDS from the start of the first code word until the end of the second code word are limited because there are only a limited number of bits that can contribute to an increase of the absolute value of the RDS.

Abstract: A method and apparatus are provided for decoding a sequence of code words into a sequence of data words. Each code word includes an encoded data word and an indicator bit. The encoded data word is extracted unchanged into a respective unencoded data word if an indicator bit has a first binary value and is extracted into the unencoded data word and then complemented if the indicator bit has a second, opposite binary value.

Abstract: A communications channel includes a buffer that receives symbols of user data including a plurality of M-bit symbols. A seed selector receives the M-bit symbols of the user data, selectively removes symbols of the user data from a seed set, and selects a scrambling seed from symbols remaining in the seed set. A scrambling device that communicates with the seed selector and the data buffer generates scrambled user data using the user data and the selected scrambling seed. A Hamming weight coding device determines a Hamming weight of symbols of the scrambled user data and selectively codes the symbols depending upon the determined Hamming weight.

Abstract: A DVD recording method for recording data onto recording media by using a given coding rule, including: generating two data streams by using a plurality of code mapping variants prepared for coding input data, quasi-randomly selecting one of the plurality of code mapping variants, if absolute DSVs of the two data streams are substantially equal, and converting into recording code sequences, where polarities of said two data streams are inverted with respect to each other; and recording data onto said recording media, based on said recording code sequences.

Abstract: Six record areas for predetermined data that has been encoded and digitally modulated are formed in a data record area on a disc. The record areas have different offset compensation amounts. The offset compensation amounts allow all offset amounts that may take place in an error correction code encoder to be compensated. Thus, regardless of the offset amount generated by the error correction code encoder, encoded and modulated data that has been generated by the conventional EFM modulating system and recorded in one of the record areas securely causes DSV to deviate. Each of the record areas is set to a sufficient length that allows the effect of which DSV deviates to be recognized.

Abstract: An apparatus and method for checking validity of an 8B/10B code-group are provided. The apparatus for checking validity of an 8B/10B code-group includes a 6B/5B disparity classification unit, a 4B/3B disparity classification unit, an RD6 detection unit, an RD4 detection unit, an 8B/10B code-group rule violation detection unit, an RD error detection unit, and a unit for outputting 8B/10B code-group validity. The apparatus receives an 8B/10B code-group, divides into a least significant 6-bit nibble and a most significant 4-bit nibble, detects a running disparity, and by doing so, determines the validity of a code-group. The apparatus and method for checking validity of an 8B/10B code-group relatively shortens the critical path, which indicates the number of combinational logic circuits that should be operated in a unit time, and therefore the apparatus and method are appropriate to high-speed systems such as gigabit Ethernet systems.

Abstract: A method and apparatus for modulating data modulates data having a length of m-bits to a variable length code having a basic code length of n-bits. A SYNC bit inserting section adds a sync signal to a train of codes, after a minimum run. The sync signal has a pattern that breaks a maximum run.

Abstract: An encoder that encodes a communication signal including a precoder that precodes portions of the communication signal. The portions comprise M bits, where M is greater than. A buffer buffers said portions. A DC tracking device that modulates a flip signal based on a comparison of a DC value of one of the portions of the communication signal and an average DC value of N previous bits of the communication signal where N is greater than M. A flip device that selectively flips said portions based on said flip signal.

Abstract: A precoder for an optical duo-binary transmission apparatus disposing the precoder before a time division multiplexer includes a judgment unit for judging whether an odd number or even number of ‘1’s exist in data input signals of N channels inputted at an nth time of channel input. Further included in the precoder is a toggle unit for toggling an output signal of the judgment unit when the judgment is odd, and for determining an output value for one of the channels. The precoder also has an output unit for determining output values of other channels according to a respective data input signal and a predetermined channel from among the N channels.

Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. Code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0,” while two's complement q1 of a sum of code sequences c1 up to that time is “1”. That is, the condition that q0?q1 is met.

Abstract: An apparatus and method for modulating and demodulating data to transmit or record the data on a recoding medium. Data is modulated and demodulated into a variable-length code. The modulated data comprises a sync signal adding means for adding a sync signal to a train of codes after adding a minimum run. The demodulated data comprises a sync signal detecting means for detecting, from a train of codes, a sync signal having a pattern that breaks a maximum run, after detecting a minimum run. A SYNC bit inserting section adds a sync signal to a train of codes, after adding a minimum run, where the sync signal has a pattern that breaks a maximum run.

Abstract: An encoder includes a DC tracking device that generates a flip signal as a function of a statistical measure of portions of a communication signal. The flip signal has a flip state and a nonflip state. A flip device selectively flips the portions based on the flip signal to reduce an average DC value of the communication signal.

Abstract: The invention filed involves a method of coding and/or decoding binary data for wireless transmission, particularly for radio transmitted data. A sequence of binary data, introduced at the entry to the coding machine with a class N coder (KOD) comprising a register (REG), a comparator (COMP) and a counter (CITN), where N is a number greater than or equal to 3, is separated into a sequence of binary data of the same value, so that the length of each such sequence is not less than one and not more than N, and so that the binary values of the data introduced at the entry to the coder (KOD) are compared with the value last received and recorded in it, the lengths of the same sequences at this entry are read up to the number N and, after reading to N, a sequence of binary data of a value opposite to the value at the entry to the coder (KOD) is inserted, this inserted data sequence having a length M, where M is a number greater than or equal to one and less than N.

Abstract: In a data demodulating method and apparatus, and a code arranging method, a multiplexer multiplexes an input data stream divided by a predetermined length into a plurality of types of pseudo random data streams using multiplexed information of predetermined bits by applying a predetermined multiplexing method to each of the pseudo random data streams. An encoder RLL-modulates the plurality of types of pseudo random data streams to create a modulated code stream including a minimum of DC components. The multiplexer generates the random data streams by inconsecutively scrambling the input data stream using the multiplexed information. The encoder weak DC-free RLL-modulates each of the multiplexed data streams without using a DC control sub code conversion table to which additional bits are added and provides a code stream including a minimum of DC components among multiplexed, RLL-modulated code streams.

Abstract: A method and apparatus for data coding for high-density recording channels exhibiting low frequency contents is disclosed. Coding is used that satisfies both Running Digital Sum (RDS) and Maximum Transition Run (MTR) properties, which are desirable for achieving high-density recording for recording channels exhibiting low frequency components such as perpendicular magnetic recording channel.

Abstract: A communications channel includes a buffer that receives user data symbols including a plurality of M-bit symbols. A seed selector receives the plurality of M-bit symbols, selectively removes symbols from a seed set based on Hamming distances between at least two of the M-bit symbols, and selects a scrambling seed from remaining symbols in the seed set. A scrambling device that communicates with the seed selector and the data buffer generates scrambled user data based on the user data symbols and the scrambling seed. The communications channel is implemented in a data storage system. The seed selector ensures a minimum Hamming weight of 15 percent in the scrambled user data. The seed selector compares first and second user data symbols in the plurality of M-bit symbols.

Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. Code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0,” while two's complement q1 of a sum of code sequences c1 up to that time is “1”. That is, the condition that q0?q1 is met.

Abstract: In an optical disk apparatus, the polarity of synchronization information is adaptively set to thereby improve the quality of data recording and reproduction. When inserting and recording synchronization information, an encoder of an optical disk apparatus temporarily sets the polarity of the synchronization information to either a mark or a space in accordance with a predetermined rule. A DSV which is obtained if the synchronization information is to be recorded with the polarity which has been temporarily set is computed. If the DSV which is computed is equal to or smaller than a predetermined limit value, the polarity which has been temporarily set is accepted and the synchronization information is actually recorded with the polarity. If the DSV which is computed exceeds the limit value, on the other hand, the polarity which has been temporarily set is not adopted, and the synchronization information is actually recorded with a polarity which is different from the polarity.

Abstract: A Hamming weight encoder includes an input that receives user data including P symbols and a Hamming weight module that determines a Hamming weight of N of said P symbols. N and P are integers greater than one and N is less than or equal to P. The Hamming weight encoder also includes a comparing module that compares the Hamming weight to a Hamming weight threshold and an inverting module that selectively bitwise inverts bits in said N symbols based on said comparison.

Abstract: In a data demodulating method and apparatus, and a code arranging method, a multiplexer multiplexes an input data stream divided by a predetermined length into a plurality of types of pseudo random data streams using multiplexed information of predetermined bits by applying a predetermined multiplexing method to each of the pseudo random data streams. An encoder RLL-modulates the plurality of types of pseudo random data streams to create a modulated code stream including a minimum of DC components. The multiplexer generates the random data streams by inconsecutively scrambling the input data stream using the multiplexed information. The encoder weak DC-free RLL-modulates each of the multiplexed data streams without using a DC control sub code conversion table to which additional bits are added and provides a code stream including a minimum of DC components among multiplexed, RLL-modulated code streams.

Abstract: In a data demodulating method and apparatus, and a code arranging method, a multiplexer multiplexes an input data stream divided by a predetermined length into a plurality of types of pseudo random data streams using multiplexed information of predetermined bits by applying a predetermined multiplexing method to each of the pseudo random data streams. An encoder RLL-modulates the plurality of types of pseudo random data streams to create a modulated code stream including a minimum of DC components. The multiplexer generates the random data streams by inconsecutively scrambling the input data stream using the multiplexed information. The encoder weak DC-free RLL-modulates each of the multiplexed data streams without using a DC control sub code conversion table to which additional bits are added and provides a code stream including a minimum of DC components among multiplexed, RLL-modulated code streams.

Abstract: Techniques are provided for performing substitutions of bit sequences that are known to cause errors. Input data is initially modulation encoded. The modulated data is then analyzed in a sliding window to determine if it contains any additional bit sequences that are known to cause errors. If an error prone bit sequence is identified in the data, a substitution engine replaces the error prone bit sequence with a predetermined pattern of bits that is less likely to cause errors. The bit stream output of the substitution engine is then recorded on a storage medium. The recorded bit stream is decoded when it read from the medium. The decoding process identifies the substituted bit pattern and replaces the substituted pattern with the original sequence of bits.

Abstract: An up-sampled data stream, upsampled times a factor P, is generated by the input block providing signal samples having a frequency rate, while an intermediate data stream is generated by a Rate Adapting Stage providing signal samples adapted to an intermediate frequency rate. An output data stream is delivered by a final low pass filter, and includes M signal samples having a desired output sample frequency rate (fOUT=M/Ts). The method provides generation of a provisional stream in the Rate Adapting Stage, wherein this provisional stream is affected by aliases falling within the output Nyquist band [?fOUT/2, fOUT/2], although being adapted to the output frequency rate by a direct insertion of zero samples into the processed stream when L<M, or by a direct cancellation of samples when L>M. Then these aliases are suppressed in the Rate Adapting Stage by weighting the provisional stream via a set of weights.

Abstract: The design of communication and storage systems requires a choice of modulation and coding. In conventional storage and communication systems, the commonly used modulation scheme is called Non Return to Zero (NRZ) and the commonly used codes are called Run Length Limited (RLL) codes. The disclosure describes a new modulation scheme that can be used to increase the data transmission rate or storage density. The disclosure also describes codes that are referred to as Interval Modulation Codes, which can be used to transmit or store information efficiently using the new modulation scheme. Also described are procedures for determining if there exist suitable Interval Modulation Codes, given predetermined parameters that describe their desired performance. The disclosure also describes procedures or algorithms for constructing optimal Interval Modulation Codes given a set of parameters that describe their performance. The described techniques can be used in different communication (e.g.

Abstract: The method is based on a controlled, direct insertion/cancellation of samples in a processed data stream. An up-sampled data stream is generated by the input block providing signal samples having a frequency rate. An intermediate data stream generated by a Rate Adapting Stage providing signal samples adapted to an intermediate frequency rate. An output data stream is delivered by a final low pass filter, including M signal samples having a desired output sample frequency rate. The method provides a generation of an up-sampled weighted stream in the Rate Adapting Stage by weighting the signal samples of the up-sampled data stream via a set of weight. Then, the input frequency rate is adapted to the output frequency rate in Rate Adapting Stage by a direct insertion of zero samples into the processed stream when L<M, or by a direct cancellation of samples when L>M.

Abstract: Techniques are provided for applying modulation constraints to data streams divided into separate interleaved portions. The even and odd bits in a data stream are separated into two data paths. A first modulation encoder encodes the even bits according to a first constraint. A second modulation encoder encodes the odd bits according to a second constraint. The two encoded data streams are then interleaved to form one data stream. The modulation encoders can encode the two data paths using Fibonacci encoding.

Abstract: A method and system for a feed-forward encoder is described. The method includes evaluating one or more source characters to determine whether each source character will invert or maintain a current running disparity and determining a running disparity for each source character before encoding the source character based on the current running disparity and whether the source character will invert or maintain the current running disparity. The current running disparity along with the associated source character may then be passed to an encoder to encode the source character into a transmission character.

Abstract: In a method of multi-dimensionally encoding a user data stream of user words into a channel data stream of channel words evolving in a one-dimensional direction of infinite extent, a user word is encoded into an NRZ channel word by selecting a NRZ channel word from a code table depending on the user word and the current state of an underlying finite-state-machine. A NRZ channel word comprises a sequence of NRZ channel symbols of NRZ channel bits having a one-dimensional interpretation along said one-dimensional direction and wherein states of an underlying finite-state-machine describing the characteristics of the multi-dimensional code are defined by NRZI channel bits of the previous channel work and by NRZ channel symbols of the current channel word. The NRZ channel symbols are transcoded into NRZI channel symbols by a one-dimensional 1T-precoding operation including an intergration modulo 2, said 1T-precoding operation being carried out along said one-dimensional direction of infinite extent.

Abstract: An encoder encodes a communication signal including a precorder that precodes portions of the communication signal. The portions comprise a plurality of bits. A buffer buffers said portions. A DC tracking device modulates a flip signal based on a comparison of a DC value of one of the portions of the communication signal and a weighted average DC value of a plurality of previous portions of the communication signal. A flip device selectively flips said portions based on the flip signal.

Abstract: A state modulation method and an apparatus for inserting state control codes are provided. To overcome the problems of inefficient control on direct current and low frequency component in conventional state modulation techniques, the disclosed method inserts state control codes in a state modulation method to increase the probability for selection. With multi-level characteristics, the inserted state control codes can provide a plurality of sets of different signals for selection during coding. Thereby, the direct current and low frequency components can be well controlled.

Abstract: When a zero run, which violating G constraint of a run-length-limited (RLL) code, is detected from the data stored in a first input register 1111 and a second input register 1112, bits before and after the zero run is transferred to a temporary register 1150 via a bus for zero run removal 1130 to be combined to each other. Thus, by effectively using the mechanism of bus transfer, a circuit can be simplified, thereby realizing a small circuit.

Abstract: A code conversion method and apparatus is provided for scrambling and modulating data. The method and apparatus includes scrambling an input main data unit based on any of plural types of pseudo-random number sequences, and modulating the scrambled main data unit based on any of plural types of modulation data. An output main data unit is produced from the modulated main data unit, and a calculated value representing a difference between a number of 0 bits and a number of 1 bits included in the output main data unit is obtained. Any of the modulation data is then selected dependent upon the calculated value.