Abstract: A bit resolution phase detector can be realized for a parallel elastic store by comparing a write bit clock and a read bit clock to determine when stuff bits are required; upon detection of phase alignment between the write and read clocks, the phase detector will output a signal which will enable the insertion of a data bit into the stuff opportunity bit and cause the write clock to lag the read clock by one bit period.

Abstract: Fractional rate modulation is accomplished by separating incoming data into frames of bits. Each frame in partitioned into bit words of unequal lengths. The words are divided by a modulus to obtain remainders. The remainders are transmitted using, for example, QAM modulation. At the receiving end, the process is reversed. The ratio of baud rate of the system to the incoming bit rate defines the modulus as well as the number of QAM modulation points. A "data rate throttling" technique takes advantage of the capabilities provided by the foregoing to allow the rate at which data is channel mapped and transmitted over a communication channel to be easily varied in small increments.

Abstract: A sampling rate converter for converting an input digital signal, such as D2 PAL, into an output digital signal, such as D1 PAL, has a pair of polyphase filters. The input digital signal is input in parallel to the two polyphase filters, with the phase selected by one of the filters being offset by one from that of the other. The outputs of the polyphase filters are input to a linear interpolator to produce the output digital signal. The resolution of the sampling rate conversion is a function of the number of phases N of the polyphase filters and the number of interpolation steps M of the interpolator.

Abstract: A system for digital conferencing over narrowband channels which allows use bymultiple simultaneous speakers and which allow for interfacing between vocoders which operate at different bit rates. The system takes advantage of the properties of multi-rate parametric vocoders (which includes the Sinusoidal Transform Coder and the Multi-Band Excitation Vocoder, as well as embedded coders), defined as parametric vocoders for whom the basic model and parameter set remain unchanged over a wide range of bit-rates. The system performs signal summation. To maintain quality for a single speaker while allowing multiple speakers, the system adaptively allocates channel bandwidth based on the number of speakers to be represented. This system also provides digital-to-digital conversion between narrow-band digitizers (vocoders) operating at different bit-rates. The system takes advantage of the characteristics of a particular class of coders, sine-wave based coders, which perform parameter estimation by sine-wave summation.

Abstract: A solid state camera apparatus converts image signals read from a solid state image-sensing device at a reading clock rate of a first frequency f.sub.CCD to digital video signals at the reading clock rate, converts the resulting digital video signal using a clock signal of a second frequency f.sub.STD [f.sub.STD =f.sub.CCD *n/m (where m and n are positive integers and m>n)] to form digital video signals with a transmission clock rate of the second frequency f.sub.STD, and applies image processing to the digital video signals at the reading clock rate of the first frequency f.sub.CCD so as to form output video signals.

Abstract: A data transmitting QAM modem with partitions incoming data into unequal frames. Some of the bits in each frame are encoded using fractional rate encoding and then recombined the rest of the bits to form frames of equal bits. Trellis encoding is then performed on the frames of equal bits. Advantageously the number of points in the QAM constellation is also increased to an integer divisible by a power of 2 to reduce the complexity of fractional rate encoding.

Abstract: Fractional rate modulation is accomplished by separating incoming data into frames of bits. Each frame is partitioned into bit words of unequal lengths. The words are divided by a modulus to obtain remainders. The remainders are transmitted using for example QAM modulation. At the receiving end the process is reversed. The ratio of the baud rate of the system to the incoming bit rate defines the modulus as well as the number of QAM modulation points.

Abstract: A system is provided for converting an input digital data sampled at a first sampling frequency to an output digital data to be sampled at a second sampling frequency. The input digital data is sampled to obtain sampling data with respect to an estimating data corresponding to a data at a sampling point of the output data. The sampling is performed within a period of the least common multiple between a period of sampling of the input digital data and a period of sampling of the output digital data. The estimating data is interpolated from the obtained sampling data.

Abstract: A circuit arrangement for converting a digital signal of a first frequency into a signal of a second frequency and including an interpolator/decimator is characterized, notably for asynchronous first and second clock signals, in that there is provided at least one multiplexer arrangement which includes a first register which is clocked at the inverted first clock frequency and a second register which is clocked at the second clock frequency, and also includes a multiplexer, the input signal of the multiplexer arrangement being applied to the first register and to a first input of the multiplexer whose second input is coupled to the output of the first register, there also being provided a control circuit which alternately switches the signals applied to the two inputs of the multiplexer to its output in such a manner that at the instants at which this signal is written into the second register a valid signal is always present at the output of the multiplexer.

Abstract: A first and second digital rate converter device and method provides for synchronization between a first digital sample sequence and a second digital output sequence related to the first digital sample sequence for a rate converter pair (501, 511; 601, 611). The method typically utilizes at least one of: queue monitoring and zero-crossing with resetting to minimize sampling timing error.

Abstract: A sampling frequency conversion apparatus having N (where N is an integer, which is two or more) sampling conversion means serially connected, each of the N sampling frequency conversion means comprising a first digital filter for outputting a signal with longer bit length than that of an input signal, and first sampling means for sampling a signal which is output from the digital filter at a sampling frequency, the sampling frequency decreasing as the stage of the sampling frequency conversion means becomes later. Thus, the earlier stages which should be operated at a high speed, the bit length of signals becomes short. In the later stages where the bit length becomes long, the sampling frequencies are decreased. Consequently, the apparatus can be operated at a high speed and constructed at a low cost.

Abstract: An information track on a record carrier (2) is read by a read head which includes detectors producing detection signals (IA, IB, IC and ID) which correspond to the information pattern on the track. The respective detection signals are converted by analog-to-digital converters (16a, 16b, 16c and 16d) into respective series of n-bit digital signal values (ua, ub, uc and ud). From such signal values a data signal (SD) is derived which is representative of the information being read. The signal values are also applied to respective cascade arrangements of a quantizing circuit (21a, 21b, 21c and 21d) and a decimating filter (22a, 22b, 22c and 22d), which convert them into respective series of signal values (va, vb, vc and vd) which represent only the low frequency portion of the information in the detection signals produced by the read head and include control information relating to tracking by the read head.

Abstract: An apparatus for encoding variable bit length data words into constant bit length data words concatenates the variable length data words supplied at a first data rate so as to output constant length data words at a second data rate. An apparatus for decoding constant bit length data words into variable bit length data words shifts and concatenates the constant bit length data words, determines when a variable length data word is present in the concatenated data, supplies information about the number of bits in the variable length data words which is used when shifting the next constant bit length data word, and outputs variable bit length data words.

Abstract: A sampling frequency conversion apparatus according to this invention converts an input data string based on an input sampling pulse into a data string based on an output sampling pulse having a frequency different from the frequency of the input sampling pulse. The apparatus reproduces the input sampling pulse based on the input data string, generates interpolation sampling pulses having a frequency corresponding to an integral multiple of the frequency of the input sampling pulse, and generates an interpolated data string from the input data string on the basis of the interpolation sampling pulses. On the other hand, the apparatus phase-modulates the output sampling pulse to diffuse its frequency spectrum, and selects and determines a timing of the interpolation sampling pulse closest to the timing of the phase-modulated output sampling pulse. The apparatus selects data corresponding to the selected timing from the interpolated data string, and outputs the selected data.

Abstract: In a sampling rate converter which converts a sampling frequency of digital signals sampled at a first sampling frequency into a second sampling frequency, output clocks corresponding to the second sampling frequency are counted in a cyclic fashion from an initial value to a maximum value based on periodicity of the first and second sampling frequencies. Coefficient addresses are generated in accordance with the resulting count value and a coefficient correction value which is determined in accordance with the number of counts of the maximum value and the periodicity of the first and second sampling frequencies, the number of counts of the maximum value being the number of times the output clocks are counted to the maximum value. The sampling frequency of digital signals sampled at the first sampling frequency is thus converted into the second sampling frequency with a simple construction of counting to the maximum value in accordance with the periodicity of the sampling frequencies.

Abstract: A conversion method converts a first digital signal having a first sampling period to a second digital signal having a second sampling period which is different from the first sampling period. The method comprises four steps. In the first step, the first digital signal is oversampled. In the next step, the sample value of the oversampled signal maintains an identical value during a short period corresponding to a common multiple of the first sampling period and the second sampling period. In the third step, an interpolation process is carried out. Finally, the second digital signal is outputted by sampling at the second sampling period.

Abstract: A quantization device with variable digital coding rate for coding and decoding sound and speech in telecommunications and frequency transform coding. For a signal of amplitude .vertline.x.vertline. whose probability density is of the Laplace law type p(x)=.alpha./2e.sup.-.vertline.x.vertline., this device comprises a quantizer operator and a reverse quantizer operator. The quantizer operator includes an operator for calculating the ampltiude signal and a sign signal, an operator for combining the amplitude signal .vertline.x.vertline. and the number N of digital codes by subtracting a term KN=3/.alpha. Log (N+1) and a quantizer with fixed quantization thresholds in which the value of the thresholds Li is determined by the relation Li=-3/.alpha. Log (i+1). The reverse quantizer operator includes a reverse quantizer with fixed reverse quantization levels i with i=3/.alpha.

Abstract: A device for doubling or dividing by 2 the flow rate of series bits comprising a succession of first one-bit registers (R4-R0) actuated at a frequency F; a second register (R) actuated at a frequency 2F; an input terminal (IN) connected to the input of the first (R4) of the first registers and, through a first gate (T5), to an internal line (L) connected to the input of the second register; first multiplexers (M4-M1) connected to the input of each second (R3) to last (R0) of the first registers for selecting either the output of the preceding register, or the internal line, or still the output of the second register; a second multiplexer (M), which selects either the output of the last (R0) of the first registers, or the output of the second register, or filling bits; second transfer gates (T4-T0) between the output of each first register and the internal line; and means for controlling the various gates and multiplexers.

Abstract: A digital clock frequency multiplication and data serialization circuit for converting Q parallel data bits into a serial data stream is provided. A clock phase generator is coupled to receive the clock signal of the Q parallel data bits and output in response thereto Q synchronous clocks each of different phase. Logic circuitry is coupled to simultaneously receive the Q synchronous clocks and the Q parallel data bits. The Q synchronous clocks are used by the logic to gate a respective one of the Q parallel data bits such that the Q parallel data bits are sequentially output therefrom as a serial data stream. Circuits are provided for simultaneous frequency multiplication and return-to-zero data serialization and simultaneous frequency multiplication and nonreturn-to-zero data serialization. Further, digital clock frequency multiplication and synchronization circuits for converting a low frequency signal to a high frequency signal are described.

Abstract: Fractional rate modulation conversion is accomplished by separating incoming data into frames of bits. Each frame is partitioned into bit words of unequal bit lengths. The words are divided by a modulus to obtain remainders. The remainders are then multiplexed into sequential bauds of common modulus. The apparatus can be used for data compression as well as efficient modulation in bandwidth restricted channels.

Abstract: A digital filter performs a predetermined arithmetic operation on input digital data inputted thereto in time-series manner by the predetermined first sampling period to thereby generate output digital data corresponding to a second sampling frequency which is N (where N denotes an integral number) times larger than the predetermined first sampling frequency. This digital filter provides a synchronizing signal generating circuit and an operation control circuit. The synchronizing signal generating circuit detects the predetermined first sampling period of the input digital data to thereby generate a synchronizing signal having the second sampling frequency. The operation control circuit is activated by its internal clock which is asynchronous with the input digital data. This operation control circuit starts to perform its operation processes when the synchronizing signal is supplied thereto, thereafter it terminates the operation processes when a predetermined step number is completed.

Abstract: A parallel-to-serial signal converting apparatus which comprises: a logic circuit for converting first parallel bit signals of a low frequency to be converted to a high frequency serial bit signal into second parallel bit signals having the same frequency as the first parallel bit signals and having information as to whether adjacent two bits of the serial bit signal are equal in level or not; a circuit for adjusting the phase of the second parallel bit signals to form third parallel bit signals whose phases are shifted by a phase difference, successively, in an order of corresponding bits of the serial bit signal, the phase difference being substantially equal to the phase difference between adjacent two bits of the serial bit signal; and a logic circuit for logically processing the third parallel bit signals to obtain the serial bit signal. An image displaying system utilizes the parallel-to-serial signal converting apparatus.

Abstract: A universal digital code processor device (10) for the processing of scanner digital input data including bar code data is disclosed. The device is flexible and universal in nature in that it can provide inputs to both a fixed program decoder (20) for the decoding of the Universal Product Code (UPC) code as well as a programmable processor (26) which can decode UPC as well as a variety of many other bar codes. Further, the device can handle inputs from various types of scanners (11) including high-speed counter top, hand-held scanners and light pen scanners and magnetic card readers, which provide input data over a wide range of frequencies. A large number of individual frequencies are made available in the device.

Abstract: Modem receiving from/transmitting to a DTE data bits at a rate DR and adapted for operating at a modulation rate MR in an environment operating at a basic rate BR. In the receiving way, it comprises a first means for converting a number X of samples received at a frequency FS into a number X times MR/BR of samples before processing these samples by the signal processor whereby the processing results in DR/BR words of DR/MR bits, and second means for converting the DR/BR words into DR/MR words of DR/BR bits to be transmitted to the DTE. For the transmitting way the first and second converting means, are the same means but run in the reverse order. The result is that such an adapted modem behaves as a modem operating at a modulation rate MR on a periodic process interval of DR/(BR times MR) seconds.

Abstract: An encoder encodes input data into codes and outputs the codes. The numbers of bits required to represent the codes which are outputted from the encoder during respective first predetermined periods (such as periods for scanning a block of pixels) are predicted. The predicted numbers are added to derive a sum therefore. Such a sum is generated during each of a plurality of second predetermined periods (such as one-frame periods), which are longer than each of the first periods. An actual number of bits required to represent the output codes from the encoder is controlled in accordance with the derived sum. Differences between the predicted numbers of bits representing the output codes and the actual numbers of bits representing the output codes which are generated during the respective first periods are sequentially generated. The differences are accumulated into an accumulated value.

Abstract: A sampled digital filter system for filtering a signal that has a frequency lower than an unwanted signal component in the input signal. The digital filter system samples the input signal in bursts at a rate satisfying the Nyquist criterion for the unwanted signal component.

Abstract: An apparatus adaptable for use with an analog-digital-analog conversion device for effecting communications between an analog device and a digital device, the analog-digital-analog conversion device converting incoming analog signals received from the analog device to incoming digital signals, and for converting interpolated outgoing digital signals to outgoing analog signals. The apparatus has a digital signal processing circuit for decimating the incoming digital signals and providing a decimated incoming digital signal to the digital device, and for interpolating outgoing digital signals received from the digital device and providing an interpolated outgoing digital signal to the analog-digital-analog device.The digital signal processing circuit is comprised of a plurality of modules which are configured so that a specified set of the plurality of modules effects a specified number of iterations of decimation and a specified number of iterations of interpolation.

Abstract: An apparatus adaptable for use in effecting communications between an analog device and a digital device, having an analog-digital-analog circuit for converting incoming analog signals received from the analog device to incoming digital signals, and for converting interpolated outgoing digital signals to outgoing analog signals. The apparatus further has a digital signal processing circuit for decimating the incoming digital signals and providing a decimated incoming digital signal to the digital device, and for interpolating outgoing digital signals received from the digital device and providing an interpolated outgoing digital signal to the analog-digital-analog device. The analog-digital-analog device includes a single digital-to-analog converter and switches for selectively configuring the analog-digital-analog circuit to effect conversion of incoming analog signals to incoming digital signals or, alternatively, to effect conversion of interpolated outgoing digital signals to outgoing analog signals.

Abstract: A time-division bit number circuit that comprises a bit number expansion system and/or a bit number reduction system. The bit number expansion system converts an N bits signal to a 2N bits signal, while the bit number reduction system converts the 2N bits signal to the N bits signal where N is an integer. Thus, according to the time-division bit amount circuit, the number of memory can be saved, the area of circuit can be reduced and the pattern area of substrate can be reduced.

Abstract: A sample rate conversion circuit converts first digital data processed by a first clock signal having a first frequency into digital data processed by a second clock signal having a second frequency. A ring oscillator has a predetermined number of voltage-controlled gate delay elements connected to each other in the form of a loop so as to output polyphase delay clock signals and a predetermined self-excited oscillation signal. A phase-locking circuit applies a control voltage corresponding to a phase difference between the first clock signal and the self-excited oscillation signal to each of the voltage-controlled gate delay elements so as to phase-lock the first clock signal with the self-excited oscillation signal output from the ring oscillator. A latch circuit latches the polyphase delay clock signals output from the ring oscillator in accordance with the second clock signal.

Abstract: A circuit for the stable synchronization of an asynchronous data signal. The circuit comprises a first latch for receiving a first asynchronous data signal, a first delayed system clock signal, and a synchronized reset signal and for providing a system clock synchronized version of the first asynchronous data signal. A first delaying circuit receives a system clock signal and the first asynchronous data signal and provides the first delayed system clock signal. The circuit also includes a second latch for receiving a second asynchronous data signal which is a function of the inverse of the first asynchronous data signal and a second delayed system clock signal, and for providing the synchronized reset signal. A second delaying circuit receives the system clock signal and the first asynchronous data signal and provide the second delayed system clock signal.

Abstract: A converter converts time-sequential input digital data Q.sub.i having a sampling frequency f.sub.m to time-sequential digital data P.sub.j having a sampling frequency f.sub.n (f.sub.n :f.sub.m =n:m, n>m, n, m; an integer), which comprises a time axis compressing converter 6 receiving the time-sequential input digital data Q.sub.i, adding (n-m) dummy data D.sub.K every m received input data Q.sub.i and outputting the combined data at the frequency f.sub.n and a single transversal type digital filter 12 for performing filter processing on output data from the time-axis compressing converter 6 in which tap coefficient data .beta..sub.k is sandwiched at the cycle of 1/f.sub.n. The tap coefficient data is selected to nullify dummy data D.sub.K which periodically appears, based on impulse response data obtained by sampling a sampling function for the sampling frequency f.sub.m with a frequency of the least common multiple of the sampling frequencies f.sub.n and f.sub.m.

Abstract: A signal path setting circuit for a digital recorder comprising: a digital-to-analog converter hereinafter referred to as a D/A converter to convert a digital signal into an analog signal, a first switch to supply to the D/A converter a selected signal from a plurality of digital signals including a first digital signal from recording and playing back means for making a digital recording and playback through a recording medium, a second switch to supply a selected signal from a plurality of analog signals including the analog signal from the D/A converter, and an analog-to-digital converter (hereinafter referred to as an A/D converter) to convert the analog signal from the second switch into a second digital signal which is adapted to be directly or selectively supplied to the recording and playing back means.

Abstract: Apparatus and technique for ADPCM transmission of voiceband data at rates up to and including 9600 bits/s via an ADPCM system comprising an ADPCM transmitter receiving PCM encoded signals at an 8 KHz sampling rate and being operative to transmit data at a sampling rate of 6.4 KHz and a transmission rate of 5 bits per sample and an ADPCM receiver having apparatus for receiving the transmitted data from the ADPCM transmitter and being operative for providing PCM encoded signals at an 8 KHz sampling rate. The ADPCM transmitter includes an adaptive quantizer which is operative to provide an output signal I(n), employing a scale factor adapted according to a discrete function difference signal W(I) having a relationship to I(n) which typically is substantially different from that given in recommendation G.721 of the CCITT. The ADPCM transmitter also includes an adaptive predictor having predictor coefficients which are updated using a leak factor lower than that shown in recommendation G.721 of the CCITT.

Abstract: A bit pattern conversion system for converting a sequence of a bit pattern between a central processing unit and a peripheral circuit, including a data bus line connected between the central processing unit and the peripheral circuit, and a conversion circuit provided in the peripheral circuit for converting the sequence of the bit pattern from a most significant bit to a least significant bit, and vice versa, in accordance with a conversion signal.

Abstract: The described circuit arrangement for converting a data signal having a constant bit rate and code words of different length into an output signal consisting of code words of constant length but with a variable bit rate while using a buffer memory comprises a first encoder which recognizes code words of the data signal and converts them into code words of equal length, said code words being written in the buffer memory, read out from this memory by a second encoder and being converted into code words of the output signal. The construction of the first encoder is characterized in that a first EPROM and a comparator are connected to the parallel outputs of a shift register through which the data signal with its bit clock is shifted. The output data of the first EPROM and of the comparator are transferred to an intermediate memory and simultaneously applied to the address inputs of a second EPROM.

Abstract: To increase storage capacity of a disk storage device, the recording surface of the device is partitioned into a plurality of concentric recording bands, data to be recorded on respective bands are encoded using different run-length-limited codes with the code rate of each band being higher than the adjacent inner band.