Abstract: Variable sample rate converter by convolution of input data samples with an impulse response to produce output samples with the impulse response values generated by interpolation from a table of oversampled values with the oversampling rate lower for outlying lobes of the impulse response.

Abstract: A method and computer program product are provided for implementing text conversion table compression. For implementing text conversion table compression, a character sequence is loaded from a full-size conversion table. The character sequence is checked for one of plurality of character patterns. Responsive to identifying one of the plurality of character patterns, the character sequence is compressed into a compressed conversion table for the identified one character pattern. Responsive to failing to identify one of the plurality of character patterns, the character sequence is copied into the compressed conversion table. The character sequence from the full-size conversion table is checked for one of the plurality of character patterns including a repeating character sequence, a ramping character sequence, and a repeating high byte character sequence.

Abstract: Huffman encoding, particularly from a packed data format, is simplified by using two different table formats depending on code length. Huffman tables are also reduced in size thereby. Decoding is performed in reduced time by testing for the length of valid Huffman codes in a compressed data stream and using an offset corresponding to a test criterion yielding a particular test result to provide a direct index into Huffman table symbol values while greatly reducing the size of look-up tables used for such a purpose.

Abstract: An input port receives input data X, generates input packets by adding generation numbers and node numbers indicative of prescribed destinations, in the order of reception, and in addition, generates a data packet from a separately input clock signal. The input data packet is written to an image memory using the generation number in the packet as an address signal, or read from the image memory using the generation number in the data packet as an address signal. Operation is performed in accordance with the input data packet or the data packet read from the image memory by a memory interface, and the processed data packet is output to the outside of a data driven engine, a memory interface or a data driven type processor.

Abstract: A portable information equipment has a main body portion and a display portion hinged each other. A space is secured in the display portion by using a cabinet for a reflection type liquid crystal display which requires no backlight instead of a liquid crystal display with backlight. The space is used for an additional internal battery. The additional internal battery increases an electric capacity to extend an operation time of the portable information equipment and need no externally attached extension battery.

Abstract: A method and apparatus for converting sample rates of digital signals includes processing that begins by receiving an input data stream at a first sample rate. The processing continues by retrieving predetermined integrated samples at the first sampling rate, where the predetermined integrated samples are derived based on a ratio between the first sampling rate and a second sampling rate. The processing then continues by adjusting the retrieved predetermined integrated samples based on data values of the input data stream to produce adjusted integrated samples. The processing continues by differentiating the adjusted integrated samples to produce an output data stream at an output sample rate, wherein the second sample rate is a multiple of the output sample rate.

Abstract: The method and apparatus of the present invention is directed to architectures for signal processing, such as for performing analog-to-digital and digital-to-analog conversions, in which the source signal is decomposed into subband signals by an analysis filter, processed, and the processed subband signals combined to form a reconstructed signal that is representative of the source signal.

Abstract: An MRI system acquires NMR signals and digitizes them at a fixed sample rate. A lower, prescribed sample rate is obtained by fractionally decimating the sampled NMR signals. Fractional decimation is achieved by a combination of zeropadding the sampled NMR signal in the frequency domain and decimating the sampled NMR signal in the time domain.

Abstract: A coding and/or decoding system includes: a code-word table for storing therein a plurality of code words, which are capable of being decoded both in forward and backward directions and which are formed so that delimiters of the code words are capable of being identified by a predetermined weight of the code words, so that the code words correspond to different source symbols; an encoder for selecting code words corresponding to inputted source symbols from the code-word table; and a synchronization interval setting part for preparing coded data every predetermined interval using the code words selected by the encoder and for inserting stuffing codes capable of being decoded in the backward direction. Thus, it is possible to decrease useless bit patterns to enhance the coding efficiency by smaller amounts of calculation and storage, and to decode variable length codes both in the forward and backward directions even if the synchronization interval is set every interval using the stuffing bits.

Abstract: A method for converting digital data which has been sampled at a first rate to a second rate. Audio data is stored on a compact disk at high frequency and it may be desirable to use this data on a codec which has a lower sampling rate. In the situation where the two sampling rates are not integer factors of one another a method has been developed to compare the ratios of the two sampling rates and using ratio to analyze each sample number of the bitword in the original data set to determine if sampling of that particular bitword is necessary.

Abstract: A sample rate conversion system converts data of a first sample rate to data of a different second sample rate. The system involves an interpolator, operating at the first sample rate and includes a first interpolation network and a delay network. The first interpolation network interpolates the first sample rate data to provide upsampled interpolated data samples according to a first sample spacing. The delay network interpolates the upsampled interpolated data to provide delayed upsampled interpolated data samples, according to a second sample spacing of higher resolution than the first sample spacing, and preceding and succeeding an original sample position. The system also includes a digital filter operating at the second sample rate for filtering the higher resolution data samples to provide the second sample rate data.

Abstract: An input port receives input data X, generates input packets by adding generation numbers and node numbers indicative of prescribed destinations, in the order of reception, and in addition, generates a data packet from a separately input clock signal. The input data packet is written to an image memory using the generation number in the packet as an address signal, or read from the image memory using the generation number in the data packet as an address signal. Operation is performed in accordance with the input data packet or the data packet read from the image memory by a memory interface, and the processed data packet is output to the outside of a data driven engine, a memory interface or a data driven type processor.

Abstract: A delta-sigma modulator comprises a 1-bit quantizer located for quantizing an analog signal applied thereto, and for outputting a first quantized digital signal, a 1-bit DA converter converting the first quantized digital signal into a quantized analog signal, a subtracting circuit for subtracting the quantized analog signal output from the 1-bit DA converter from the analog signal input to the 1-bit quantizer, and an input integrating circuit series including a series of one or more stages each of which includes a subtracter and an integrator for integrating an output of the subtracter, one subtracter at a first stage subtracting the quantized analog signal delayed by a delay element from an input analog signal input to the delta-sigma modulator, and one integrator at a final stage outputting its output to the 1-bit quantizer. A multiple-bit quantizer quantizes an analog output of the subtracting circuit and outputs a second quantized digital signal.

Abstract: Encoding and decoding systems and methods for digital data in 24 bit sequences. An encoder generates state variables as a function of four or fewer bits of the 24 bit sequence, and encodes the sequence into 11 and 14 bit codewords. After transmission, the 11 bit and 14 bit codewords are decoded using recovered state variables. The encoding places a run length limit (RLL) of k=7 on a 25 bit codeword comprised of the 11 and 14 bit codewords to limit runs of zeros. Each of the 11 bit and 14 bit codewords are preferably also encoded with a run length limit of interleaved bits is i=7. The encoding and decoding systems and methods can be applied to a magnetic disc drive.

Abstract: A data conversion apparatus for converting first data into second data. An input section receives the first data. A conversion section converts the first data into the second data by moving each of the first data to the position of second positional information that is represented by a sequence of numbers that is obtained by reversing the order of a sequence of numbers of first positional information that is an N-ary number (N: a natural number that is greater than or equal to 2) and represents the position of each of the first data. The data conversion apparatus can easily distribute data existing in a temporally or spatially localized region.

Abstract: An audio codec having an encoder and a decoder is disclosed. The encoder enables the compression of an audio signal for transmission or storage while the decoder receives a compressed audio signal for playback. A time scaling module within the decoder allows variation of the playback rate of the compressed audio signal. Further, no significant depreciation in the quality of pitch occurs as a result of varying the playback rate. The codec features a control for independently varying the playback rate and a module for delivering pitch compensation. The encoder utilizes a sub-band coding scheme (e.g., MPEG-1 and MPEG-2) wherein an audio signal is split into at least two frequency sub-bands for compression. Using a filter bank having two filters, for example, the audio signal is split into the frequency sub-bands. An decoder having a time scaling module is further disclosed. The time scaling module time stretches or compresses an audio signal as desired using a synchronized overlap and add (SOLA) algorithm.

Abstract: A method and apparatus encoding and decoding data for storage on a mass storage device is described. The code used is a 5/6 rate code in which a maximum transition run constraint is imposed. This code is designed for use with an EEPR4 read channel and provides a Euclidian squared free distance, d2free, of 10 when used with an EEPR4 partial response filter and a Viterbi decoder.

Abstract: An optical rotating recording medium in which a 17-bit codeword is recorded converted from a 16 bit data, wherein (i) a 16-bit data word is coded to a 17-bit codeword set with restrictive conditions on a minimum number (d) of consecutive zeros, a maximum number (k) of consecutive zeros, and a maximum number (r) of consecutive “1”s in the codeword; (ii) a “1” in a codeword is converted to an inversion of “1” and “0” in recording data and a “0” in a codeword to non-inversion by non-return to zero inverse (NRZI), and (iii) a “1” and “0” in the recording data are stored linked with one of the existence of a bit on the optical rotating recording medium and two polarities of magnetization and a data recording method, a recording apparatus, and a reproducing apparatus relating to the same.

Abstract: An analog signal, for example in a sound recording process, is converted into an input series of digital signals and is then encoded using a special differential encoding scheme. The scheme involves generating two series of signals, one series corresponding to some of the terms of the input signals, while other terms of the input series are excluded. For example the first series may include every second term of the input series. The second series includes terms corresponding to a difference between at least two terms of the input series, at least one of which is not included in the first series. Preferably the two terms of the input series defining a term of the second series are sequential or at most separated by one other term. The two series can be combined and can be either transmitted to a receiver or recorded on a medium. A high quality output is then obtained by reconstructing the input series from the two series.

Abstract: A mixer (200, 201) including a transformation circuit (210) is used for frequency converting a first digital signal (208), sampled at a first sampling rate and operating at a first frequency, to a second digital signal (214) operating at a desired frequency. The transformation circuit (210) is adapted to modify and filter the first digital signal (208) to eliminate unwanted frequencies in the first digital signal (208) and to alter the first sampling rate of the first digital signal (208) by a predetermined factor to generate a modified and filtered first digital signal (308) operating at a second sampling rate and the first frequency. The transformation circuit (210) is further adapted to mix the modified and filtered first digital signal (308) with a predetermined injection signal (312) to generate the second digital signal (214) operating at the desired frequency and the second sampling rate.

Abstract: Methods and circuits for the generation and application of sample rate conversion ratios using distributed jitter. In some applications, it is not possible to represent the required sample rate conversion ratio with an exact fractional binary ratio having a denominator that is a power of two. When this occurs, a fractional binary ratio is selected that approximates the required conversion ratio. The residual phase error resulting from the use of the selected fractional binary ratio is then computed and compensated for by adding a predetermined amount of “jitter.” The jitter can be distributed periodically, uniformly, or randomly over each repetition period, the period between which the input and output clock pattern repeats.

Abstract: Adaptive coding method and apparatus in which the speed at which the coder transitions between different codes to perform bit generation is adapted, or adjusted, while coding the data to arrive at a point where the initial bits of the outputs include zeros and ones occurring equally often.

Abstract: Asynchronous sample rate conversion is performed using a noise-shaped numerically controlled oscillator (204,420) that generates a clock (207,428) that is synchronous to the system clock (217,424) but having a time average frequency that is equal to a multiple (X) of the asynchronous sample rate frequency required for the conversion. Unwanted spectral energy in the generated clock (207,428) is noise-shaped out of the pass-band and so does not degrade signal performance. For digital-to-analog conversion, the generated clock (207) is used to time an interpolation (206) of digital data (DATAFs) by an multiple X to produce an interpolated signal (DATAFsX) having a time average rate equal to the over-sampling frequency but being synchronized with the system clock (217). The interpolated signal (DATAFsX) is then converted (216) to an analog signal using a derivative of the system clock (217), or can be output as digital data at the rate derived from the system clock.

Abstract: The invention relates to a method and apparatus for achieving maximal coding gain for audio transmission. More particularly, at a chosen sample rate and frequency range value, an audio input signal is downsampled to the sample rate, encoded and transmitted at a given bit rate. At the receiving end, the downsampled signal is decoded and upsampled to the original or other suitable sample rate. The upsampled signal is then audibly output. Since resampling ratios using “small” numbers prove to be more computationally efficient, this method and apparatus supports resampling ratios which imply both standard and non-standard sampling ratios in the coded.

Abstract: An asynchronous sample rate converter for converting a first sample rate in a signal to a second sample rate in the same signal is presented. The signal is first provided as input to an interpolator which upsamples the signal to form a signal having sample rate UFs1 where the upsampling factor U is a variable that is directly related to the ratio Fs2/Fs1. The resampler then linearly interpolates the upsampled signal to form a signal having sample rate DFs2. Finally, the resampled signal is downsampled to form a signal having sample rate Fs2.

Abstract: A general rate N/(N+1) (0, G), code construction, e.g., for a magnetic recording system, allows for encoding or decoding of a dataword having N elements, N preferably being an integer multiple of eight. The dataword is divided into N/8 bytes of binary data that are encoded as a run-length limited (RLL) codeword in accordance with the general rate N/(N+1) (0, G) code construction. The general rate N/(N+1) (0, G) code construction is characterized by the constraints (d=0, G=(N/4)+1, l=N/8, r=N/8). the N/(N+1) (0 (N/4)+1, N/8, N/8) RLL codeword is constructed from the dataword in accordance with 1) pivot bits identifying code violations related to the constraints, 2) correction bits set to correct code violations, and 3) preserved elements having values not included in the code violations.

Abstract: A program controlled integrated circuit having an input path for receiving an analog signal with given attributes and using a program controlled sequence of treatment stages to generate a bit-defined information vector. That vector is introduced to a distributed memory matching array where it is compared with conveyed instruction set having bit-defned codewords corresponding with an analog signal attribute. A match process under the control of a central control unit then develops a digital result. The digital result may be utilized or converted to analog form in an analog return path. Both the input path and the return path incorporate a reduced instruction set computing arithmetic unit under the control of the central control unit.

Abstract: For a system having multiple sources of digital input data to be converted to analog by Digital to Analog Converters (DACs), pre-processing of the multiple sources of data is provided, such that differences in input sampling rates are accommodated. When multiple digital input sources are to be converted to analog signals in a single integrated circuit, these input signals are routed to a clock generator having Phase Locked Loop (PLL) circuitry and to respective Asynchronous Sample Rate Converters (ASRCs). Sample rate information relating to an input signal selected from among the multiple input signals is determined during a locking operation of the PLL. Based on the common clock output from the clock generator, the ASRCs convert the input signals to a single sampling rate. Once the multiple input sources are converted to a common sample rate by the ASRCs, the inputs are converted to analog signals by DACs using the common clock and are output by the single Integrated Circuit.

Abstract: A method and means for reducing high-duty-cycle unconstrained binary signal sequences in storage and communications processes and systems by invertibly mapping such sequences into a (1, k) rate ⅔ RLL codestream constrained to a duty cycle substantially approximating one-third. That is, binary sequences ordinarily mapping into high-duty-cycle RLL-code sequences are either inhibited from repeating indefinitely or excluded.

Abstract: An internally triggered equivalent-time sampling system characterizes high-speed data signals having a predetermined nominal data rate by using an internal oscillator that runs independent of a synchronous trigger signal. The sampling system acquires samples of the data signal at a strobe rate, set by the oscillator, which is lower than the nominal data rate of the data signal. The samples, the strobe rate, and the nominal data rate are communicated to a quality optimizer which compensates for static rate deviations between the nominal data rate and the actual data rate of the data signal to establish timing correspondence between the acquired samples. The timing correspondence establishes the time placement of the acquired samples when characterizing the data signal on a display or other output device. When the oscillator has high timing stability relative to the data signal, jitter and other attributes of the data signal are accurately characterized.

Abstract: The invention dynamically compensates for differences in data rates for multistreamed systems. Any or all of the streams in a multistreamed system may be individually compensated at one time. In one embodiment, the status of an input buffer is monitored and used to change the number of oversamples within a frame of one of the number of streams. In another embodiment, a high frequency clock in the system is used to stall one of the streams for one or more clock cycles. In both ways, distortion due to differences in data rates is reduced.

Abstract: An interpolation digital filter for an audio CODEC uses a bit serial method for an audio CODEC system with a clock signal of 256 FS. The interpolation digital filter converts a 32-bits data signal of sampling frequency of 1 FS to a 32-bit data signal of the sampling frequency of 8 FS using a clock signal of 256 FS in a filter unit. Therefore, the present invention reduces the size of the system and reduces the cost.

Abstract: A frequency counter detects a sampling frequency of an input digital signal. If a control circuit is notified that the sampling frequency of the input digital signal changes according to a signal from the frequency counter, it temporarily stops accumulation of input digital signal in a data memory. An operation processing circuit continues operation processing on the input digital signal accumulated in the data memory at that time. After the operation processing terminates, the control circuit reads a program and processing data corresponding to the changed sampling frequency from a program memory and a coefficient/offset data memory and sets them in the operation processing circuit. After that, the operation processing circuit restarts operation processing.

Abstract: A filter combination for sampling rate conversion is disclosed comprising a series combination of: an input low-pass filter (1) whose attenuation characteristic (tp1) has at least one first attenuation value (a1) in the vicinity of one-half and 1.5 times the frequency of a digitization clock (f1); a time-invariant interpolation filter (2) for increasing the number of samples from that of the first data sequence (d1) by an integral factor whose attenuation characteristic (tp2) has at least one second attenuation value (a2) in the vicinity of the frequency of the digitization clock (f1) and essentially at least one third attenuation value (a3) in the region between one-half and 1.

Abstract: A multichannel polyphase filter (304, 602) includes a processing system (204, 506) for accepting and processing M input channels of data, each sampled at an input sampling rate, wherein M is a positive integer greater than unity. The processing system is programmed to provide a commutator (308, 606) for the multichannel polyphase filter, wherein the position of the commutator is decoupled from the phase of a filter impulse response selected for the position, thereby allowing the multichannel polyphase filter to be operated at a sampling rate that is a non-integer multiple of the input sampling rate. The processing system is further programmed to operate the multichannel polyphase filter at the non-integer multiple of the input sampling rate to obtain a non-integer sampling rate change.

Abstract: A system for controlling the frequency of a bit synchronizing clock signal used for reproducing an EFM signal, comprises an EFM signal frame period detecting circuit for frequency-dividing an EFM signal by 117 to output a 1/117 frequency-divided signal as a frame period signal. A control unit counts the level transition interval of the EFM signal by the bit synchronizing clock signal, selects a maximum count value in a detecting duration defined by each frame period signal, and compares the maximum count value with a predetermined value corresponding to the bit length of a frame synchronizing signal included in the EFM signal.

Abstract: A coding and/or decoding system includes: a code-word table for storing therein a plurality of code words, which are capable of being decoded both in forward and backward directions and which are formed so that delimiters of the code words are capable of being identified by a predetermined weight of the code words, so that the code words correspond to different source symbols; an encoder for selecting code words corresponding to inputted source symbols from the code-word table; and a synchronization interval setting part for preparing coded data every predetermined interval using the code words selected by the encoder and for inserting stuffing codes capable of being decoded in the backward direction. Thus, it is possible to decrease useless bit patterns to enhance the coding efficiency by smaller amounts of calculation and storage, and to decode variable length codes both in the forward and backward directions even if the synchronization interval is set every interval using the stuffing bits.

Abstract: A digital signal averager for averaging data collected by an analog detector is provided. The digital signal averager includes an analog-to-digital converter for converting the analog detector output to a digital signal for processing, a timing device for generating delayed timing pulses for sequencing operation of the digital signal averager, an averaging device for summing and storing data. The delayed timing pulses allow data to be acquired by the ADC at a series of variably offset timing sequences relative to a trigger pulse. Offsetting the data acquisition timing sequences by time slices smaller than the actual sample rate of the ADC allows data to be acquired at a higher effective sampling rate. One complete series of offset timing sequences provides a data set containing all the information which would be acquired by a ADC having a faster sampling rate.

Abstract: The present invention comprises a sample rate conversion system for eliminating sample rate slippage. The system of the present invention includes a first sample rate conversion circuit and a second sample rate conversion circuit. The first sample rate conversion circuit is adapted to multiply a sample rate frequency by a factor "N", producing a first converted sample rate frequency. The a second sample rate conversion circuit is adapted to divide the first converted sample rate frequency by a factor of "M", producing a second converted sample rate frequency. The sample rate frequency is used to encode an input signal, producing an encoded signal. The second converted sample rate frequency is used to decode the encoded signal, producing an output signal. The second converted sample rate frequency and the values of N and M are adjusted such that the input signal is substantially the same as the output signal, eliminating sample rate slippage.

Abstract: An oversampled analog-to-digital converter (ADC) (20) includes a sigma-delta modulator (21) with two decimation filters to provide minimum power consumption. The first decimation filter (30) converts the output of the sigma-delta modulator (21) to a slower intermediate frequency and performs a first part of the decimation function. The second decimation filter (40) converts the output of the first decimation filter (30) to the output frequency and performs a second part of the decimation function. The ADC (20) saves power by allowing some of the second part of the decimation function to be performed at the slower intermediate frequency. In one form, the first decimation filter (30) includes a finite impulse response (FIR) filter (32) and a down sampler (34). By using a suitable logic circuit (56), the FIR filter (32) can be implemented with only a small amount of circuit area and most of the FIR filter (32) can be operated at the slower intermediate frequency.

Abstract: An apparatus for sensing RF current delivered to a plasma includes an RF conductor along which the current is delivered to the plasma and which is divided into two parts along part of its length so that substantially equal currents flow in each part. A sensor device is inserted into the gap between the two parts of the conductor and includes first and second inductive loops disposed one n each side of the gap such that when an RF current flows along the RF conductor t magnetic flux surrounding the conductor which is generated by the RF current couples with the loops respectively in opposite directions relative to the sensor device. If a stray magnetic flux normal to the current direction couples with the loops in the same direction relative to the sensor device it will induce voltages in the loops which respectively add to the voltage induced by the RF current in one loop and subtract from the voltage induced by the RF current in the other loop.

Abstract: A communication system includes a data sampling rate converter that uses a closed-loop control arrangement to convert an input signal at a first sampling rate to a second, asynchronous, sampling rate without requiring extensive input buffering. A number of data registers in a first-in-first-out input buffer are used to receive and store data samples at the first rate and to pass the data samples from the input buffer at a controlled rate. The input buffer indicates the current capacity of the input buffer circuit for use by a frequency ratio estimation circuit, which is arranged to respond by providing an estimate of the actual ratio between the first rate and the second rate. A control circuit responds to the frequency ratio estimation circuit by generating the controlled rate at which the data samples are to be passed from the input buffer. In this manner, the data samples are passed from the input buffer at the controlled rate for processing and outputting the data at the second rate.

Abstract: A method and apparatus in a radio telecommunications system for converting data from a first sample rate to a second sample rate such that the first and second sample rates are preferably within 10% of each other are disclosed. An input buffer receives a plurality of data groupings at a first sample rate. A spline filter utilizes the input data along with a phase difference between input and output data to calculate a third order spline function and an output time for the input data. This information is used to convert the input data at the first sample rate to output data at a second sample rate. The output data is buffered within an output buffer until transmitted to an associated base band unit.

Abstract: A method and apparatus wherein raw video and audio are captured and digitized and stored at a frame rate different from the playback stand frame rate. The audio and the video are separated, the video as a frame and the audio as a data stream wherein there are time links to the video frame. The playback entails multiplexing the video and the audio, and where the multiplexer is operating at the standard frame rate synchronization is not maintained. The present invention discloses modifications of the audio header and/or data to accommodate the differences in the multiplexing frame rate and the original capture frame rate. If the originating frame rate is one half the standard then the audio header information is changed to indicate that twice as much audio information exists, whereupon the multiplexer will take the video frames and properly multiplex the proper and therefore synchronized audio data.

Abstract: A sample-rate converter has a FIFO for buffering input samples. The FIFO is written with an input sample by an input clock synchronized to the input audio stream. The samples are read from the FIFO by a derived clock. The derived clock is generated from an output clock using a nominal ratio of Q/P. Read and write counters for the FIFO are compared. When the write counter is ahead of the read counter by exactly a target amount the derived clock is a ratio of Q/P of the output clock. When the write counter is ahead of the read counter by more than the target, the read rate is increased by accelerating the derived clock to a ratio of (Q+1)/P. When the write counter is ahead of the read counter by less than the target amount, the read rate is decreased by slowing the derived clock to a ratio of (Q-1)/P. An accumulator generates the derived clock by adding Q, Q+1, or Q-1 for each output-clock pulse. Each derived-clock pulse reduces the accumulator by P.

Abstract: A symbol timing recovery circuit in a digital demodulator is disclosed. The symbol timing recovery circuit comprises means for generating a clock signal in a predetermined period, means for sampling a received signal according to the clock signal, an interpolator for interpolating the output signal from the sampling means according to a filter tap coefficients calculated by a fractional interval at each sampling period to obtain an interpolant, a data filter for filtering the interpolant and providing the filtered interpolants as a strobe data, a timing error detector for detecting a timing error from the strobe data to generate a timing error signal, a loop filter for filtering the timing error signal to obtain and provide a mean timing error signal; and a controller for providing the fractional interval and controlling the signal processing operation of the data filter, timing error detector, and loop filter according to the mean timing error signal.

Abstract: A comb filter has series connected integrators to which is fed a digital data stream at a high sampling rate in order to yield a digital data stream at a low sampling rate. The most significant bits of the digital data stream are reset in the first and second integrators, the resetting of the bits in the first integrator being stored in a counter. The counter reading of the counter is fed into the most significant bits of the last integrator at a reset time.

Abstract: A communication system includes a data sampling rate converter that uses a closed-loop control arrangement to convert an input signal at a first sampling rate to a second, asynchronous, sampling rate without requiring extensive output buffering. A small number of data registers in a first-in-first-out output buffer is used to receive and store computed data samples at a controlled rate and to pass these data samples to the output at a second rate. The output buffer indicates, the current capacity of the output buffer for use by a frequency ratio estimator, which is arranged to respond by providing an estimate of the actual ratio between the first rate and the second rate. A controller responds to the frequency ratio estimator by generating the controlled rate at which the computed data samples are to be passed to the output buffer. In this manner, the processed data samples are passed to the output buffer at the controlled rate and are output at the second rate.

Abstract: A sampling frequency converting device. A memory unit stores an input signal D.sub.si having an input sampling frequency Fsi. An interpolation unit interpolates the readout signal from the storage unit. A sampling frequency ratio detection unit detects the current sampling frequency ratio R.sub.n between the input sampling frequency Fsi and the output sampling frequency F.sub.so and detects a new sampling frequency ratio R.sub.n NEW. based on the current sampling frequency ratio R.sub.n and a past detected value R.sub.n-1 preceding the current detected value by one detection period. A control unit having the sampling frequency detection unit controls the storage unit and the interpolating unit from the new sampling frequency ratio R.sub.n NEW.

Abstract: A transfer clock converter for digital data of the present invention is a circuit for converting digital data synchronized with a first transfer clock into digital data synchronized with a second transfer clock and outputting the digital data, and includes a plurality of latching elements and a comparator-selector circuit. The comparator-selector circuit compares the output data from predetermined latching elements, selects output data to be output according to the result of the comparison, and outputs the selected output data. With this structure, it is possible to always output correct digital data without using a PLL circuit or the like, thereby significantly improving the reliability.