Abstract: Analogue to digital (A/D) and digital to analogue (D/A) converters perform the required conversion at a higher sampling rate (e.g. 64Fs) and a lower resolution (e.g. 1 to 4 bits) than the actual sampling rate (Fs) and resolution (e.g. 16 bits) of the required digital signal. The oversampled low resolution signal is generated by oversampling the input digital signal (for D/A conversion) or is decimated to generate the required output digital signal (for A/D conversion). The oversampling or decimation filters are switchable between two modes of operation, in which different signal delays are imposed by the filter. Thus a lower quality, but shorter delay, filter can be used in converters in the signal path for an artist's foldback signal. This can reduce the subjectively disturbing effects of long conversion delays in the foldback signal path.

Abstract: In a digital information modulating apparatus, first information signal is separated every m bit or bits, and n bit or bits are added to the head of every m bit or bits to change every m bit or bits of the first information signal into every m+n bits of a second information signal, where "m" and "n" denote predetermined natural numbers. The second information is pre-coded into plural pre-coded information signals in accordance with combinations of the added n bit or bits. A determination is made as to whether or not predetermined sync information is present in the pre-coded information signals. A sync detection signal is generated which represents the result of the determination. One of the pre-coded information signals is selected as a modulation-resultant output signal in response to the sync detection signal.

Abstract: A filtering technique that results in improved performance of interpolating filters. The improved filter and technique replicates samples of the digital input signal instead of inserting zeroes before smoothing to eliminate undesired images of the sampled input signal. The filter includes a digital equivalent of a sample and hold for sampling the digital input signal at the input sample rate and for replicating the sampled digital input signal a predetermined number of times to increase the sample rate by an integer multiple and produce replicated samples of the input signal. A smoothing filter is coupled to the digital sample and hold for smoothing the replicated samples. The smoothing filter has a shape having a high frequency enhancement followed by a sharp cutoff that compensates for the replicated samples of the input signal. Interpolated digital output signals are provided therefrom that are at a sample rate higher than the input sample rate.

Abstract: Picture coded data that are obtained by coding at a coding rate R1 that is input via a coded data input terminal 1 are supplied to a variable length decoder. The variable length decoder decodes data for which variable length coding has been performed, and DCT coding information is transmitted to an inverse quantizer. A quantization controller calculates a quantization step that is necessary for re-quantization, and controls a quantizer. The DCT coding information for which the inverse quantization has been performed by the inverse quantizer is recovered into a DCT coefficient. The DCT coefficient is quantized again by a quantizer at quantization step Q that is determined by the quantization controller, and the result is transmitted to a variable length coder. The variable length coder performs variable length coding of the received data at a coding rate R2, and outputs the resultant picture coded data to a coded data output terminal.

Abstract: A method and system for dynamically converting audio data into a standard format. The method and system also provides for using a directory hierarchy to specify a fidelity level and dynamically generating the audio data at the specified fidelity level. When a drive is loaded with, for example, a CD ROM containing raw audio data, the system generates a directory hierarchy for the drive. The directory hierarchy contains sub-directories corresponding to various fidelity characteristics. For example, the system may generate a sub-directory corresponding to audio data stored in stereo format and another sub-directory corresponding to audio data stored in mono format. The system also generates a file entry in sub-directories for each track of the CD ROM. For example, the stereo sub-directory may contain a file entry for track 1 of the CD ROM and the mono sub-directory also may contain a file entry for track 1.

Abstract: A codec apparatus is for converting an analog signal to a digital signal, and for decoding the digital signal to an analog signal. The codec apparatus includes a detection device for discriminating a frequency bandwidth of the analog signal, and a changing device for changing a sampling frequency of the digital signal based upon a signal from the detection device. The sampling frequency of a digital signal can be changed according to a frequency bandwidth of an analog signal. This arrangement can prevent the sampling frequency from being set excessively high.

Abstract: A data conversion circuit that acts as an interface between components or systems having different data input/output rate requirements. A circuit reads data transmitted at one bit rate and transmits data consisting of the input data along with overhead data interleaved with the input data in a fixed pattern at a faster bit rate. Also disclosed is a circuit that operates to read data at a faster bit rate and transmit data consisting of the input data stripped of interleaved overhead data at a slower bit rate. Data is written into and read from a register array that allows data to be concurrently and independently written and read. A suitable delay is introduced on the output side in order to avoid read/write collisions in the register array and achieve a minimum transmission delay.

Abstract: On converting an input data signal having a first transmission rate into an output data signal having a second transmission rate different from the first transmission rate, the input data signal is memorized as a memorized input data signal a first memory. A read clock generating circuit generates a read clock signal to read the memorized input data signal as a read data signal out of the first memory. A read control circuit controls the read clock generating circuit to stop generation of the read clock signal in order to make the read data signal have an overhead bit slot at a predetermined period. A rate control circuit produces a rate control signal having a predetermined pattern and an inhibit signal in accordance with the rate control signal. The read clock generating circuit stops generation of the read clock signal in response to the inhibit signal. A multiplexing circuit multiplexes an information signal to the read data signal on the basis of the rate control signal to produce the output data signal.

Abstract: A digital-to-digital sample rate converter for converting digital input signals x(n) having a first sample rate F into digital output signals y(m) having a second sample rate F.multidot.L/M, wherein L/M is an arbitrary rational fraction. The digital lowpass filter needed for sample rate conversion has a piecewise continuous linear hull curve. This allows an efficient and low-cost hardware solution, since only one multiplier is needed for the digital-to-digital sample rate converter.

Abstract: In a signal compressing and encoding apparatus, a plurality of A/D converters sample input audio signals synchronously to produce time sample sequences. An audio encoding circuit transforms the time sample sequences in time/frequency by a frame interval to produce frequency sample sequences. The frequency sample sequences are compressed, encoded and formatted into a frame structure to generate audio bit streams. The audio bit streams are multiplexed by a formatter into a multiplexed bit stream. On the other hand, in a compressed signal decoding circuit, a quantization decoder decodes the frequency sample sequences for each bit stream separated and extracted selectively out of the multiplexed bit stream. Adding the result the decoded frequency sample sequences produces a summing result. The summing result is then transformed in frequency/time by a frequency/time mapping to produce the original time sample sequences.

Abstract: A sampling frequency converting device. A memory unit stores an input signal D.sub.si having an input sampling frequency F.sub.si. An interpolation unit interpolates the readout signal from the storage unit. A sampling frequency ratio detection unit detects the current sampling frequency ratio R.sub.n between the input sampling frequency F.sub.si and the output sampling frequency F.sub.so and detects a new sampling frequency ratio R.sub.n NEW. based on the current sampling frequency ratio R.sub.n and a past detected value R.sub.n-1 preceding the current detected value by one detection period. A control unit having the sampling frequency detection unit controls the storage unit and the interpolating unit from the new sampling frequency ratio R.sub.n NEW.

Abstract: A digital receiver includes a tuner and a demodulator that obtains a modulated signal carried in a received analog signal. A digital-to-analog converter operates at a preselected fixed sampling rate on the modulated signal to produce a first sequence of digitized samples. The first sequence of digitized samples is processed by a digital rotator to frequency-and phase-correct the first sequence of digitized samples. A controllable digital filter processes the first sequence to produce a filter output including a second sequence of digitized samples at a symbol rate. The second sequence is processed to ascertain a symbol rate of the modulated signal. The controllable filter coefficients are automatically varied to accommodate changes in the symbol rate of the modulated signal, so that the sampling rate of the digital-to-analog converter need not change.

Abstract: A filter selector generates a filter address value to select one of a number of frequency characteristics of a filter to resample a first data signal from a first segment of data in order to generate second sampled data signal in a second segment of data. The filter selector includes an adder which adds a resampling factor to a previous address value to generate a current address value if the previous address value is less than a comparator value and which subtracts the comparator value from the previous address value to generate the current address value if the previous address value is greater than or equal to the comparator value. The current address value is shifted by n bits, where n is an integer, to generate the filter address value.

Abstract: A method and device for transcoding a digital signal first oversamples the input signal, converts the sampling rate to an oversampled output signal, filters the signal to reduce unwanted bands and decimates the oversampled output signal to produce a transcoded signal having the target sampling rate. This allows the conversion to be implemented in the composite domain, requiring a single sampling rate converter, and significantly reduces the complexity of the filter required to filter the output signal.

Abstract: A D/A converter (10) converts a digitized analog signal (32) to an analog signal (50). The D/A converter (10) includes first filtering stage (12), second filtering stage (14), and reduced-bit D/A converter (16). The first filtering stage (12) operates at a first sampling rate (25), interpolates the digitized analog signal (32) from an initial sampling rate to a first sampling rate (25), performs an anti-alias filter, and performs a first comb filtering function. The second filtering stage (14) operates at a second sampling rate (46), interpolates the digitized analog signal (32) to the second sampling rate (46), performs a second comb filtering function, and performs a noise shaper filter to produce a reduced-bit second sampling rate signal (48). The reduced-bit D/A converter (16) converts the second sampling rate signal (48) to an analog signal (50).

Abstract: A rate converter for digitally converting the sample rate of a signal, has a first digital filter for deriving an intermediate signal at increased sample rate and a second digital filter for deriving an output signal at a decreased sample rate relative to that of the intermediate signal. The first filter is of relatively high order serving to double the frequency. Because the frequency change is a power of two, the aperture characteristic is straightforward and implementation is simple even at high order. The second filter is of relatively low order so that implementation is simple even with a time-varying aperture characteristic. The low order of the second filter does not however degrade the overall frequency characteristic.

Abstract: The present invention is a method of processing digitized signal samples generated by a free running analog-to-digital converter and sampled at a first sample rate. The method includes the steps of convolving the digitized signal samples with a single-stage digital filter and generating a series of resampled signal samples having a second sample rate no greater than the first sample rate. The resampled signal samples are synchronized with a predetermined time reference during the step of generating the series of resampled signal samples.The present invention is also an apparatus for recording seismic surveys.

Abstract: A method and apparatus for digital-to-analog conversion using sigma-delta modulation of the temporal spacing between digital samples are provided. The method and apparatus include sigma-delta modulation of the time-base such that errors produced by non-uniform sampling are frequency-shaped to a high frequency region where they are reduced by conventional filtering techniques. In one embodiment, an oversampling modulator receives digital input samples and, responsive to a noise-shaped clock signal, modulates the digital input samples to produce modulated samples at an oversampling rate. The oversampling rate preferably is equal to an oversampling ratio times a preselected input sample rate. A DAC, coupled to the modulator, converts the modulated samples to an analog signal.

Abstract: An electronic device for the automatic conversion of sampling frequencies, being a type adapted to convert a predetermined frequency of a sampled input signal to a desired frequency of an output signal. The device is comprised of:a phase detector being input both the input frequency and the output frequency; a decoder block associated with the detector to determine an interpolation coefficient; an interpolation filter having a digital input for encoding the sampling signal and receiving the input frequency on the one side, and a digital signal representative of the interpolation coefficient on the other side; and a synchronizer connected after the filter and being input both said input and output frequencies, the synchronizer having a digital output for encoding the converted sampling signal.

Abstract: A sample rate converter includes a first interpolator which generates samples intermediate samples provided at a first sample rate. A second interpolator, using the intermediate samples, generates further samples at a second sample rate which are intermediate the intermediate samples. An accumulator which accumulates a value representing the ratio of the first and second sample rates, generates scale factors for performing the interpolations, and a clock signal at the second sample rate.

Abstract: A sampler develops a digital representation of an analog signal at a predetermined sampling rate. The highest frequency of a period of samples is determined and, if sampling rate of the sampler exceeds the Nyquist rate, indicating oversampling, redundant sample points are discarded from the period and the reduced record is stored. A multiplicity of periods make up a recorded session. To reconstruct the original signal, a common time domain is determined and the reduced records are expanded based upon the common time domain.

Abstract: A method apparatus for encoding segments having a selected number of ordered bits of binary data from a sequence of ordered bits of binary data into corresponding codewords having a selected number of ordered bits of binary data, such that the sequence of ordered bits of binary data is encoded into a sequence of codewords. The apparatus comprises a receiver device for receiving the segments; a separating device for separating the selected number of ordered bits of binary data of each segment into a corresponding first group and a corresponding second group; an encoder mapping device for mapping each first group into a corresponding word having a selected number of ordered bits of binary data; and an interleaving device for interleaving the bits of each corresponding second group with the selected number of ordered bits of binary data of each corresponding word to obtain the corresponding codewords.

Abstract: A digital recorder which includes an A/D converter for converting analog signal to digital form for recording and a D/A converter for converting recovered recorded digital information to analog form, includes switch circuitry for interconnecting the D/A converter and the A/D converter in a manner to perform sample rate conversion of input digital signals to condition the recorder to record digital signals having different sample rates.

Abstract: A rate converter for converting data rate is adapted to hold, at an output clock rate, by using a plurality of latch circuits, respective signals from the output stages of a shift register operative at an input clock rate to multiply, at the output clock rate by using a plurality of multipliers, held signals from the latch circuits by filter coefficients that a plurality of coefficient generators sequentially generate to add the multiplied outputs by using an adder to provide a rate converted output signal. Thus, this rate converter makes it possible to carry out rate conversion by a single digital filter without necessity of digital filters operative at a clock rate of the least common multiple of the input clock rate and the output clock rate.

Abstract: A method and apparatus for digital-to-analog conversion using sigma-delta modulation of the temporal spacing between digital samples are provided. The method and apparatus include sigma-delta modulation of the time-base such that errors produced by non-uniform sampling are frequency-shaped to a high frequency region where they are reduced by conventional filtering techniques. In one embodiment, an oversampling modulator receives digital input samples and, responsive to a noise-shaped clock signal, modulates the digital input samples to produce modulated samples at an oversampling rate. The oversampling rate preferably is equal to an oversampling ratio times a preselected input sample rate. A DAC, coupled to the modulator, converts the modulated samples to an analog signal.

Abstract: A digital resampling system is provided for converting a first digital signal to a second digital signal, where both signals represent the same analog signal but sampled at two different clock rates which are not phase-locked together. A filter is clocked by the first clock and outputs filtered samples at the first clock rate, optionally omitting samples which will not be used. A phase indicator determines the relative phase position of the first and second clocks and indicates an integer phase value and a fractional phase value which together indicate where a tick of the second clock falls among the ticks of the first clock. The integer phase value identifies a clock cycle of the first clock in which a tick of the second clock occurs, and the fractional phase value represents a fraction identifying a position of the tick of the second clock within the clock cycle of the first clock. A sample selector selects M filtered samples from those provided by the non-decimating filter based on the integer phase value.

Abstract: Method and apparatus for digital sample rate conversion. A mixed signal tester employing digital sample rate conversion is also disclosed. According to the invention, variable phase jitter is introduced into an input digital signal to produce an intermediate signal at a second sampling rate. The intermediate signal is then low pass filtered to produce the output signal. This technique is used in a mixed signal tester where one period of a stimulus signal is stored in a digital memory. The frequency of the analog stimulus signal is dictated by the rate at which the digital signal is retrieved from the memory. Sample rate conversion is used to convert the signal retrieved from memory, regardless of the rate at which it was retrieved, to the sampling rate for which a digital to analog converter has been calibrated.

Abstract: A method and apparatus for digital-to-digital conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that noise produced by non-uniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where it can be removed by conventional filtering techniques. In one embodiment, the digital data is interpolated by fixed ratio and then decimated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the incoming digital data stream. Thereafter, the digital data is interpolated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter and then decimated by a fixed ratio. The first and second frequency signal selection numbers are modulated using n-th order m-bit sigma-delta modulators.

Abstract: Base station equipment of a digital mobile communication system includes a digital audio signal processing apparatus provided for each message channel for low bit rate coding and decoding a digital audio signal. Each digital audio signal processing apparatus includes a plurality of memories that store a plurality of low bit rate coding/decoding programs differing from each other to comply with different low bit rate coding/decoding methods. A system control circuit determines the low bit rate coding/decoding method of an applied digital signal for controlling a selector to select a memory that stores corresponding low bit rate coding/decoding program. As a result, the digital audio signal processing apparatus performs digital to digital conversion of the applied digital signal according to the low bit rate coding/decoding program stored in the selected memory.

Abstract: A method and apparatus for digital to analog conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that errors produced by non-uniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques. In one embodiment, the digital data is interpolated by a fixed ratio and then decimated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the incoming digital data stream. The frequency signal selection number is modulated using an n-th order m-bit sigma-delta modulator. Data thus emerges from the interpolation/decimation process at the clock rate of the n-th order m-bit sigma-delta modulator.

Abstract: A method and apparatus for analog to digital conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that errors produced by non-uniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques. In one embodiment, digital data is interpolated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter and then decimated by a fixed ratio. The frequency selection signal is modulated using an n-th order m-bit sigma-delta modulator. Data thus emerges from the interpolation/decimation process at the sample rate selected by the n-th order m-bit sigma-delta modulator.

Abstract: A sampling rate converter for converting a first signal having a first sampling rate to a second signal having a second sampling rate, includes a circuit for generating first data corresponding to the ratio of the second sampling rate to the first sampling rate. A second circuit generates second data by correcting the first data with corrective data. A third circuit generates third data corresponding to an estimated output timing of the second signal based upon the second data. A comparator compares the third data with a fourth data corresponding to the actual output timing of the second signal to generate comparative data. A corrective circuit is responsive to the comparative data to generate the corrective data. A further circuit is responsive to the first and third data for generating the second signal.

Abstract: A bit resolution phase detector can be realized for a parallel elastic store by comparing a write bit clock and a read bit clock to determine when stuff bits are required; upon detection of phase alignment between the write and read clocks, the phase detector will output a signal which will enable the insertion of a data bit into the stuff opportunity bit and cause the write clock to lag the read clock by one bit period.

Abstract: In accordance with an embodiment of the invention, a data converter is disclosed that provides a sampling rate conversion. The converter receives a clock signal, a divided-down clock signal, and first digital signal samples at a first rate. The converter converts the first digital signal samples to second digital signal samples at a second rate. The ratio of the first rate to the second rate is defined as a fist conversion rate factor. A first programmable counter receives the clock signal and divides down the clock signal to produce a divided-down clock signal. The first programmable counter is programmable to selectively determine the first conversion rate factor.In an alternate embodiment, another stage of sampling rate conversion is provided by a second data converter. The second converter receives the divided-down clock signal, a further divided-down clock signal, and the second digital signal samples. The second data converter converts the second digital signal samples to the third rate.

Abstract: A sampling frequency converter of a compact size a for converting input data sampled at a sampling frequency of M=F * m.sub.1 * m.sub.2, . . . , * m.sub.k * m.sub.k+1 (m.sub.1, m.sub.2, . . . , m.sub.k, m.sub.k+1 are positive integers) into data sampled at a sampling frequency of N=F * n.sub.1 * n.sub.2, . . . , * n.sub.k (n.sub.1, n.sub.2, . . . , n.sub.k are positive integers). The converter includes a serial circuit of cascaded n stages of over-sampling filters Vi for over-sampling the input data by an n.sub.i -fold (i=1, 2, . . . , k) and down-sampling filters Wi for down-sampling the outputs of the over-sampling filters by an m.sub.i -fold, and a down-sampling filter W.sub.k+1 for down-sampling an output of the down-sampling filter at the stage k by an m.sub.k+1 -fold.

Abstract: A data conversion apparatus for a facsimile system converts a first digital data composed of a sequence of primary values sampled at a first frequency, into a second digital data composed of a sequence of secondary values sampled at a second frequency different from the first frequency. The apparatus is provided with a sampling frequency conversion unit operative before and after every sampling point timed by the second frequency for sampling a pair of preceding and succeeding primary values and for counting respective time differences from the sampling point to the preceding and succeeding primary values. The sampling frequency conversion unit further calculates a secondary value at every sampling point by linear interpolation of each pair of the sampled preceding and succeeding primary values according to the counted time differences to thereby produce the second digital data.

Abstract: Extra high quality or ultralong digital audio channels with an aggregate data bit rate that exceeds the maximum data bit rate for a digital storage medium, such as a CD, laser disk or digital audio tape, are recorded on the audio medium. The recording is accomplished by compressing the data bit rates of the multi-channel input signals so that their aggregate data bit rate after compression does not exceed the maximum for the storage medium, multiplexing the compressed audio signals, encoding the multiplexed signal into a predetermined format, and recording the encoded signal on the storage medium. With the storage medium configured to store audio samples having a predetermined number of bits per sample, the compressed audio signals are multiplexed into data groups having the same number of bits, thereby emulating a normal input to the storage medium, even when this involves dividing various input samples among different data groups.

Abstract: A sampling frequency converter capable of obtaining data sampled by sampled pulses having a sampling frequency of 2-, 4-, or 8-fold of 44.1 kHz without using an over-sampling filter. Input data sampled by sampling pulses having a sampling frequency of 32 kHz is over-sampled by a 3-fold by a first over-sampling filter, and down-sampled by a one-2nd-fold by a first down-sampling filter. One of input data sampled by sampling pulses having a sampling frequency of 48 kHz and the output of the first down-sampling filter is selected by a first selector. The output of the selector is over-sampled by a 147-fold by a second over-sampling filter, and down-sampled by a one-20th-fold by a second down-sampling filter. The output of the second down-sampling filter is down-sampled by one-2nd-, one-4th-, and one-8th-folds respectively by third, fourth, and fifth down-sampling filters. One of the outputs of the second to fifth down-sampling filters is selected by a second selector.

Abstract: A sampling frequency converter having an oversampler for operating on input data supplied to the converter, a signal processor for controlling operation of the sampling frequency converter and for generating oversampled output data from the oversampled input data, and a downsampler for generating output data at the output sampling frequency from the oversampled output data. The input and output of data by the signal processor are controlled by respective input and output interrupt signals, the output interrupt signal having a lower interrupt priority than the input interrupt signal.

Abstract: An interface circuit for use with process controllers permits analog signals to be input to a process controller through a binary interface of the process controller and permits analog signals to be output from the process controller through the binary interface. The input analog signal is converted to a digital sample of N bits. An identification pulse and the N bits of the digital sample are transmitted to the process controller at a rate selected for compatibility with the scan time of the process controller. The process controller includes a software routine for recognizing the identification pulse and the N bits of the digital sample. An equivalent approach is used for outputting analog signals through a binary interface of a process controller. The interface circuit can include multiple channels for inputting or outputting multiple analog signals.

Abstract: Base station equipment of a digital mobile communication system includes a digital audio signal processing apparatus provided for each message channel for low bit rate coding and decoding a digital audio signal. Each digital audio signal processing apparatus includes a plurality of memories that store a plurality of low bit rate coding/decoding programs differing from each other to comply with different low bit rate coding/decoding methods. A system control circuit determines the low bit rate coding/decoding method of an applied digital signal for controlling a selector to select a memory that stores the corresponding low bit rate coding/decoding program. As a result, the digital audio signal processing apparatus perform digital to digital conversion of the applied digital signal according to the low bit rate coding/decoding program stored in the selected memory.

Abstract: A sampling rate converter includes an arithmetic circuit for performing digital filtering processing for sampling rate conversion, and a circuit for calculating a sampling rate ratio. A memory circuit stores a plurality of groups of filter coefficients which are used in the digital filtering processing performed in the arithmetic circuit, corresponding to a plurality of sampling rate ratio ranges. A select circuit selects a filter coefficient group corresponding to the sampling rate ratio. The select circuit is arranged such that even if the sampling rate ratio is outside a sampling rate ratio range corresponding to a filter coefficient group selected at the present time, the select circuit continues to select the filter coefficient group selected at this time as long as the sampling rate ratio is within a predetermined range outside the sampling rate ratio range.

Abstract: In a sampling rate converter for converting a sampling frequency L of a digital signal to a sampling frequency M (L:M conversion) or for converting a sampling frequency M of a digital signal to a sampling frequency L (M:L conversion), the same filter coefficients are utilized and a constant predetermined DC gain is maintained for both conversions. An over-sampler multiplies the sampling frequency L or M by M or L, respectively, during the L:M conversion and the M:L conversion, respectively. A filter, which receives the output of the over-sampler, restricts the frequency band of the output.

Abstract: A signal processor is described for sampling rate conversion of a digitally sampled analog signal, the signal processor including an apparatus for generating an output sampled value for each output sampling instant, the output sampled value being equal to the input sampled value at the last input sampling instant if an input sampling instant has not occurred since the last output sampling instant and being calculated as an interpolation of input values at successive input sampling instants if an input sampling instant has occurred since the last output sampling instant. A virtual, analytic A/D-D/A conversion is employed using digital processing to convert from a given sampling rate to an arbitrary desired rate.

Abstract: The present invention provides a novel scheme for automatically increasing data throughput in a communication system by having data compression with delay minimization done within a modem. A high speed modem includes a logical link negotiation unit for probing and determining data compression parameters (DCPs) for a synchronous data compression link with a remote modem and for inserting the DCPs and codeword combinations into compressed data. The modem also includes a physical layer connection unit coupled to synchronous data terminal equipment to provide a delay minimizing scheme that adjustably accommodates data delivery delay to the receiving modem. A method and system incorporate the functions of the high speed modem.

Abstract: A converter (200) includes a transmit circuit that converts modem transmit samples at 9,600 samples/second into samples that may be transmitted by a T1 channel bank at 8,000 samples/second. The converter also includes a receive circuit that converts T1 channel bank receive samples at 8,000 samples/second into samples that may be received by a modem at 9,600 samples/second.

Abstract: A sampling rate converter has a pulse-dulation modulator for converting a pulse-code-modulated signal, which has been sampled with a first sampling frequency, into a pulse-dulation-modulated signal, and a counter for counting pulses of the pulse-dulation-modulated signal and producing a count in each sampling period determined by a second sampling frequency. The sampling rate converter also includes a multiplier connected to the output of the counter.

Abstract: A sample rate conversion system converts from an input sample rate stream having a predetermined input sample rate to an output sample stream having a predetermined output sample rate by interpolating output samples from the input samples using first and second approximate sample rate ratios. The system includes circuitry which selects a sequence of interpolation filters from among a set of filters, the sequences being defined by one of these approximate ratios, and circuitry which monitors the magnitude of the accumulated error introduced by the approximation. When this accumulated error becomes greater than a threshold, the system changes to use a further sequence of interpolation filters based on the other approximate ratio. The accumulated error changes in a positive sense with each successive sample while one of the two approximate ratios is used. The accumulated error changes in a negative sense with each successive sample while the other of the two approximate ratios is used.

Abstract: A sampling frequency converting apparatus includes an input port converting an input image data (X) into a data packet, a data driven engine executing interpolation on the data packet applied from the input port for performing sampling frequency conversion in which an operation is performed in accordance with a predetermined data flow program, an output port outputting the data packet produced by the data driven engine at a second sampling frequency, and an image memory for data processing. The sampling frequency converting apparatus can easily accommodate change of specification of the sampling frequency, and can be easily produced without requiring complicated timing control.

Abstract: A device for doubling or dividing by 2 the flow rate of series bits comprising a succession of first one-bit registers (R4-R0) actuated at a frequency F; a second register (R) actuated at a frequency 2F; an input terminal (IN) connected to the input of the first (R4) of the first registers and, through a first gate (T5), to an internal line (L) connected to the input of the second register; first multiplexers (M4-M1) connected to the input of each second (R3) to last (R0) of the first registers for selecting either the output of the preceding register, or the internal line, or still the output of the second register; a second multiplexer (M), which selects either the output of the last (R0) of the first registers, or the output of the second register, or filling bits; second transfer gates (T4-T0) between the output of each first register and the internal line; and means for controlling the various gates and multiplexers.