Abstract: The present invention pertains to a distance-enhancing coding method that can be applied to digital recording and digital communications. It improves the time-varying maximum transition run method used in a conventional distance-enhancing coding to avoid main error events ±(1,−1) from happening. Under the premise of maintaining a code gain of 1.8 dB, the code rate can be increased from ¾ to ⅘. The invention also provides a method of using an enumeration algorithm and an exhaustive method to search for block codes for distance-enhancing coding, which can find required codes by following specific steps.

Abstract: The decimator filter includes at least three identical undersampled filters out-of-phase with each other and connected in parallel, and an interpolator connected to the output of each filter. The decimator filter includes a triple integrator having an output connected to each of the filters. Each filter defines a channel that includes in sequence an undersampling circuit, a differentiator and a multiplier. The outputs of the multipliers are connected to an adder. The input signals to each of these channels are offset by a delay equal to one period of the oversampled frequency. Each undersampling circuit and each multiplier has a second input receiving a signal from a state machine. The decimator filter improves the required phase extraction time and the precision defined in the ISDN U interface specifications. By combining the decimation filter and the extraction functions, a device is produced in a small area, which consequently, consumes low power.

Abstract: A filter system and method are provided that is particular applicable to the resampling of a signal, such as a digital audio signal. The filtering method in accordance with the invention may use a nearest neighbor strategy to reduce the complexity and cost of the filter without reducing the precision of the resampling.

Abstract: Methods and apparatus are provided for sample rate conversion in a system including two or more sample rate converters. The method includes the steps of providing an input clock and an output clock to each of the sample rate converters, measuring a sample rate ratio of the clocks in one of the sample rate converters, designated as a master, and controlling each of the sample rate converters with the sample rate ratio measured by the master. The measured sample rate ratio may be transmitted from the master to each of the other sample rate converters. This approach matches the group delays among the sample rate converters.

Abstract: An MPEG coded and compressed video signal is received and decompressed for display. Prior to storing frames required for motion compensation in memory, pixel blocks are recompressed into DPCM prediction error values to reduce bandwidth and frame memory requirements. Fixed length quantization and dequantization tables (FIG. 2) have N levels (e.g., 15 levels), and each level has an associated output symbol of predominantly M bits (e.g., 4 bits), except that at least one of said N levels (e.g., level 7) is defined by a unique short symbol having less than M bits (e.g., 3 bits), and input data for that level is received at a desired rate. Each time a short symbol is used to represent a data value, bandwidth and memory are reduced and/or preserved for other uses, for example, inserting overhead data into a fixed-size data stream. For large sequences of data, such as exists for video data for example, the reduction in memory and bandwidth is significant.

Abstract: A method and apparatus for sample rate conversion in an analog to digital converter includes processing that begins by converting an analog input signal into a stream of digital data. The processing continues by determining an up sampling value and a down sampling value based on a sample rate conversion value. The processing continues by computing a moving sum of data of the stream of data based on the up sampling value, the clock rate of the stream of data, and a predetermined filter function. The processing continues by producing a digital output value from the moving sum based on the down sampling value, wherein the digital output value is at a desired output rate.

Abstract: A resampler device and method are used to convert a digital input signal string (Sin) with an input-sampling rate into a digital output signal string (Sout) with a higher output-sampling rate. Prior to interpolation, a time shift (tmod(n)/Tout) is first determined for every sampling time (t′n) of the output signal string (sout) relative to a next sampling time (ti+1) of the input signal string (sin). Then the time shift (&Dgr;t(n)/Tout) of the sampling time (t′n) of the output signal string (Sout) relative to the preceding sampling time (ti) of the input signal string (Sin) is determined from the previously determined time shift (tmod(n)/Tout) relative to the next sampling time (ti+1).

Abstract: A method for upsampling a digital audio signal is described. The method includes receiving a first digital audio signal including samples and having a first sampling rate. The method also includes outputting at least one sample from the first digital audio signal as part of a second digital audio signal, the second digital audio signal having a desired second sampling rate, the second sampling rate being higher than the first sampling rate. The method also includes incrementing a counter for each sample from the first digital audio signal that is output as part of the second digital audio signal. The method also includes, when the counter exceeds a threshold number, inserting at least one synthetic sample as part of the second digital audio signal. The method also includes repeating the outputting, incrementing, and inserting until all the samples in the first digital audio signal have been output.

Abstract: A system for, and method of, increasing sample rate converter filter coefficient derivation and running speed and a digital signal processor incorporating the system or the method. In one embodiment, the system includes: (1) a coefficient table containing a matrix of predefined filter coefficients for each of a plurality of alpha intervals and (2) an intra-range interpolator that adjusts the predefined filter coefficients for a specific alpha within the alpha interval to yield filter coefficients specific to the alpha.

Abstract: In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop filter capacitor nor for a large loop filter capacitor to be integrated on the same integrated circuit die as the PLL. In a preferred embodiment, an analog phase detector is utilized whose phase error output signal is delta-sigma modulated to encode the magnitude of the phase error using a digital (i.e., discrete-time and discrete-value) signal. This digital phase error signal is “integrated” by a digital integration block including, for example, a digital accumulator, whose output is then converted to an analog signal, optionally combined with a loop feed-forward signal, and then conveyed as a control voltage to the voltage-controlled oscillator.

Abstract: A system for, and method of, increasing sample rate converter filter coefficient derivation and running speed and a digital signal processor incorporating the system or the method. In one embodiment, the system includes: (1) a coefficient table containing a matrix of predefined filter coefficients for each of a plurality of alpha intervals and (2) an intra-range interpolator that adjusts the predefined filter coefficients for a specific alpha within the alpha interval to yield filter coefficients specific to the alpha.

Abstract: In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the highest, ½ of the frequency of the input digital data are employed for operating the SPC circuit, whereby the SPC circuit is improved in power dissipation, stability and reliability.

Abstract: A method for upsampling a digital audio signal is described. The method includes receiving a first digital audio signal including samples and having a first sampling rate. The method also includes outputting at least one sample from the first digital audio signal as part of a second digital audio signal, the second digital audio signal having a desired second sampling rate, the second sampling rate being higher than the first sampling rate. The method also includes incrementing a counter for each sample from the first digital audio signal that is output as part of the second digital audio signal. The method also includes, when the counter exceeds a threshold number, inserting at least one synthetic sample as part of the second digital audio signal. The method also includes repeating the outputting, incrementing, and inserting until all the samples in the first digital audio signal have been output.

Abstract: A variable rate decimator is described, intended to reduce a digital signal sample rate while maintaining a level of digital signal integrity at a relatively low cost. It is also a goal of the variable rate decimator described herein to provide a scalable decimator architecture while maintaining relatively low complexity of use.

Abstract: A bit-rate converting apparatus and a method thereof, in which bit-rate conversion is executed by low computational complexity, are provided. The bit-rate conversion is executed in a frequency domain, and psycho-acoustic analysis is not needed by using information included in an inputted bit-stream before the bit-rate conversion is applied. With this, the computational complexity is lowered. And in order that many equal values are not contained in a frequency domain signal, which is inputted to a quantizing means, a quantized value before inverse quantizating is applied is modified, or an inverse quantized value after the inverse quantizing was applied is modified. With this, fine control for the bit-rate is made to be easy.

Abstract: A variable rate decimator is described, intended to reduce a digital signal sample rate while maintaining a level of digital signal integrity at a relatively low cost. It is also a goal of the variable rate decimator described herein to provide a scalable decimator architecture while maintaining relatively low complexity of use.

Abstract: A scalable physical coding sublayer (PCS) can be adjusted to provide different combinations of communication channels and data widths. The PCS can use 8B/10B encoders having a disparity input connection and at least one disparity output connection. In one embodiment, the encoder has both a synchronous and an asynchronous disparity output connection. The encoder can be coupled with additional encoders to provide an expanded width channel of 16B/20B encoding. Additional configurations are possible. In expanded operation, only one of the encoders needs to output special codes. The encoders, therefore, include a slave input connection to place the encoder in a slave mode so that a special code is replaced with an inert special code. All but one encoder in an expanded system are slave encoders. An idle input connection is also provided in the encoders to place the encoder in an idle mode where pre-defined data is output from the encoder.

Abstract: Methods and apparatus are provided for sample rate conversion in a system including two or more sample rate converters. The method includes the steps of providing an input clock and an output clock to each of the sample rate converters, measuring a sample rate ratio of the clocks in one of the sample rate converters, designated as a master, and controlling each of the sample rate converters with the sample rate ratio measured by the master. The measured sample rate ratio may be transmitted from the master to each of the other sample rate converters. This approach matches the group delays among the sample rate converters.

Abstract: A method for providing audio sample rate conversion within a data-processing system is disclosed. An audio data stream having an input sample rate is first received. A sampling frequency ratio of the input sample rate to a selected output sample rate is determined, and this sampling frequency ratio is then utilized to compute output samples. The output samples are subsequently filtered with a lowpass filter and output at the selected output sample rate.

Abstract: An anti-aliasing filter with adaptable cutoff frequency. In various embodiments, the filter includes a calibrator/adaptor section and an anti-aliasing filter section. Both sections include a cascaded arrangement of adjustable delay circuits, and the calibrator/adaptor section includes a control circuit. A reference signal is input to the delay circuits and the control circuit of the calibrator/adaptor section, and an analog input signal is input to the delay circuits of the anti-aliasing filter. The control circuit compares the directly received reference signal to the reference signal from the last delay circuit and generate an adjustment signal responsive to the comparison. The delay intervals of all the delay circuits are adjustable responsive to the adjustment signal from the control circuit.

Abstract: A filter system and method are provided that is particular applicable to the resampling of a signal, such as a digital audio signal. The filtering method in accordance with the invention may use a nearest neighbor strategy to reduce the complexity and cost of the filter without reducing the precision of the resampling.

Abstract: A sample rate converter 210, 209 includes a filter 210 for processing digital data in response to a clock controlled by a clock enable signal, the filter 210 receiving the digital data at a first sampling rate and outputting digital data at a second sampling rate. Resampler circuitry 209 generates first selected periods of the clock enable signal having a first duty cycle approximating a ratio between the first sampling rate and the second sampling rate. Selectively, selected periods of the clock enable signal are generated having a second duty cycle for minimizing an error accumulated over the first selected periods of the clock enable signal.

Abstract: A method for providing a sample-rate conversion (“SRC”) filter on an input stream of sampled data provided at a first rate, to produce an output stream of data at a second rate different from the first rate. The input stream of sampled data is operated on with a first low-order interpolation filter routine to produce a first stream of intermediate data. The first stream of intermediate data is operated on with a first simplified interpolation filter routine, having a substantially small number of operations to calculate the coefficients thereof, to produce a second stream of intermediate data. The second stream of intermediate data is operated on with a first decimating filter routine to produce the output stream of data.

Abstract: Analog-to-digital converter for converting an analog input signal which is present at a signal input (2a, 2b) and has a specific frequency bandwidth, into an offset-free digital output signal, having a subtracting amplifier (5), which subtracts an analog actuating signal from the analog input signal in order to generate an analog difference signal and amplifies the analog difference signal generated, an analog-to-digital converter circuit (18) having a high clock rate for converting the amplified analog difference signal into the digital output signal, a digital clamping circuit (24) for digital low-pass filtering of the digital output signal, and having a digital-to-analog converter circuit (49) for converting the digital output signal filtered by the clamping circuit (24) into the analog actuating signal.

Abstract: A method and device for converting high rate serial data into low rate serial data are disclosed.

Abstract: Disclosed is transmission of a signal over a single interconnect between functional blocks of the IC. A scaled or encoded signal responsive to a first digital signal is generated by summing currents responsive to the first control signal. The summed currents, which may be the sum of one or more currents, is the scaled signal. The encoded signal is transmitted over a single interconnect. This transmission occurs in one clock period in contrast to the at least two clock periods required to serially transmit data. The encoded signal is then used to generate a second digital signal. The generation of the second digital signal preferably includes mirroring the current of the encoded signal. The mirrored current is can then generate one or more separate voltages which are used to generate the second digital signal.

Abstract: The hardware of an over-sampling A/D and D/A converter is provided, which hardware is capable of being operated with either kind of software: one corresponding to a first method in which the over-sampling ratio is fixed and the other corresponding to a second method in which the over-sampling ratio is variable. The value N3 written on the pseudo-frequency-dividing-ratio-register 11 and the value N4 written on the pseudo-over-sampling-ratio-register 21 are converted through a user interface into the frequency dividing ratio N1 by the conversion circuit 12 and the converted result is written in the frequency-dividing-ratio-register 10.

Abstract: The present invention describes a system and method for encoding a sequence of 64 bit digital data words into a sequence of 65 bit codewords having constraints of (d=0, G=11/I=10) for recording upon a magnetic medium within a magnetic recording channel are disclosed. The method for encoding a sequence of 64 bit digital data words into a sequence of codewords having 65 bits, comprising the steps of dividing each 64-bit digital data word into 8-bit bytes, encoding two 8-bit bytes to form a 17-bit word, forming five 11-bit intermediate blocks from the 8-bit bytes, encoding the five 11-bit intermediate blocks, and concatenating the five encoded 11-bit intermediate blocks and uncoded and unconstrained bits from the 64 bit digital data word to form a 65 bit codeword. A corresponding decoding method is also described. A byte shuffler may be used in the processing.

Abstract: A sampling system includes an input terminal for receiving a data signal having a signal component and possibly a noise component. A sampler samples the data signal at a sample rate set in responsive to a control signal. A noise detector detects the presence of a noise component, and if a noise component is detected, generates the control signal conditioning the sampler to sample the data signal at a first sample rate satisfying the Nyquist criterion for the data signal including the noise component, and otherwise generating the control signal conditioning the sampler to sample the data signal at a second data rate satisfying the Nyquist criterion for the data signal including only the signal component.

Abstract: A sample rate converter for converting the sampling frequency of an input signal from a first frequency to a second frequency. Such a sample rate converter uses interpolator and a phase-locked loop receiving the first and the second sampling frequency. The interpolator is implemented as a polynomial interpolator.

Abstract: A method and apparatus for sample rate conversion in an analog to digital converter includes processing that begins by converting an analog input signal into a stream of digital data. The processing continues by determining an up sampling value and a down sampling value based on a sample rate conversion value. The processing continues by computing a moving sum of data of the stream of data based on the up sampling value, the clock rate of the stream of data, and a predetermined filter function. The processing continues by producing a digital output value from the moving sum based on the down sampling value, wherein the digital output value is at a desired output rate.

Abstract: A method and apparatus for analog to digital conversion includes processing that begins by quantizing an analog input signal to produce a stream of digital data at an over sampling rate. The processing continues by producing partially filtered data based on a moving sum of the stream of data. The processing continues by decimation filtering the partially filtered data to produce a digital output value.

Abstract: A multirate digital-to-analog amplifier system is disclosed. An interpolator is configured to interpolate digital values between samples of a digital signal from a digital signal source, in which the digital signal has a first sample rate. An output signal from the interpolator has a second, predetermined sample rate, which is independent of the first sample rate, of the digital signal. An amplifier is configured to amplify a digital signal having the second sample rate in response to the output signal of the interpolator.

Abstract: An arbitrary sample rate conversion apparatus is described. This apparatus includes a buffer for forming blocks of input samples having a first sample rate. For each block of input samples a subfilter is selected from a polyphase filter. Each block of input samples is convolved with the corresponding selected subfilter for producing blocks of output samples having a second sample rate.

Abstract: A general-purpose processor performs high-speed variable-length decoding. The general-purpose processor includes a video data register for exclusively storing the variable-length code that stores data having a length larger than the maximum length of the variable code to be decoded. The general-purpose processor also includes a data counter register for exclusively storing the length of the data in the video data register which has not been decoded, as well as a pointer register for exclusively storing the address of the variable-length code to be read out next from a bit stream stored in memory. The general-purpose processor also includes an ALU for performing general purpose operations, and decodes the variable-length code stored in the video data register by controlling the video data register, the data counter register, and the pointer register.

Abstract: A device and method for data rate selection in data transmission is provided, having a first register for storing an N bit data upon clocking by a first clock; a second at least one register for storing the N bit data upon clocking by a second clock, the second clock having a clock rate of two times the clock rate of the first clock; a circuit for receiving the N bit data output from the first register and outputting a first half of the N bit data during a first phase of the first clock and outputting a second half of the N bit data during a second phase of the first clock; and a multiplexer for receiving as first inputs the output of the circuit and second inputs the output of the second at least one register, wherein the multiplexer outputs the first inputs as a lower speed data and outputs the second inputs as a higher speed data based on a rate select signal.

Abstract: A resampler device and method are used to convert a digital input signal string (Sin) with an input-sampling rate into a digital output signal string (Sout) with a higher output-sampling rate. Prior to interpolation, a time shift (tmod(n)/Tout) is first determined for every sampling time (t′n) of the output signal string (sout) relative to a next sampling time (ti+1) of the input signal string (sin). Then the time shift (&Dgr;t(n)/Tout) of the sampling time (t′n) of the output signal string (Sout) relative to the preceding sampling time (ti) of the input signal string (Sin) is determined from the previously determined time shift (tmod(n)/Tout) relative to the next sampling time (ti+1).

Abstract: A method comprising identifying a sample rate of received audio content, receiving a conversion sample rate, and converting the received audio content to the received conversion sample rate. Wherein the conversion comprises utilizing a repeating sequence of packets where all but one of the packets of each sequence are truncated to a whole number of samples, while the remaining packet is rounded up to the next whole number of samples if the conversion fails to resolve packet size to a whole number.

Abstract: A resampler converts a digital input sequence with an input sampling into a digital output signal sequence with an output sampling rate. An estimation device estimates the sampling rate ratio between the input sampling rate and the output sampling rate and the desired phase of the output signal sequence in an observation interval with a predetermined length of N samples of the output signal sequence, the observation intervals overlapping in the ratio 1:6. A control device compares the actual phase of the output signal sequence with the desired phase and, in a manner dependent on the estimated sampling rate ratio and the deviation of the actual phase from the desired phase, generates a control signal for in each case N/6 samples of the output signal sequence. An interpolator interpolates the input signal sequence for the purpose of generating the output signal sequence at sampling instants whose temporal position is predetermined by a control signal.

Abstract: A resampler is used to convert an input digital signal sequence having an input sampling rate into an output digital signal sequence having an output sampling rate (fout). An estimating unit estimates the sampling rate ratio between the input sampling rate and the output sampling rate (fout) and estimates the set point phase of the output signal sequence in observation intervals whose observation length is variable. A controlling system compares the actual phase of the output signal sequence with the set point phase and generates a control signal (RTC,k) as a function of the estimated sampling rate ratio and the deviation of the actual phase from the set point phase. An interpolator interpolates the input signal sequence for generating the output signal sequence at sampling times whose location in time is predetermined by the control signal (RTC,k).

Abstract: Audio data decoded in an MPEG system to be stored in a storage unit is supplied to an audio output via a filtering processing. For performing the filtering processing, presentation time interval of respective audio data is changed to conform to a user's designated playback speed, and the decoded audio data stored in the storage unit by being synchronized with the changed presentation time interval is written on an input queue in the set unit. A TSM algorithm is performed in the frame unit with respect to the audio data of the input queue to decrease the quantity of the audio data when the designated playback speed is faster than a normal playback speed or to increase it when the designated playback speed is slower than the normal playback speed, in accordance with a value of the designated playback speed. The TSM audio data is transferred to a middle queue.

Abstract: An improved design and method of a digital decimation and interpolation filter for a multi-bit input signal, reduces the buffer requirement during a decimation operation and relieves the processing bottleneck during an interpolation operation through the use of transposition of an FIR filter structure having time-varying coefficients. The design includes an input lead (120), a multiplier (122), a accumulator (132), a memory (128), a shift register (132), an output buffer (138) and a sequencer (140). The input lead receives the digital input signal. The multiplier (122) having a first and second multiplier input terminal coupled to the input lead (120) at its second multiplier terminal receives the digital input signal. The memory (128), having stored coefficient sets, is coupled to the first multiplier input terminal. The sequencer (140), coupled to the memory (128) and the output buffer (138), transfers each coefficient set to the first multiplier input terminal.

Abstract: A resampler (1) is used to convert a digital input signal string (Sin) with an input sampling rate (fin) into a digital output signal string (Sout) with an output sampling rate (fout). An estimating unit (11) estimates a sampling rate ratio (Rk) between the input sampling rate (fin) and the output sampling rate (fout) and a setpoint phase of the output signal string (Sout). A regulating unit (12) compares an actual phase of the output signal string (Sout) to the setpoint phase, and generates a control signal (RTC,k) as a function of the estimated sampling rate ratio (Rk) and a deviation of the actual phase from the setpoint phase. An interpolator (7) interpolates the input signal string (Sin) for producing the output signal string (Sout) at sampling times whose temporal position is determined by the control signal (RTC,k).

Abstract: The invention dynamically compensates for differences in data rates. In one embodiment, the status of an input buffer is monitored and used to change the number of oversamples within a frame. In another embodiment, a high frequency clock in the system is used to stall the codec for one clock. In both ways, distortion due to differences in data rates is reduced.

Abstract: A reproducing arrangement (1; 14) is adapted to reproduce compressed data (KD) included in data blocks (DB) of a data stream (DS) in a normal speed reproducing mode and in a multi-speed reproducing mode. The compressed data (KD) included in each data block (DB) are decompressible independently of one another and the sequence of the encoded data blocks (KB) in the data stream (DS) corresponds to the sequence of reproduction of the decoded data (KD) in the normal speed reproducing mode. In the multi-speed reproducing mode of the reproducing arrangement (1; 14) encoded data (KD) are read from only a part of the data blocks (DB) of the data stream (DS) and supplied to decoding means (7) of the reproducing arrangement (1; 14), whose computing capacity is therefore also adequate for the multi-speed reproducing mode.

Abstract: A signal processing circuit for converting a 2-channel analog signal into a digital signal includes an analog/digital conversion component for sequentially converting the 2-channel analog signal into digital data according to a sampling clock, and an operation control component for setting a high sampling frequency of the sampling clock at a frequency higher than a normal sampling frequency of the sampling clock and setting a sampling clock duty ratio so that digital data of at least one channel can be sampled.

Abstract: Sample rate converters are known, and are used to convert a signal with a first sample rate (sampling frequency) into a signal with a second sample rate (sampling frequency). To obtain a flexible sample rate converter with sampling frequencies that are not known beforehand, until now only sample rate converters with very high intermediate sampling frequencies are known. The invention provides a flexible sample rate converter, which is able to handle unknown input and output sampling frequencies. This is achieved by using polyphase decomposition filter means in combination with interpolation means.

Abstract: A digital/analogue communication system is described, where data is generated and received by a processing unit in a digital format and transmitted via a communication path in an analogue format. A DSP unit receives a sequence of multi-bit digital samples at a first sampling rate and generates a plurality of interpolated samples. A bit generation unit receives the multi-bit digital samples and the interpolated samples and generates a sequence of single-bit digital samples at a second sampling rate which is higher than the first sampling rate. A set of single wire communication paths are used to convey the single-bit digital samples to respective digital to analogue converters. The use of single-bit digital samples allows them to be held in a buffer. A buffer controller can be provided to delete single-bit digital samples from the buffer so as to match the sampling times at at least one reference frequency of a received signal with sampling times of a generated signal.

Abstract: A method for upsampling a digital audio signal is described. The method includes receiving a first digital audio signal including samples and having a first sampling rate. The method also includes outputting at least one sample from the first digital audio signal as part of a second digital audio signal, the second digital audio signal having a desired second sampling rate, the second sampling rate being higher than the first sampling rate. The method also includes incrementing a counter for each sample from the first digital audio signal that is output as part of the second digital audio signal. The method also includes, when the counter exceeds a threshold number, inserting at least one synthetic sample as part of the second digital audio signal. The method also includes repeating the outputting, incrementing, and inserting until all the samples in the first digital audio signal have been output.

Abstract: In a tape drive, or other storage device, used for storing computer data, both record data and record structure information such as file marks are encoded with codewords to form an encoded data stream. Of the fixed number of possible fixed-length codewords, one codeword is assigned as a root sequence for one or more longer codewords. Thus, detection of the root sequence during decoding of an encoded data stream triggers the reading of a fixed number of further bits. The further bits represent file marks and any other defined information. In the tape drive (800), the tape drive interface (810) receives record data and file mark commands. The formatter (820) encodes the record data as fixed length codewords.