Abstract: A variable encoding puncturer, for encoding data in response to a variable encoding rate, in a digital broadcasting communication encoder, including a control unit for controlling an alignment of input data and a selection of a compression matrix, and an alignment of output data according to a variable encoding rate inputted from an external circuit; an input data aligning control unit for outputting the aligned data in parallel in response to an input clock signal after aligning data with a variable encoding rate in response to a control of the control unit; an input buffer for storing, in order, the aligned data from the input data aligning control unit; an output data aligning control unit for selecting the aligned data from the input buffer according to the variable encoding rate under the control of the control unit and for outputting the selected data; and an output buffer outputting the selected data encoded data from the output data as aligning control unit in response to an output clock signal.

Abstract: A sample rate conversion system and method uses a digital signal processor (DSP) and a separate sample rate conversion circuit (SRC) to perform multiple stream conversion and mixing of different rate input audio streams. The sample rate conversion system converts data, such as multiple streams of digital audio data sampled at different rates, and performs interpolation, decimation, FIR filtering, and mixing of multiple streams of data using the separate SRC. The SRC uses two bidirectional I/O memories for alternately storing input and output data as part of a sample rate converter. When the sample rate converter writes output to one of the bidirectional memories, it has the option of summing the data with the data already stored in the same I/O memory. Therefore a separate digital signal processor can use the sample rate converter circuit to perform some of the mixing for the multiple streams.

Abstract: A sample rate converter for converting a digital signal having a particular sample rate frequency into a signal having a different, specified sample rate frequency. The converter includes an interpolation function for increasing the sample rate frequency of the input signal by an interpolation factor (L), so as to produce an intermediate signal having an intermediate sample rate frequency. The intermediate signal is then filtered with a predefined single-stage, low-pass filter to eliminate high frequency noise introduced as a result of the interpolation. The filtered intermediate signal is then supplied to a decimation function, which extracts samples from the intermediate signal in accordance with a decimation factor (M), thereby producing an output signal having the desired sample rate frequency. The filter is configured so as to be optimized to provide the best conversion results for a plurality of critical input/output sample rate conversion pairs, which are used to define the filter cutoff frequency.

Abstract: In one embodiment a system is provided for multirate communications allowing for different data rates for each data unit on a channel, including both data units from different mobile units and from the same mobile unit. A sending unit preferably begins by determining the rate at which to start communications, and monitors, for example by use of an RSSI detector, for an indication that the rate should be changed. A rate adjustor implements the change, and can make changes as frequently as every data unit. The encoder applies the appropriate rate and inserts a rate indicator indicative of the data or encoding rate, and sends the data unit. On receiving data units, the receiving unit first determines the rate for each data unit or group of units, then appropriately decodes the data unit(s). As a result, the actual data throughput can be adjusted to permit optimized throughput.

Abstract: A method and apparatus for analog to digital conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that errors produced by nonuniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques. In one embodiment, digital data is interpolated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter and then decimated by a fixed ratio. In another embodiment, the digital data is interpolated by a fixed ratio and then decimated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter. The frequency selection signal is modulated using an n-th order m-bit sigma-delta modulator.

Abstract: A sample rate conversion system and method uses a digital signal processor (DSP) and a separate sample rate conversion circuit (SRC) to perform multiple stream conversion and mixing of different rate input audio streams. The sample rate conversion system converts data, such as multiple streams of digital audio data sampled at different rates, and performs interpolation, decimation, FIR filtering, and mixing of multiple streams of data using the separate SRC. The SRC uses two bidirectional I/O memories for alternately storing input and output data as part of a sample rate converter. When the sample rate converter writes output to one of the bidirectional memories, it has the option of summing the data with the data already stored in the same I/O memory. Therefore a separate digital signal processor can use the sample rate converter circuit to perform some of the mixing for the multiple streams.

Abstract: A first data storing and outputting apparatus includes a coding unit for coding data of a program through N coding processes and generating N sets of coded data of the program, N being a natural number more than one, a memory for storing the N sets of coded data of the program, and a reading and outputting circuit responsive to a request for selectively reading and outputting one of the N sets of coded data of the program from the memory.

Abstract: Audio sample rates are converted by an arbitrary ratio of Q/P using a two-stage sample-rate converter. One stage is an L-tap low-pass finite-impulse-response (FIR) filter, while the other stage is a linear interpolator. Coefficient storage for the L-tap low-pass FIR filter is dramatically reduced by reducing the effective P factor. The effective P factor is reduced by using two stages, with each stage adjusting the sampling rate by a different ratio. A first stage adjusts the sampling rate by Q0/P0, while a second stage further adjusts the sampling rate by Q1/P1. Q0 and P0 are large integers of about 400 to 700 that differ by one or three; thus the ratio Q0/P0 is very close to one. The linear interpolator stage eliminates or adds one or three samples and smoothes the samples by linear interpolation over the 400 to 700 remaining samples. The FIR filter stage adjusts the sample rate by a ratio of Q1/P1, which is approximately but not exactly Q/P.

Abstract: An over-sampling device is provided for double over-sampling the input signal and for outputting as a sampling signal. The sampling signal is filtered at one of conversion rates of 147/160, 160/147, and 1/1 by using a prototype filter, based on the first sampling frequency and the second sampling frequency, and a filtering signal is produced. The filtering signal is filtered by a low pass filter having a predetermined cutoff frequency band, and a low frequency signal is produced. A down-sampling device is provided for down-sampling the low frequency signal by one half.

Abstract: A rational decimation circuit (200) has an integration filter (210) and an FIR-filter (220). The integration filter (210) has N serially arranged integrator blocks (230-n) and an interpolator block (250). The FIR-filter (220) has K filter channels (260-k) and a commutator (290) which are controlled by a control block (300). Each channel (260-k) has a multiplier unit (270-k) and an accumulator unit (280-k).The integration filter (210) has a transfer function with N-fold poles and the FIR-filter (220) has a transfer function with zeros which cancel the poles. FIR-coefficients h.sub.k (T.sub.V) in the FIR-filter (220) are related to the F.sub.V /F.sub.X ratio of the interpolator block (250) and to the number N of integrator blocks (230-n). A method is also described.

Abstract: A variable-length code decoding apparatus for decoding sequential variable-length codewords includes a first barrel shifter for producing a first window output sequence in response to a window control signal, a second barrel shifter for producing a second window output sequence and a code value in response to a decoded codeword length, a relay circuit for latching the second window output sequence for the clock cycle and providing the latched second window output sequence as a decoding output sequence, a first look-up table memory for producing the decoded codeword length in response to a pre.sub.-- fix code of the variable-length codeword that begins at the first bit position of the decoding output sequence, a second look-up table memory for producing a fixed-length word in response to the decoded codeword length and the code value, and an accumulation block for producing the window control signal.

Abstract: According to decode system and method of the present invention in which a system clock is generated on the basis of a time stamp contained in transmission data to be transmitted every packet, and the transmission data are decoded on the basis of the system clock, the transmission data are stored into a buffer memory before a time stamp is extracted, and a packet storage amount of the transmission data stored in the buffer memory is detected to increase the read-out rate of the transmission data from the buffer memory when the storage amount is larger than a predetermined reference value and reduce the read-out rate of the transmission data from the buffer memory when the storage amount is smaller than the predetermined reference value.

Abstract: A method and apparatus for digital-to-digital conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that noise produced by NONUNIFORM sampling are frequency-shaped to a region (i.e., shifted to higher frequencies where it can be removed by conventional filtering techniques. In one embodiment, the digital data is interpolated (16) by fixed ratio and then decimated (21) under control of a first sigma-delta modulated frequency selection signal (26) that represents, on average, the data rate of the incoming digital data stream. Thereafter, the digital data is interpolated (30) under control of a second sigma-delta modulated frequency selection signal (46) that represents, on average, the data rate of the digital data to be output by the converter and then decimated (40) by a fixed ratio.

Abstract: A cascaded integrator-comb (CIC) interpolation filter is included within a digital-to-analog converter (138) and includes two up-samplers (150, 164). The two up-samplers (150, 164) also include a sample-and-hold function. The first up-sampler (150) up-samples an output of a differentiator (140). The second up-sampler (164) up-samples an output of an integrator (152) This reduces the area and power requirements of the CIC interpolation filter, while providing approximately the same filtering performance in the pass band and transition band. The total over-sample ratio of the CIC interpolation filter is equal to the first up-sampling ratio multiplied by the second up-sampling ratio. The stop band requirements of the CIC interpolation filter determines the relative sizes of the first and second up-sampling ratios.

Abstract: A memory control apparatus for compression or expansion of data includes an input end for receiving a signal indicating the data rate of the original data and a second signal indicating the data rate of the target data, a first unit for generating an addressing control signal and a select control signal which vary a write or read address of the memory, in response to the first data rate and the second data rate, and a second unit for generating, in synchronization with the addressing control signal of said first unit, a write enable signal of the memory for controlling compression of the input data or a read enable signal of the memory for controlling expansion of the input data, according to the select control signal and first and second data rates. Thus, the input data can be freely compressed or expanded at any desired ratio.

Abstract: A digital QPSK demodulator includes a plurality of two-input-two-output (TITO) two-fold decimators where each TITO two-fold decimator operates at a rate equal to its input data rate. The in-phase I signal and the quadrature Q signal are computed in an interleaved sequence of {Q"(n), I"(n), Q"(n+1), I"(n+1), . . . } to generate Q" decimation output and I" decimation output. The TITO two-fold decimators are cascaded in a reverse order to form a programmable down-sampler which decimates the input data by factors of 1, 2, 4, 8 or more. In a first embodiment, the programmable down-sampler is coupled between a complex multiplier and an interpolator. In a second embodiment, the in-phase and quadrature signals are fed through a complex multiplier, an interpolator, then the programmable down-sampler. In the third embodiment, the in-phase and quadrature signals are fed through an interpolator, a complex multiplier, then the programmable down-sampler.

Abstract: A sampling phase of digital data is converted with having a phase stabilization and a phase alignment. In a converting circuit for converting first digital data synchronized with a fist clock into second digital data synchronized with a second clock not synchronized with the first clock, there are provided; a dividing circuit for dividing 1 (one) time period of the first clock into N time periods ("N" being larger than, or equal to 2); a coefficient setting circuit for setting first and second interpolation coefficients with respect to each of the divided time periods; a data producing circuit for producing the second digital data from data within a certain clock period and data within another clock period subsequent to the certain clock period among the first digital data by using the first and second interpolation coefficients in the divided period where the second clock is located, among the first and second interpolation coefficients set for each of the divided periods.

Abstract: A serial data timing base modulator includes a bidirectional data format converter, a data buffer, and a timing base generator. The bidirectional data format converter converts inputted serial data into parallel data which are then stored in a computer via the data buffer. The converted parallel data are sent to the buffer after being analyzed and emulated. The timing base generator outputs a train of timing pulses which have the same presentation speed of the original inputted serial data. The bidirectional data format converter converts the parallel data into serial data based on the timing pulses sent from the timing base generator, thus recovering the parallel data to the originally inputted serial data.

Abstract: The present invention includes a method and circuit for the compression encoding and decoding of digital images. In particular, the method is directed to an improved implementation of the QM-Coder as defined in the JBIG Standard and a merged implementation of the QM-Coder as defined in the JBIG Standard with the Q-Coder as defined by the IBM ABIC standard. The improved implementation of the QM-Coder as defined in the JBIG Standard includes an improved CLEARBITS procedure. The merged implementation of the QM-Coder as defined in the JBIG Standard and Q-Coder as defined by the ABIC standard includes the sharing of hardware to reduce implementation logic.

Abstract: A method for resampling includes convolving a given set of samples with the impulse response function of a low-pass filter. In this method, values of the impulse response required for the convolution calculation are computed at the time of resampling from a segmented polynomial approximating the impulse response.

Abstract: A signal processing method and apparatus for performing special-effects processing on a 1 bit .SIGMA..DELTA. modulated signal in which, for amplitutde limiting a .SIGMA..DELTA. modulated 1-bit digital signal, the 1-bit digital signal is temporarily converted into a multi-bit signal. For re-quantizing the converted multi-bit signal, an integrator constituting a .SIGMA..DELTA. re-modulator is controlled by a limiter. This enables the 1-bit digital signal to be amplitude-controlled in the form of the digital signal without converting the 1-bit digital signal into an analog signal.

Abstract: A sampling rate converting method and apparatus for converting the sampling frequency of a 1-bit digital data obtained a .SIGMA..DELTA. modulator to 32 kHz, 48 kHz, 96 kHz or 192 kHz without producing jitter. A decimation filter 3 decimates the sampling frequency of 1-bit digital data of 2.8224 MHz supplied from an input terminal 2 by 1/2-tuple decimation. An interpolation filter 4 oversamples the frequency of the output of the decimation filter 3 by quintuple oversampling with an integer ratio of 1:5. A decimation filter 5 decimates the frequency of the output of the interpolation filter 4 by 1/21-tuple decimation with an integer ratio of 21:1.

Abstract: A system (400) and apparatus (200, 300) for, and method (100) of, interfacing a demodulator and a forward error correction decoder enables a forward error correction decoder to be used in conjunction with an otherwise incompatible demodulator. Data received from the demodulator having a first encoding and formatted as M bits per baud at a first baud rate is encoded into data having a second encoding. The data having the second encoding is output to the forward error correction decoder as N bits per baud at a second baud rate as required by the forward error correction decoder.

Abstract: When digitized signals are transmitted from a digital transmission system (NET1), e.g. a PDH system, to another digital transmission system (NET2), e.g. a SDH system, which operate at different clock rates (f.sub.1, f.sub.2), the clock rate must be adapted during the transition. To that end, the digitized signals are converted into discrete-time and value-discrete signals in a decoding unit (D1) at the clock rate (f.sub.1) of the one digital transmission system (NET1). A conversion unit (UE1) converts the discrete-time and value-discrete signals into further discrete-time and value-discrete signals, whose pulse repetition rate is adapted to a clock rate derived from the clock rate (f.sub.2) of the other digital transmission system (NET2). This is achieved e.g. with a low-pass filter (FIL1) and a sample-and-hold device (AH1). An encoding unit (K1) converts the further discrete-time and value-discrete signals into digital signals, whose bit rate is adapted to the clock rate (f.sub.

Abstract: A sampling frequency converting device. A memory unit stores an input signal D.sub.si having an input sampling frequency Fsi. An interpolation unit interpolates the readout signal from the storage unit. A sampling frequency ratio detection unit detects the current sampling frequency ratio R.sub.n between the input sampling frequency Fsi and the output sampling frequency F.sub.so and detects a new sampling frequency ratio R.sub.n NEW based on the current sampling frequency ratio R.sub.n and a past detected value R.sub.n-1 preceding the current detected value by one detection period. A control unit having the sampling frequency detection unit controls the storage unit and the interpolating unit from the new sampling frequency ratio R.sub.n NEW.

Abstract: An efficient and power-saving method of converting serial in-phase (I) and quadrature-phase (Q) symbols at the IS-54 standard symbol rate, to time-aligned IQ pairs at the CDPD standard symbol rate. A FIFO buffer stores the serial in-phase (I) and quadrature-phase (Q) symbols at the IS-54 standard symbol rate. A DSP performs CDPD demodulation by reading time-aligned IQ pairs directly from the FIFO buffer, even though the FIFO buffer contains serial in-phase (I) and quadrature-phase (Q) symbols at the IS-54 standard symbol rate. This is accomplished by performing a rate conversion method between the DSP pointer and the FIFO buffer. The rate conversion combines, symbol rate conversion, sample timing alignment, and sign corrections in one calculation, resulting in an efficient method of generating the desired time-aligned IQ pairs at the CDPD symbol rate. A look-up table is used for several of the variables in the rate conversion calculation.

Abstract: According to a data conversion method and apparatus, an original signal is wavelet-transformed with a desired expansion count to generate transformed data. The transformed data is corrected such that a difference between the original signal and a value obtained by inversely wavelet-transforming the transformed data falls within a desired tolerance range, thereby generating the corrected transformed data as compressed data in which the original signal is compressed.

Abstract: A sampling rate conversion apparatus in which according to an area effect correlation method, an input signal having a first sampling rate K is converted into an output signal having a second sampling rate N. The apparatus includes a first data input device for inputting the first sampling rate and a horizontal synchronous signal or an effective pixel start signal and outputting a multiplication accumulation input data sequence generated by an area effect correlation method, a second data input device for outputting an area effect correlation coefficient generated by the area effect correlation method and the second sampling rate, and a multiplier for multiplying the area effect correlation coefficient and the multiplication accumulation input data device so that the input signal having the first sampling rate K is converted into the output signal having the second sampling rate N.

Abstract: A sample rate converter is described for converting an input data stream including a plurality of input samples at one sample rate to an output data stream including a plurality of output samples at another sample rate. The converter uses an interpolation approach that utilizes an integer accumulator to track the timing relation between input samples and output samples. Based on the value of the accumulator, the method determines if the correct input samples are being used to calculate the current output sample. If so, the output sample is calculated as a function of the input samples and the accumulator value. The converter provides the robustness of a table based conversion approach without the need to pre-calculate and store a table, simplifies the calculations involved, and is less sensitive to numeric round off errors.

Abstract: A time division switching matrix capable of effecting rate conversion comprises a plurality of serial inputs for connection to respective serial input links, each capable of carrying time division multiplexed PCM channels, a plurality of serial outputs for connection to respective serial output links, each capable of carrying time division multiplexed PCM channels, and a serial-to-parallel converter associated with each input for converting a serial input stream to parallel format, each said serial-to-parallel converter being independently configurable to produce the same net parallel throughput regardless of the bit rate of the associated input link. The serial-to-parallel converters are staggered length shift registers. The output side of the switching matrix can be similarly configured.

Abstract: A method and an apparatus are provided for generating an (4,20) RLL modulation code having a decreased detectible window width and an increased recording density ratio. The code's spectrum is concentrated in the low-frequency band, thereby improving the signal-to-noise ratio. In addition, the hardware of an encoder and a decoder can be easily implemented since the modulation code has a fixed codeword length.

Abstract: A syntax parsing apparatus produces an effective bit length used in a video decoder which decodes encoded bitstream data. The syntax parsing apparatus includes an input port for receiving encoded bitstream data, and a control command output port for storing data of a plurality of control commands and sequentially selects and outputs the data of each of the plurality of the control commands. A variable-length code table unit selects and outputs either the bitstream data received via the input port or a variable-length code corresponding to the received bitstream data according to the control command data supplied from the control command output port, and outputs a variable-length code length corresponding to the received bitstream data. A data store stores the selected data output from the variable-length code table unit in response to the control command data.

Abstract: A digital oversampling noise-shaping system includes a digital noise-shaped clock signal generating circuit, including a DCO operating at a fixed master clock rate, that receives a digital input sample clock signal having an input sample rate and produces a noise-shaped clock signal having a variable rate with an average rate equal to a multiple of the input sample rate. In one embodiment, an interpolator is coupled to the clock signal generating circuit and receives the digital input samples at an input sample rate and, responsive to the noise-shaped clock signal, upsamples the digital input samples at the variable rate. A hold circuit repeats the interpolated samples at the master clock rate. A digital noise-shaping circuit, coupled to the hold circuit, performs digital noise-shaping on the repeated samples received from the hold circuit. In another embodiment, a decimator is coupled to the clock signal generating circuit.

Abstract: A digital-to-analog (D/A) converting apparatus for converting digital data to an analog signal is provided. Specifically, the apparatus contains a sampling rate converting circuit, an interpolator, a digital sigma-delta demodulation circuit, and an analog D/A converter. The converting circuit inputs and converts the digital data into sampled digital data. Then the interpolator interpolates the sampled digital data to produce interpolated data. Also, the interpolator has an infinite impulse response (IIR) filter which performs an IIR filtering operation based on the sampled digital data to produce the interpolated data. The demodulation circuit inputs the interpolated data, performs a sigma-delta demodulation operation on the interpolated data, and outputs corresponding demodulated data. Then, the analog D/A converter converts the demodulated data to the analog signal. By using the interpolator and the demodulation circuit, the structure of the converting apparatus is relatively simple.

Abstract: A data encoding method and apparatus are provided for implementing a predefined rate code, such as a 16/17 rate code for a data detection channel in a direct access storage device. A binary data stream is received and sequential symbols of the received binary data stream are identified. Sequential alternate symbols of the binary data stream are encoded into first codewords. Sequential alternate other symbols are encoded into second codewords. The alternating first and second codewords are sequentially combined. For a rate 16/17 rate code, the first codewords include 9-bit codewords and the second codewords include 8-bit codewords. The second 8-bit codewords are either raw symbols of the received binary data stream or remapped symbols of the received binary data stream. All likely error events are limited to within three consecutive bytes in a user data stream with a 16/17 rate code of the preferred embodiment.

Abstract: A re-sampling circuit includes a poly-phase finite impulse response (FIR) interpolator; a polynomial interpolator having a sample input connected to a sample output of the poly-phase FIR interpolator; and a numerically controlled oscillator (NCO) having an output partitioned into: Nc integer bits connected to a control input of the FIR interpolator, and Nf fractional bits connected to a control input of the polynomial interpolator. The circuit may also include a reference clock for generating a reference clock signal. The NCO preferably further comprises a sample clock generator for generating a sample clock signal based on the reference clock signal, and the FIR interpolator further has a sample clock input for receiving the sample clock signal from the sample clock generator.

Abstract: Low-redundancy codes are increasingly being striven for, such codes thus inevitably requiring comparatively long code words. However, since the memory requirement for coding tables increases considerably with the length of the code words, the use of code tables is then no longer expedient. Instead, coding is then effected by selecting the optimum code word in each case from a plurality of different code words taking account of coding; prescriptions and spectral decisions. For this purpose, the maximum run length for each code word is also determined, inter alia, but the spectral decisions are decisive as long as the maximum run length does not exceed a predetermined maximum value. Provided that the end of one code word and the beginning of a succeeding code word have the same binary value, incorrect decisions in the selection of the optimum code word may arise in the region where the synchronizing pattern is keyed in.

Abstract: A sampling frequency converting device. A memory unit stores an input signal D.sub.si having an input sampling frequency Fsi. An interpolation unit interpolates the readout signal from the storage unit. A sampling frequency ratio detection unit detects the current sampling frequency ratio Rn between the input sampling frequency Fsi and the output sampling frequency F.sub.so and detects a new sampling frequency ratio R.sub.n NEW. based on the current sampling frequency ratio R.sub.n and a past detected value R.sub.n-1 preceding the current detected value by one detection period. A control unit having the sampling frequency detection unit controls the storage unit and the interpolating unit from the new sampling frequency ratio R.sub.n NEW.

Abstract: Modem-equipped computers which can initiate an audio channel using the modem data connection. The connection is initiated with a new protocol called the voice-over-data protocol. The new protocol does not require any additional modem hardware or telephone line features, and is not tied to any proprietary hardware/software compression or transmission schemes. The voice-over-data protocol negotiates an audio compression/decompression scheme and then sets up an audio channel over an existing data connection using a socket. Compressed audio data is then delivered to the remote computer where it is decompressed and output. The voice-over-data protocol significantly reduces the latency which disrupts normal speech patterns when voice data is sent over a data connection. This protocol also reduces the bandwidth required to send voice over a data connection.

Abstract: The off-state of the binary transitions is used in order to possibly generate symmetrical transitions of the active state of the binary transitions in relation to the off-state, in order to replace the two-state logic of at least one binary transition capable to go to the rest-state by a three-state logic.

Abstract: Data converter (10, 50, 150, 200) and method (250, 300) operate at variable sampling rates. Input gain stage (12) adjusts input bit stream (18) at an input bit rate (20) to produce gain adjusted bit stream (22). Integrator (14) and comb filter (16) operate on the gain adjusted bit stream (22) to produce a filtered bit stream (28) at an output bit rate (24). The gain of the integrator (14) and comb filter (16) pair varies with the sampling rates implemented. An input gain value of the input gain stage (12) adjusts to compensate for the gain of the integrator (14) and comb filter (16) pair to produce the filtered bit stream (28) within a predetermined dynamic range. DC offset stage (52) and output gain stage (54) provide further adjustment to the filtered bit stream (28). Data converters (10, 50) and method (250) convert data from a higher frequency bit rate to a lower frequency bit rate. Data converters (150, 200) and method (300) convert data from a lower frequency bit rate to a higher frequency bit rate.

Abstract: When digital audio data is input, the data is temporarily stored in a ring buffer memory. A clock generator adjusts an output transfer clock cycle so that the difference between the count of an address counter for writing data and the count of an address counter for reading data always falls within a predetermined range. An input rate calculating circuit calculates an average transfer rate at which the input data is transferred. The clock generator increases or decreases the transfer rate of the output data so that the average transfer rate of the output data becomes equal to the average transfer rate of the input data. Consequently, a fluctuation of the transfer rate of the output data is prevented, and thus deterioration of the quality of output signals of digital data is prevented. Moreover, reproduction of output signals becomes available with the use of a synchronous sampling rate converter.

Abstract: Source data each consisting of m-bits can be converted into conversion codes each consisting of n (>m) bits with ease, and reverse conversion thereof can be performed with ease. The code conversion and the reverse conversion can be characterized in terms of a series of tables.The current input source data and the next input source data are respectively taken in by registers. Whether or not the run length at a connecting portion between consecutive source data satisfies conditions is determined by a control unit, and a table to be used is selected to finally obtain a conversion code.

Abstract: A method and apparatus for compressing a block of data using a shared dictionary. Data to be compressed is divided into subblocks which are each provided to a respective compressor in a plurality of compressors. The compressors cooperatively construct a dynamic compression dictionary and compress the subblocks in parallel using the dictionary. Compressed subblocks output by the compressors are concatenated to form a compressed block.

Abstract: An asynchronous digital mixer (20) receives digitally sampled audio signal data at different unrelated asynchronous sampling rates. The audio data is then edge synchronized and mixed using a summing element (28) and an oversampled sigma delta digital modulator (42), where a single bit output of the digital modulator (42) can be output as an analog signal with the use of a smoothing filter (46), or further decimated using a digital decimation filter (44) for storage on a digital media. Additionally, analog audio signals can be converted and mixed digitally within the system using an analog interface (35) without having to decimate and filter each analog input signal individually.

Abstract: A sampling rate converting method and apparatus for converting the sampling frequency of a 1-bit digital data obtained by a .SIGMA..DELTA. modulator to 32 kHz, 48 kHz, 96 kHz or 192 kHz without producing jitter. A decimation filter 3 decimates the sampling frequency of 1-bit digital data of 2.8224 MHz supplied from an input terminal 2 by 1/21-tuple decimation. An interpolation filter 4 oversamples the frequency of the output of the decimation filter 3 by quintuple oversampling with an integer ratio of 1:5. A decimation filter 5 decimates the frequency of the output of the interpolation filter 4 by 1/21-tuple decimation with an integer ratio of 21:1.

Abstract: An integrated digital communication system utilizing multilevel vestigial sideband transmission is provided. The communication system receives a multi-level pulse-amplitude modulated digital signal from a limited bandwidth channel. The system includes processing stages which demodulate, sample and filter the incoming signal prior to recovery of the digital data. Other stages recover the timing and lock on to the frequency and phase of the transmitted signal, as well as provide for automatic gain control. An adaptive equalizer, error correction circuitry, and an output interface recover the digital data and provide for transfer to other devices.

Abstract: A 1:N divider 40 divides an input high rate data signal into N (N being 2 or greater integer) division data signals. Data transmission rate converters 70.sub.1 -70.sub.N for converting the transmission rate of each of the N division data signals. The respective N division data signals are transmitted through N transmission lines 30.sub.1 -30.sub.n. A multiplier 50 multiplies the transmitted N division data signals into a single high rate data signal.

Abstract: A method and apparatus for digital to analog conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that errors produced by nonuniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques In one embodiment, the digital data is interpolated by a fixed ratio and then decimated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the incoming digital data stream. In another embodiment, the digital data is interpolated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the incoming digital data stream and then decimated by a fixed ratio. The frequency signal selection number is modulated using an n-th order m-bit sigma-delta modulator.

Abstract: A method of converting GMSK modulated signals arriving at an integer multiple of the IS-54 standard sampling (or symbol) rate (24.3 KHz) to GMSK modulated signals at an integer multiple of the CDPD standard sampling rate (19.2 KHz). In the preferred embodiment, the GMSK signals arrive as serial in-phase (I) samples and quadrature-phase (Q) samples at the IS-54 sampling rate. The method of the present invention combines into one calculation the following operations 1) time-alignment of the serial I and Q samples into IQ pairs, 2) conversion of the time-aligned IQ pairs to the CDPD sampling rate of 4.times.19.2 KHz, and 3) sign correction of each time-aligned IQ pair. Because of the periodic nature of certain variables in the above calculation, efficiency is further achieved with the present invention by storing tables containing the possible values of these variables, then using pointers to access the stored values as needed, thereby saving considerable processing power and time.