Abstract: A multi-mode parallel 3-D graphics system having multiple graphics processing pipelines with multiple GPUs supporting a parallel graphics rendering process having time, frame and object division modes of operation, wherein each GPU comprises video memory, a geometry processing subsystem and a pixel processing subsystem, and wherein 3D scene profiling is performed in real-time, and the parallelization state/modes of the system are dynamically controlled to meet graphics application requirements. The multiple modes of parallel graphics rendering use real-time graphics application profiling, and dynamic control over time-division, frame-division, and object-division modes of parallel operation, within the same parallel graphics platform, which can be realized on PC-based computing system architectures.

Abstract: A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of receiving a common input stream, tracking a periodic event associated with the common input stream, generating a plurality of fragment streams from the common input stream, inserting a marker based on an occurrence of the periodic event in a first fragment stream in the multiple fragment streams, and utilizing the marker to influence the processing of the first fragment stream so that a plurality of raster operation (ROP) request streams maintains substantially the same coherence as the common input stream. Each fragment stream is independently processed and corresponds to one of the ROP request streams.

Abstract: In a media server for processing data packets, media server functions are implemented by a plurality of modules categorized by real-time response requirements.

Abstract: Systems and methods for assembling pixel shader program threads for execution based on resource limitations of a multithreaded processor may improve processing throughput. Pixels to be processed by the pixel shader program are assembled into a launch group for processing by the multithreaded processor as multiple shader program threads. The pixels are assembled based on parameter storage resource limitations of the multithreaded processor so that common parameters shared by multiple pixels are not stored separately for each pixel. Therefore, the limited parameter storage resources are efficiently used, allowing more shader program threads to execute simultaneously.

Abstract: A centralised game server in a bank (50) of game servers runs a game program for use by a user at a remote terminal (52, 56, 58). In the game server, the game program sends a first set of graphics instructions to a first graphics processing unit (76) which is intercepted by an instruction interception module (74). The first set of instructions, including vertex data, transformation data and texture data are passed to the first graphics processing unit (76) while a specially manipulated version of the instructions is generated and passed to a second graphics processing unit (78). The first graphics processing unit (76) renders the image data as the game intended while the second graphics processing unit (78) is used to render specially adapted graphics data from which to extract compression assistance data used for compression, e.g. motion vectors.

Abstract: Systems and methods for balancing a load among multiple graphics processors that perform different portions of a rendering task. A rendering task is partitioned into portions for each of two (or more) graphics processors. The graphics processors perform their respective portions of the rendering task and return feedback data indicating completion of the assigned portion. Based on the feedback data, an imbalance can be detected between respective loads of two of the graphics processors. In the event that an imbalance exists, the rendering task is re-partitioned to increase the portion assigned to the less heavily loaded processor and to decrease the portion assigned to the more heavily loaded processor.

Abstract: A system, method, and computer program product are provided for generating a ray tracing data structure utilizing a parallel processor architecture. In operation, a global set of data is received. Additionally, a data structure is generated utilizing a parallel processor architecture including a plurality of processors. Such data structure is adapted for use in performing ray tracing utilizing the parallel processor architecture, and is generated by allocating the global set of data among the processors such that results of processing of at least one of the processors is processed by another one of the processors.

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: The present invention relates to a data processing apparatus provided with a multi-graphic controller and a data processing method using the data processing apparatus. A data processing apparatus of the present invention comprises a first graphic controller 10a and a second graphic controller 20 for processing and displaying inputted image data; and a control unit 50 for distributing the image data in consideration of data processing capabilities of the first and second graphic controllers 10a and 20. According to the present invention, there is provided a data processing apparatus and method capable of simultaneously using a plurality of graphic controllers, so that data processing speed can be improved. Image data are appropriately distributed, whereby the efficiency of data processing can be enhanced.

Abstract: A system, method, and computer program product are provided for preventing display of unwanted content stored in a frame buffer. In use, unwanted content stored in a frame buffer is identified. Furthermore, display of the unwanted content is prevented based on the identification of the unwanted content.

Abstract: A system, method, and computer program product are provided for selecting a ray tracing entity from a group of ray tracing entities for processing by a parallel processing architecture. In operation, it is determined whether at least one thread in a parallel processing architecture has completed processing a ray tracing entity. Further, an additional ray tracing entity is selected from a group of ray tracing entities for processing by the parallel processing architecture, based on the determination.

Abstract: Embodiments of the present invention are directed to techniques for providing an environment for the efficient execution of recognition tasks. A novel environment is provided which automatically and efficiently executes a recognition program on as many computer processors as available. This program, deconstructed into separate tasks, may be executed by constructing a dependency network from known inputs and outputs of the tasks, applying project planning methods for scheduling these tasks into multiple processing threads, and dynamically assigning tasks within these threads to processors. Therefore, an efficient schedule of tasks to complete a recognition program can be created and executed automatically, for any type of recognition problem.

Abstract: Disclosed are methods and systems for granting an application-specific integrated circuit (ASIC) in a multi-ASIC environment controlled access to a shared resource. A system includes a first ASIC, a second ASIC, and a shared memory that stores a shared resource and a data set partitioned into fields. The first ASIC writes data to a first subset of the fields and reads data from the fields. The first ASIC includes first logic that computes a first value based on the data read from the fields. The second ASIC writes data to a second subset of the fields and reads data from the fields. The second ASIC includes second logic that computes a second value based on the data read from the fields. Based on the first and second values respectively computed by the first and second logic, only one of the first and second ASICs gains access to the shared resource.

Abstract: Task and data management systems methods and apparatus are disclosed. A processor event that requires more memory space than is available in a local storage of a co-processor is divided into two or more segments. Each segment has a segment size that is less than or the same as an amount of memory space available in the local storage. The segments are processed with one or more co-processors to produce two or more corresponding outputs. The two or more outputs are associated into one or more groups. Each group is less than or equal to a target data size associated with a subsequent process.

Abstract: Intermediate target(s) are utilized in connection with computer graphics in a computer system. In various embodiments, intermediate memory buffers in video memory are utilized to allow serialized programs from graphics APIs to support algorithms that exceed the instruction limits of procedural shaders for single programs. The intermediate buffers may also allow sharing of data between programs for other purposes as well, and are atomically accessible. The size of the buffers, i.e., the amount of data stored in the intermediate targets, can be variably set for a varying amount of resolution with respect to the graphics data. In this regard, a single program generates intermediate data, which can then be used, and re-used, by an extension of the same program and/or any number of other programs any number of times, enabling considerable flexibility and complexity of shading programs, while maintaining the speed of modern graphics chips.

Abstract: A method and apparatus employing selectable hardware accelerators in a data driven architecture are described. In one embodiment, the apparatus includes a plurality of processing elements (PEs). A plurality of hardware accelerators are coupled to a selection unit. A register is coupled to the selection unit and the plurality of processing elements. In one embodiment, the register includes a plurality of general purpose registers (GPR), which are accessible by the plurality of processing elements, as well as the plurality of hardware accelerators. In one embodiment, at least one of the GPRs includes a bit to enable a processing element to enable access a selected hardware accelerator via the selection unit.

Abstract: A method to perform compositing of three-dimensional images includes, on a Central Processing Unit (CPU), automatically assembling a Graphics Processing Unit (GPU) program for each element of a plurality of image elements. The GPU program for each element is to apply at least one effect to the respective image element. The plurality of image elements, and the associated GPU programs, is communicated from the CPU to a GPU.

Abstract: A graphics processing subsystem for use in a computing system, including a plurality of GPUs operating according to time division mode of graphics parallelization. At least one of the GPUs is a display-designated GPU that is connectable to a screen for displaying images produced by the graphics processing subsystem, and at least one of the GPUs is a non-display-designated GPU. The subsystem includes a hardware hub having a router, and being located between a CPU of the computing system and the plurality of GPUs. For images to be generated and displayed on the screen, the router directs to the plurality of GPUs successively a stream of geometric data and graphics commands. The geometric data and graphics commands directed to a non-display-designated GPU are processed by the GPU into image pixel data associated with a frame, the image pixel data is then redirected to the router, the image pixel data is then redirected to the display-designated GPU, and the image pixel data is then displayed on the screen.

Abstract: A method of performing a blit operation in a parallel processing system includes dividing a blit operation into batches of pixels, performing reads of pixels associated with a first batch in any order, confirming that all reads of pixels associated with the first batch are completed, and performing writes of pixels associated with the first batch in any order. The pixels of the first batch and pixels of additional batches are applied to parallel processors, where the parallel processors include a corral defined by entry points and exit points distributed across the parallel processors.

Abstract: A system, method, and computer program product are provided for postponing the execution of primitive intersection. In operation, at, least one node traversal operation and at least one primitive intersection operation is executed, utilizing a parallel processing architecture. Additionally, the execution of the at least one primitive intersection operation is postponed.

Abstract: A device for processing a data stream originating from a device generating matrices of N1 rows by Nc columns of data includes K computation tiles and interconnection means for transferring the data stream between the computation tiles. At least one computation tile includes: one or more control units to provide instructions, n processing units, each processing unit carrying out the instructions received from a control unit on a neighborhood of V1 rows by Vc columns of data, a storage unit to place the data of the stream in the form of neighborhoods of V1 rows by (n+Vc?1) columns of data. The storage unit includes a block of shaping memories of dimension V1×Nc and a block of neighborhood registers of dimension V1×(n+Vc?1), an input/output unit to convey the data stream between the interconnection means and the storage unit on the one hand, and between the processing units and the interconnection means on the other hand.

Abstract: Embodiments of the invention provide assigning two different class identifiers to a device to allow loading to an operating system as different devices. The device may be a graphics device. The graphics device may be integrated in various configurations, including but not limited to a central processing unit, chipset and so forth. The processor or chipset may be associated with a first identifier associated with a graphics processor and a second device identifier that enables the processor or chipset as a co-processor.

Abstract: A system and method for applying non-homogeneous properties to multiple video processing units (VPUs) in a multiple VPU system are described. Respective VPUs in the system cooperate to produce a frame to be displayed. In various embodiments, data output by different VPUs in the system is combined, or merged, or composited to produce a frame to be displayed. In load balancing modes, each VPU in the system performs different tasks as part of rendering a same frame, and therefore typically executes different commands. In various embodiments, efficiency of the system is enhanced by forming a single command buffer for execution by all of the VPUs in the system even though each VPU may have a different set of commands to execute in the command buffer.

Abstract: The present disclosure describes implementations for processing instructions and data across multiple Arithmetic Logic Units (ALUs). In one implementation, a graphics processing apparatus comprises a plurality of ALUs configured to process independent instructions in parallel. Pre-processing logic is configured to receive instructions and associated data to be directed to one of the plurality of ALUs for processing from a register file, the pre-processing logic being configured to selectively format received instructions for delivery to a plurality of the ALUs. In addition, post-processing logic is configured to receive data output from the plurality of the ALUs and deliver the received data to the register file for write-back, the post-processing logic being configured to selectively format data output from a plurality of the ALUs for delivery to the register file as though the data had been output by a single ALU.

Abstract: Multichip graphics processing subsystems include at least three distinct graphics devices (e.g., expansion cards) coupled to a high-speed bus (e.g., a PCI Express bus) and operable in a distributed rendering mode. One of the graphics devices provides pixel data to a display device, and at least one of the other graphics devices transfers the pixel data it generates to another of the devices via the bus to be displayed. Where the high-speed bus provides data transfer lanes, allocation of lanes among the graphics devices can be optimized.

Abstract: A method and system for minimizing an amount of data needed to test data against subarea boundaries in spatially composited digital video. Spatial compositing uses a graphics unit or pipeline to render a portion (subarea) of each overall frame of digital video images. This reduces the amount of data that each processor must act on and increases the rate at which an overall frame is rendered. Optimization of spatial compositing depends on balancing the processing load among the different pipelines. The processing load typically is a direct function of the size of a given subarea and a function of the rendering complexity for objects within this subarea. Load balancing strives to measure these variables and adjust, from frame to frame, the number, sizes, and positions of the subareas. The cost of this approach is the necessity to communicate, in conjunction with each frame, the graphics data that will be rendered. Graphics data for a frame is composed of geometry chunks.

Abstract: In a graphics processing device, a plurality of processors write fragment shading results for order-dependent data to a buffer, according to the order in which the data is received. Fragment shading results for order-neutral data is written to the buffer one batch at a time. The order-dependent data comprises spatially overlapping data. Order-neutral data may not overlap. A scheduler controls the order of reception of one batch of data at a time by the processors. The order for receiving the order-dependent data may be determined. The plurality of processors may process the data in parallel. A writing order for writing results to a buffer from the processing in parallel, may be enforced. A portion of the processors may be instructed to wait before writing results to the buffer in a specified order. Processors signal when writing results to the buffer is complete.

Abstract: A drawing apparatus includes a reception unit, a first holding unit and a drawing processing unit. The reception unit receives graphic information. The first holding unit holds a plurality of first data which is a part of the graphic information received by the reception unit, in association with identification numbers assigned to the first data. The drawing processing unit draws a graphic on the basis of the first data held in the first holding unit. The drawing processing unit uses the plurality of the first data in a same task to draw the graphic. The reception unit records the identification numbers of the first data and a synchronization flag in order of reception. The synchronization flag is set for the first data received first among the plurality of first data processed by the same task in the drawing processing unit.

Abstract: In a video matrix display interface, an interface includes one or more subsystems to receive information from a plurality of display devices, compile the information from the plurality of display devices, report the compiled information to a graphics processing device, generate a video image using the compiled information, the image to be viewable across the plurality of display devices, splice the video image into portions and transmit the video image portions to the plurality of display devices, thereby creating a continuous image across the plurality of display devices.

Abstract: An image display device includes an operation unit having a plurality of operating members configured to input operation data indicative of content of a user's operation; an operation data storage unit configured to store the operation data; an application process execution unit configured to execute a predetermined application process based on the operation data; an information screen display operation detection unit configured to detect a predetermined information screen display operation; an information screen display unit configured to display an information screen in a display unit when the information screen display operation detection unit detects information screen display operation; and an operation invalidation flag storage unit configured to store an operation invalidation flag in a manner in which it corresponds to a part or all of the operation data when the operation data satisfies a predetermined condition during the information screen is displayed.

Abstract: A data processing apparatus includes a plurality of processing units each performing a respective one of process parts into which a predetermined process to be performed on data is divided, and a changing unit that changes a connection between the plurality of processing units on the basis of setting parameters that are set to enable a plurality of types of processing procedures.

Abstract: A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller.

Abstract: Dynamic processor allocation is implemented based upon bitmap data density. A bitmap index is used to process the query. A bitmap is created for the query. The bitmap is partitioned into single I/O operations. A variable partition size is provided based upon data density. Data density for each partition is calculated. Processors are assigned based upon data density of each partition. Then the partitions are processed and query results are returned.

Abstract: A device for the graphical generation of symbologies intended for a display screen, the device having functions for the generation of symbology elements and means for monitoring its correct operation. The monitoring of correct operation allowing the use of certain of the functions for the generation of symbology elements to be prohibited and micro-images dedicated to the monitoring of the functions to be generated and controlled.

Abstract: A server apparatus and a server control method which transmits display data to a client apparatus and which displays the display data on a display screen of the client apparatus, wherein there are provided a plurality of accelerators, each of the plurality of accelerators being equipped with a difference detection circuit which compares the display data for a previous screen transmitted to the client apparatus with the display data for a current screen to be transmitted to the client apparatus to detect a difference therebetween. Then, the size of a drawing area to be allocated to each of the plurality of accelerators is calculated for each of the accelerators in response to a request from the client apparatus, and when a display request is made from a new client apparatus, the accelerator having a smaller drawing area among the calculated drawing areas is allocated to the new client apparatus.

Abstract: A system, method, and computer program product are provided for executing node traversal or primitive intersection using a parallel processing architecture. In operation, it is determined whether a plurality of threads in a parallel processing architecture are to execute node traversal or primitive intersection. Additionally, the node traversal or the primitive intersection is executed, based on the determination.

Abstract: The semiconductor device having task processing units which perform predetermined functional processes and are capable of freely accessing memories independently of each other, includes: the task processing units provided on the semiconductor substrate and configured to select at least one of the memories independently of each other and issue requests for memory access to the selected memory; and memory control units which are capable of operating independently of each other, correspond to the respective memories independently of each other, and are each configured to arbitrate the requests for memory access from the task processing units and connect, to the respective memories, the task processing units which have issued the arbitrated requests for memory access so that data can be transferred between the task processing units and the memories.

Abstract: A computing system employing a multi-GPU graphics processing and display subsystem supporting single-GPU non-parallel (i.e. multi-tasking) and multi-GPU parallel application-division modes of graphics processing operations, in order to execute graphic commands and process graphics data (GCAD) render pixel-composited images containing graphics for display on a display device during the run-time of the multiple graphics-based applications, while managing and conserving electrical power and graphics processing resources. An automatic mode control module (AMCM) analyzes the application profiles assigned to graphics applications running on the computing system, and automatically controls the mode of operation of the multi-GPU graphics processing and display subsystem during the run-time of the multiple graphics-based applications.

Abstract: An image forming apparatus and a control method thereof. The image forming apparatus includes a plurality of image processors which process an image to be formed on a printing medium corresponding to a plurality of colors, a processor which executes an interrupt routine with respect to the plurality of image processors, and a controller which generates an interrupt signal and transmits the interrupt signal to the processor if at least two of the plurality of image processors generate interrupt requests so that the processor executes the interrupt routine.

Abstract: A1A system embodying the invention includes a controlling device and a set of rendering devices, with the effect that the controlling device can distribute a set of objects to the rendering devices. Each rendering device computes a (2D) image in response to the objects assigned to it, including computing multiple overlapping images and using a graphics processor to blend those images into a resultant image. To interface with the graphics processor, each rendering device spoofs the ?-value with a pixel feature other than opacity (opacity is expected by the graphics processor), with the effect that the graphics processor delivers useful ?-values, while still delivering correct color values, for each pixel. This has the effect that the resultant images include transparency information sufficient to combine them using transparency blending.

Abstract: A circuit arrangement and method support a multithreaded rendering architecture capable of dynamically routing pixel fragments from a pixel fragment generator to any pixel shader from among a pool of pixel shaders. The pixel fragment generator is therefore not tied to a specific pixel shader, but is instead able to utilize multiple pixel shaders in a pool of pixel shaders to minimize bottlenecks and improve overall hardware utilization and performance during image processing.

Abstract: Disclosed is a system and method for determining, in parallel on a graphics processing unit, a block compression case which results in a least error to a block. Once determined, the block compression case may be used to compress the block.

Abstract: In typical embodiments a three GPU configuration is provided comprising three discrete video cards, each connected to a standard monitor placed horizontally for a 3× horizontal resolution. In this configuration, depending on the load on each GPU, the vertical split lines are dynamically adjusted. To adjust the load balancing according to these virtual split lines, the rendering clip rectangle of each GPU is adjusted, in order to reduce the number of pixels rendered by the heavily loaded GPU. These split lines define the boundary of the scene to be rendered by each GPU, and, according to some embodiments, may be moved horizontally. Thus for example if a GPU has a more complex rendering clip polygon to render than the other GPUs, the neighboring GPUs may render the rendering clip polygon it displays plus a portion of the rendering clip polygon to be displayed by heavily loaded GPU.

Abstract: This invention relates to an information-signal-processing apparatus etc. for performing a series of processing pieces by using plural functional blocks in response to any information signals, in which functions can be easily upgraded through version upgrading of the functional blocks. Control block 110 issues a common command and transmits it to a control block 120 via a control bus 111. Control I/F 120 of the functional block 120 converts this common command into an intra-functional-block command if the common command is the common command related to its own functional block, and supplies the functional section 120e with it. This enables the functional block 120 to operate adaptively in accordance with the common command. When performing upgrade of the functions by the version updating of a predetermined function block, the common command need not be changed.

Abstract: A method for a computer system includes determining a plurality of illumination modes associated with a plurality of scene descriptors, wherein the plurality of scene descriptors includes a first scene descriptor and a second scene descriptor, determining a first plurality of weights, wherein each weight from the first plurality of weights is associated with an illumination mode from the plurality of illumination modes, determining illumination data associated with the first scene descriptor in response to the first plurality of weights and in response to the plurality of illumination modes, determining a second plurality of weights, wherein each weight from the second plurality of weights is associated with an illumination mode from the plurality of illumination modes, and determining illumination data associated with the second scene descriptor in response to the second plurality of weights and in response to the plurality of illumination modes.

Abstract: A technique for performing stream output operations in a parallel processing system is disclosed. A stream synchronization unit is provided that enables the parallel processing unit to track batches of vertices being processed in a graphics processing pipeline. A plurality of stream output units is also provided, where each stream output unit writes vertex attribute data to one or more stream output buffers for a portion of the batches of vertices. A messaging protocol is implemented between the stream synchronization unit and the plurality of stream output units that ensures that each of the stream output units writes vertex attribute data for the particular batch of vertices distributed to that particular stream output unit in the same order in the stream output buffers as the order in which the batch of vertices was received from a device driver by the parallel processing unit.

Abstract: Parallel processing for distance transforms is described. In an embodiment a raster scan algorithm is used to compute a distance transform such that each image element of a distance image is assigned a distance value. This distance value is a shortest distance from the image element to the seed region. In an embodiment two threads execute in parallel with a first thread carrying out a forward raster scan over the distance image and a second thread carrying out a backward raster scan over the image. In an example, a thread pauses when a cross-over condition is met until the other thread meets the condition after which both threads continue. In embodiments distances may be computed in Euclidean space or along geodesics defined on a surface. In an example, four threads execute two passes in parallel with each thread carrying out a raster scan over a different quarter of the image.

Abstract: A method of controlling the mode of parallel operation of a multi-mode parallel graphics processing system (MMPGPS) embodied within a host computing system having (i) host memory space (HMS) for storing one or more graphics-based applications and a graphics library for generating graphics commands and data (GCAD) during the run-time (i.e. execution) of the graphics-based application, (ii) one or more CPUs for executing said graphics-based applications, (iii) a display device for displaying images containing graphics during the execution of said graphics-based applications, and (iv) a multi-mode parallel graphics rendering subsystem supporting multiple modes of parallel operation selected from the group consisting of object division, image division, and time division and having a plurality of graphic processing pipelines (GPPLs) supporting a parallel graphics rendering process that employs one of the object division, image division and/or time division modes of parallel operation.

Abstract: A chipset is electrically connected with an external graphic module, which generates a first graphic signal and outputs it to the chipset. The chipset includes an internal graphic module and a control module. The internal graphic module generates a second graphic signal, and the control module receives the first graphic signal and the second graphic signal. The control module divides the first graphic signal into at least two first graphic sub-signals and divides the second graphic signal into at least two second graphic sub-signals, respectively. When under a first output mode, the control module simultaneously outputs one of the first graphic sub-signals and one of the second graphic sub-signals.

Abstract: The present invention is a digital electronic system for rendering a volume image in real time. The system accelerators the processing of voxels through early ray termination and space leaping techniques in the projection guided ray casting of the voxels. Predictable and regular voxel access from high-speed internal memory further accelerates the volume rendering. Through the acceleration techniques and devices of the present invention real-time rendering of parallel and perspective views, including those for stereoscopic viewing, are achieved.