Abstract: The present disclosure relates to the field of players, and provides a portable multimedia player includes a housing; an integrated circuit module received in the housing for playing multimedia; a storage device interface electrically connected to the integrated circuit module, and configured to connect to an external storage device; and a male HDMI connector electrically connected to the integrated circuit module, configured to be connected to a female HDMI of an external display device. The multimedia function of the external display device is expanded by connecting the male HDMI 11 to the female HDMI of the external display device. The portable multimedia player is connected to the display device without any corresponding interface cable, such that it affords convenient using to users and beautiful appearance.

Abstract: A data processing architecture includes multiple processors connected in series between a load balancer and reorder logic. The load balancer is configured to receive data and distribute the data across the processors. Appropriate ones of the processors are configured to process the data. The reorder logic is configured to receive the data processed by the processors, reorder the data, and output the reordered data.

Abstract: A parallel processing subsystem includes a plurality of general processing clusters (GPCs). Each GPC includes one or more clipping, culling, viewport transformation, and perspective correction engines (VPC). Since VPCs are distributed per GPC, each VPC can process graphics primitives in parallel with the other VPCs processing graphics primitives.

Abstract: Methods and systems for allocating workloads in a pixel sequential rendering system comprising a plurality of processors are disclosed. Such workloads typically comprise a raster pixel image comprising a plurality of graphical objects. For each scan line (540) of the raster pixel image (510), edges of the plurality of graphical objects (520, 525) that intersect with a current scan line (540) of the raster pixel image (510) are identified in a predetermined order. Spans of pixel locations on the current scan line, each defined by an adjacent pair of edges of the identified edges, are divided into segments (503, 504), one of which comprises varying pixel values. The segments (503, 504) are allocated independently of existing workloads of the processors to respective ones of the processors or processor cores for rendering.

Abstract: Systems, methods, and computer-readable media for optimizing emulated fixed-function and programmable graphics operations are provided. Data comprising fixed function and programmable states for an image or scenario to be rendered is received. The data for the image is translated into operations. One or more optimizations are applied to the operations. The optimized operations are implemented to render the scenario.

Abstract: A mapping engine maps general processing clusters (GPCs) within a parallel processing subsystem to screen tiles on a display screen based on the number of enabled streaming multiprocessors (SMs) within each GPC. A given GPC then generates pixels for the screen tiles to which the GPC is mapped. One advantage of the disclosed technique is a given GPC performs a fraction of the processing tasks associated with the parallel processing subsystem that is roughly proportional to the fraction of SMs included within the GPC.

Abstract: Systems and methods for layering multiple graphics planes on top of a compressed video signal are disclosed herein. A processed video stream is received from a video processing path, wherein the processed video stream comprises a stream of video macroblocks. A composite graphics plane is received from a graphics processing path, wherein the composite graphics plane comprises a set of graphics macroblocks. The composite graphics plane comprises a plurality of layered graphics planes. The composite graphics plane is layered on top of the processed video stream to generate an output video stream. Layering comprises blending a video macroblock from the stream of video macroblocks with a graphics macroblock from the set of graphics macroblocks. By layering one macroblock at time, graphics overlay can occur in real time or faster than real time as the compressed input stream is received.

Abstract: A system and method for facilitating increased graphics processing without deadlock. Embodiments of the present invention provide storage for execution unit pipeline results (e.g., texture pipeline results). The storage allows increased processing of multiple threads as a texture unit may be used to store information while corresponding locations of the register file are available for reallocation to other threads. Embodiments further provide for preventing deadlock by limiting the number of requests and ensuring that a set of requests is not issued unless there are resources available to complete each request of the set of requests. Embodiments of the present invention thus provide for deadlock free increased performance.

Abstract: Multiple graphics processors in a graphics processing system are interconnected in a unidirectional or bidirectional ring topology, allowing pixels to transferred from any one graphics processor to any other graphics processor. The system can automatically identify one or more “master” graphics processors to which one or more monitors are connected and configures the links of the ring such that one or more other graphics processors can deliver pixels to the master graphics processor, facilitating distributed rendering operations. The system can also automatically detect the connections or lack thereof between the graphics processors.

Abstract: The present invention provides an apparatus that includes a network-enabled graphics processing unit. In one embodiment, the apparatus includes integrated circuit that includes a graphics processing element, a media fragmentation engine, and a network interface controller for conveying packets to or from the integrated circuit. The media fragmentation engine translates between a packet format used by the network interface and a graphics format used by the graphics processing element.

Abstract: A three-dimensional (3D) image processor and processing method are described. The 3D image processor includes a space division unit to divide a virtual object space where a virtual 3D object is located into a plurality of sub-spaces, and a plurality of processors to correspond to each of the divided sub-spaces and to compute a trajectory of a ray within each of the corresponding sub-spaces, the ray being transmitted into each of the corresponding sub-spaces.

Abstract: In some aspects, systems and methods provide for forming groupings of a plurality of independently-specified computation workloads, such as graphics processing workloads, and in a specific example, ray tracing workloads. The workloads include a scheduling key, which is one basis on which the groupings can be formed. Workloads grouped together can all execute from the same source of instructions, one or more different private data elements. Such workloads can recursively instantiate other workloads that reference the same private data elements. In some examples, the scheduling key can be used to identify a data element to be used by all the workloads of a grouping. Memory conflicts to private data elements are handled through scheduling of non-conflicted workloads or specific instructions an deferring conflicted workloads instead of locking memory locations.

Abstract: The present invention extends to methods, systems, and computer program products for providing asymmetric Graphical Processing Unit (“GPU”) processors in a para-virtualized environment. A virtual GPU (“vGPU”) within a child partition of the para-virtualized environment includes a kernel-mode driver (“KMD”) and a user-mode driver (“UMD”). The KMD includes a plurality of virtual nodes. Each virtual node performs a different type of operation in parallel with other types of operations. The KMD is declared as a multi-engine GPU. The UMD schedules operations for parallel execution on the virtual nodes. A render component within a root partition of the para-virtualized environment executes GPU commands received from the vGPU at the physical GPU. A plurality of memory access channels established between the KMD and the render component communicate GPU commands between a corresponding virtual node at the KMD and the render component.

Abstract: Described is a device comprising a spatial light modulator comprising a plurality of comparators for computing a respective drive for each pixel of a plurality of pixels.

Abstract: A latency tolerant system for executing video processing operations. The system includes a host interface for implementing communication between the video processor and a host CPU, a scalar execution unit coupled to the host interface and configured to execute scalar video processing operations, and a vector execution unit coupled to the host interface and configured to execute vector video processing operations. A command FIFO is included for enabling the vector execution unit to operate on a demand driven basis by accessing the memory command FIFO. A memory interface is included for implementing communication between the video processor and a frame buffer memory. A DMA engine is built into the memory interface for implementing DMA transfers between a plurality of different memory locations and for loading the command FIFO with data and instructions for the vector execution unit.

Abstract: Exemplary embodiments of methods, apparatuses, and systems for seamlessly migrating a user visible display stream sent to a display device from one rendered display stream to another rendered display stream are described. For one embodiment, mirror video display streams are received from both a first graphics processing unit (GPU) and a second GPU, and the video display stream sent to a display device is switched from the video display stream from the first GPU to the video display stream from the second GPU, wherein the switching occurs during a blanking interval for the first GPU that overlaps with a blanking interval for the second GPU.

Abstract: Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an interlink module is coupled to receive processed data corresponding to the frames from each of the multiple processors. The interlink module controls a phase alignment between the processors. The interlink module selects pixels of the frames from the processed data of one of the processors based on a predetermined pixel characteristic and outputs the frames that include the selected pixels.

Abstract: According to one embodiment, an information processing apparatus includes a stage determination module, a score calculator and a pass window determination module. The stage determination module determines a process-target stage or process-target stages from plural stages, each of the plural stages rejecting a window of windows set on an image, wherein the rejected window does not include a target object. The score calculator calculates in parallel, scores of the windows in the process-target stages when the process-target stages have been determined. The pass determination module determines in parallel, pass or rejection of a window of the windows, based on two or more scores of the window in the process-target stages.

Abstract: A system, method and a computer program product are provided for distributing prim groups for parallel processing in a single clock cycle. A work distributor divides a draw call for primitive processing into a plurality of prim groups according to a prim group size. The work distributor then distributes the plurality of prim groups to a plurality of shader engines for parallel processing of the plurality of prim groups during a clock cycle. The size of a prim group and a number of prim groups are scaled to the plurality of shader engines.

Abstract: A method for providing two or more processors access to a single command buffer is provided. The method includes receiving instructions in the command buffer from a central processor, at least one of the instructions being designated for a particular one of the two or more processors. The method also includes sending the at least one instruction to only the particular processor.

Abstract: System and method for a parallel image processing mechanism for applying mask data patterns to substrate in a lithography manufacturing process are disclosed. In one embodiment, the parallel image processing system includes a graphics engine configured to partition an object into a plurality of trapezoids and form an edge list for representing each of the plurality of trapezoids, and a distributor configured to receive the edge list from the graphics engine and distribute the edge list to a plurality of scan line image processing units. The system further includes a sentinel configured to synchronize operations of the plurality of scan line image processing units, and a plurality of buffers configured to store image data from corresponding scan line image processing units and outputs the stored image data using the sentinel.

Abstract: Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. An interlink module is coupled to receive processed data corresponding to the frames from each of the processors. The interlink module divides a first frame into multiple frame portions by dividing pixels of the first frame using at least one balance point. The interlink module dynamically determines a position for the balance point that minimizes differences between the workload of the processors during processing of commands and/or data of one or more subsequent frames.

Abstract: A rendering processing apparatus and method using multiprocessing are disclosed. The rendering processing method includes dividing an application execution window into frames and generating a rendering processing command for rendering processing of an image on a frame basis by a pre-rendering manager, generating a rendering image for a frame according to the generated rendering processing command by a rendering manager, and storing the generated rendering image in a memory. A task for generating a rendering processing command is divided into at least one task, a task for generating a rendering image is divided into at least one task, and the divided tasks can be processed simultaneously in a plurality of threads.

Abstract: A rendering processing apparatus and method using multiprocessing are disclosed. The rendering processing method includes dividing an application execution window into frames and generating a rendering processing command for rendering processing of an image on a frame basis by a pre-rendering manager, generating a rendering image on a frame basis according to the rendering processing command by a rendering manager, and storing the generated rendering image in a memory. The generation of a rendering processing command and the generation of a rendering image are performed in a plurality of threads.

Abstract: A device receives, via a technical computing environment, a program that includes a parallel construct and a command to be executed by graphical processing units, and analyzes the program. The device also creates, based on the parallel construct and the analysis, one or more instances of the command to be executed in parallel by the graphical processing units, and transforms, via the technical computing environment, the one or more command instances into one or more command instances that are executable by the graphical processing units. The device further allocates the one or more transformed command instances to the graphical processing units for parallel execution, and receives, from the graphical processing units, one or more results associated with parallel execution of the one or more transformed command instances by the graphical processing units.

Abstract: A method of dynamic load-balancing in a PC-based computing system employing a multiple GPU-based graphics pipeline architecture supporting multiple modes of GPU parallelization. During the execution of the graphics application, the stream of geometrical data and said graphics commands is analyzed, and the mode of parallelization of the GPUs during each frame, is determined using results of the analysis of the stream of geometrical data and graphics commands, and one or more policies for determining the mode of parallelization. The stream of geometrical data and graphic commands is distributed to the GPUs according to the determined mode of parallelization. During the generation of each frame, one or more of GPUs are used to process the stream of geometrical data and graphic commands, or a portion thereof, while operating in the parallelization mode, so as to generate pixel data corresponding to at least a portion of an image of 3D object.

Abstract: A technique for early sample evaluation during coarse rasterization of primitives reduces the number of pixel tiles that are processed during fine rasterization of the primitive. A primitive bounding box determines when a primitive is small and may not actually cover any samples within at least one fine raster tile. Early sample evaluation is performed for the small primitive during coarse rasterization and the small primitive is discarded when no samples are actually covered by the small primitive. When the small primitive lies on a boundary between at least two fine raster tiles, early sample evaluation is performed during coarse rasterization to correctly identify which, if any, of the at least two fine raster tiles includes samples that are actually covered by the small primitive.

Abstract: A print data processing apparatus allocates memory from an unused area of memory to one processor out of two processors so that a size of the memory allocated to the processor is equal to a fallback threshold value, and then allocates an unused area of the remaining memory to the other processor.

Abstract: A method is provided that utilizes a parallel processing system to determine whether different geometries intersect each tile in a map hierarchy. The method receives a description of a geometry and an identification of a tile in a tile tree. The method utilizes an available processing unit to determine whether the geometry intersects the tile. When the geometry intersects the tile and the tile has child tiles, the method stores several task descriptions that can be assigned to any processing units in the parallel processing system. Each task description includes the description of the portion of the geometry that overlaps the tile and an identification of one of the child tiles of the tile. The method then assigns each of the tasks to an available processing unit to continue down the tree hierarchy to determine whether each child tile intersects a portion of the geometry.

Abstract: An information processing apparatus includes a first graphics chip having a first drawing processing capacity and being capable of producing a first image signal; a second graphics chip having a second drawing processing capacity higher than the first drawing processing capacity and being capable of producing a second image signal; an output changeover section capable of selectively outputting one of the first or second image signals; an inputting section configured to input a user operation to select one of the first graphics chip or the second graphics chip; and a control section configured to control the output of the output changeover section in response to the inputted user operation.

Abstract: An arithmetic logic stage in a graphics processor unit includes arithmetic logic units (ALUs) and global registers. The registers contain global values for a group of pixels. Global values may be read from any of the registers, regardless of which of the pixels is being operated on by the ALUs. However, when writing results of the ALU operations, only some of the global registers are candidates to be written to, depending on the pixel number. Accordingly, overwriting of data is prevented.

Abstract: A method of managing multiple contexts for a single mode display includes receiving a plurality of tasks from one or more applications and determining respective contexts for each task, each context having a range of memory addresses. The method also includes selecting one context for output to the single mode display and loading the selected context into a graphics processor for the display.

Abstract: The time needed for back-end work can be estimated without actually doing the back-end work. Front-end counters record information for a cost model and heuristics may be used for when to split a tile and ordering work dispatch for cores. A special rasterizer discards triangles and fragments outside a sub-tile.

Abstract: Methods and apparatuses for scheduling and storing media creation are described. Methods and apparatuses for rendering a plurality of vector graphic objects on a display are also described.

Abstract: Input pixel values associated with input pixel positions having a first spacing along a direction are received and processed to determine output pixel values associated with output pixel positions having a second spacing along the direction, from respective combinations of input pixel values weighted by coefficients given by an interpolation function. In a downscaling operation, the second spacing is larger than the first spacing, and the weighting coefficients represent values of the interpolation function expanded spatially by an expansion factor equal to the ratio of the second spacing to the first spacing.

Abstract: In general, this disclosure relates to techniques for using graphics instructions and state information received from a graphics device to visually create a graphics image. Performance analysis may also be conducted to identify potential bottlenecks during instruction execution on the graphics device. One example device includes a display device and one or more processors. The one or more processors are configured to receive a plurality of graphics instructions from an external graphics device, wherein the graphics instructions are executed by the external graphics device to display a graphics image, and to receive state information from the external graphics device, wherein the state information is associated with execution of the graphics instructions on the external graphics device. The one or more processors are further configured to display, on the display device, a representation of the graphics image according to the graphics instructions and the state information.

Abstract: A portable data terminal including a multi-core processor having at least a first core and a second core, at least one illumination assembly and at least one imaging assembly and data storage means configured to store a plurality of program instructions, the program instructions including at least one one-dimensional decoder and at least one two-dimensional decoder.

Abstract: A multithreaded rendering software pipeline architecture dynamically reallocates regions of an image space to raster threads based upon performance data collected by the raster threads. The reallocation of the regions typically includes resizing the regions assigned to particular raster threads and/or reassigning regions to different raster threads to better balance the relative workloads of the raster threads.

Abstract: Described is a technology for constructing kd-trees on GPUs, in a manner that is sufficiently fast to achieve real-time performance by exploiting GPU-based parallelism during the kd-tree construction. Tree nodes are built in breadth-first search order, e.g., to use a thread for each node at each level. For large nodes at upper tree levels, computations are parallelized over geometric primitives (instead of nodes). To this end, large nodes are split into child nodes by cutting off empty space based until an empty space ratio is achieved, and thereafter performing spatial splitting. Small nodes are split based on split candidate costs, e.g., computed by a surface area heuristic or a voxel volume heuristic (VVH).

Abstract: Systems, methods, and computer-readable storage media for resizing images using seam carving techniques may include generation of a partial solution matrix by at least partially isolating dependencies between sub-problems of a dynamic programming problem corresponding to its solution within different regions of an input image. The number and/or shape of the isolated (or partially isolated) sub-problems may be dependent on the access pattern used by a dynamic programming operation to identify seams in the input image. Multiple sub-problems may be processed independently and in parallel on respective processor core(s) or threads thereof to generate the partial solution matrix. The partial solution matrix may then be processed to identify one or more low-cost seams of the input image. The methods may be implemented as stand-alone applications or as program instructions implementing components of a graphics application, executable by a CPU and/or GPU configured for parallel processing.

Abstract: Backlit LCD displays are becoming commonplace within many vehicle applications. The unique advantage of this invention is that it optimizes system power savings for display of low dynamic range (LDR) images by dynamically controlling spatially adjustable backlighting. This is accomplishes through use of a control technique that takes into account the sequential nature of the video display process.

Abstract: Disclosed are methods and systems for granting an application-specific integrated circuit (ASIC) in a multi-ASIC environment controlled access to a shared resource. A system includes a first ASIC, a second ASIC, and a shared memory that stores a shared resource and a data set partitioned into fields. The first ASIC writes data to a first subset of the fields and reads data from the fields. The first ASIC includes first logic that computes a first value based on the data read from the fields. The second ASIC writes data to a second subset of the fields and reads data from the fields. The second ASIC includes second logic that computes a second value based on the data read from the fields. Based on the first and second values respectively computed by the first and second logic, only one of the first and second ASICs gains access to the shared resource.

Abstract: A software layer is disposed between an application and a driver. In use, the software layer is adapted to receive an object from the application intended to be rendered by a first graphics processor. Such software layer, in turn, routes the object to a second graphics processor, based on a policy.

Abstract: One embodiment of the present invention sets forth a method for enabling an intermediate code-based application program to access a target graphics processing unit (GPU) in a parallel processing environment. The method includes the steps of compiling a source code of the intermediate code-based application program to an intermediate code, translating the intermediate code to a PTX instruction code, and translating the PTX instruction code to a machine code executable by the target graphics processing unit before delivering the machine code to the target GPU.

Abstract: A system and method force a display device to receive the output produced by a graphics processing unit that is configured as the video graphics array (VGA) boot device for display of critical system screens. A hybrid computer system that includes multiple graphics processors configures a display multiplexor to select image data from one of the multiple graphics processing units for output to the display device. When a critical system event occurs and the graphics processing unit that is selected is not configured as the VGA boot device, system basic input/output system (BIOS) interfaces are used to configure the multiplexor to select the one graphics processing unit that is configured as the VGA boot device to output the critical system screen to the display device.

Abstract: Embodiments of the present application automatically utilize parallel image captures in an image processing pipeline. In one embodiment, image processing circuitry concurrently receives first image data to be processed and second image data to be processed, wherein the second image data is processed to aid in enhancement of the first image data.

Abstract: An image processing device, in a case in which an image processing module, uses in image processing a processor that is different than a processor used in image processing by an image processing module of a preceding stage, is connected at a subsequent stage, carries out transfer processing that transfers image data, that has been written into a buffer by the image processing module of the preceding stage, to a buffer for transfer that is reserved in a memory space corresponding to the processor that the image processing module of the subsequent stage uses in image processing, and carries out processing that causes the image processing module of the subsequent stage to read-out the image data transferred to the buffer for transfer.

Abstract: A reusable expression graph system and method that generates reusable expression graphs that can be used with potentially different input parameters in order to achieve computational efficiency and ease of programming. Reusable expression graph mitigate the need to rebuild an expression for each new value. This is achieved in part by creating a node called a “parameter node.” The parameter node acts as a generic placeholder for a leaf node in the expression graph. In addition, the parameter node acts as a proxy for a bindable term of the leaf node, and the bindable term can be either a value or one or more additional expressions. The parameter node then is bound to the bindable term and the expression is evaluated with that bindable term instead of the placeholder. The parameter node created by embodiments of the reusable expression graph system and method works across many different programming languages.

Abstract: A method for utilizing a CUDA based GPU to accelerate a complex, sequential task such as video decoding, comprises decoding on a CPU headers and macroblocks of encoded video, performing inverse quantization (on CPU or GPU), transferring the picture data to GPU, where it is stored in a global buffer, and then on the GPU performing inverse waveform transforming of the inverse quantized data, performing motion compensation, buffering the reconstructed picture data in a GPU global buffer, determining if the decoded picture data are used as reference for decoding a further picture, and if so, copying the decoded picture data from the GPU global buffer to a GPU texture buffer. Advantages are that the data communication between CPU and GPU is minimized, the workload of CPU and GPU is balanced and the modules off-loaded to GPU can be efficiently realized since they are data-parallel and compute-intensive.

Abstract: A symbolic encoding of predicated execution for static verification, based on a plurality of data parallel program instructions, is obtained. A result of static verification of one or more attributes associated with the plurality of data parallel program instructions is obtained, based on the symbolic encoding.