Abstract: Systems and methods for generating distributed dataflow graphs and processing data elements in parallel utilizing the distributed dataflow graphs are provided. A sequential dataflow graph is formed from incoming data elements, and a variety of heuristics is applied to the sequential dataflow graph to determine which of the data transformation steps within the graph are capable of being processed multiple times in parallel. Once determined, the sequential dataflow graph is divided into subgraphs, which are then replicated, e.g., based on available resources and.or external constraints. The resulting subgraphs are connected, based on the semantics of each vertex, and a distributed dataflow graph is generated, which can efficiently process data elements, for instance, for data warehousing and the like.

Abstract: A non-transitory computer-readable storage medium having computer-executable instructions for causing a computer system to perform a method for constructing bounding volume hierarchies from binary trees is disclosed. The method includes providing a binary tree including a plurality of leaf nodes and a plurality of internal nodes. Each of the plurality of internal nodes is uniquely associated with two child nodes, wherein each child node comprises either an internal node or leaf node. The method also includes determining a plurality of bounding volumes for nodes in the binary tree by traversing the binary tree from the plurality of leaf nodes upwards toward a root node, wherein each parent node is processed once by a later arriving corresponding child node.

Abstract: A non-transitory computer-readable storage medium having computer-executable instructions for causing a computer system to perform a method for constructing k-d trees, octrees, and quadtrees from radix trees is disclosed. The method includes assigning a Morton code for each of a plurality of primitives corresponding to leaf nodes of a binary radix tree, and sorting the plurality of Morton codes. The method includes building a radix tree requiring at most a linear amount of temporary storage with respect to the leaf nodes, wherein an internal node is built in parallel with one or more of its ancestor nodes. The method includes, partitioning the plurality of Morton codes for each node of the radix tree into categories based on a corresponding highest differing bit to build a k-d tree. A number of octree or quadtree nodes is determined for each node of the k-d tree. A total number of nodes in the octree or quadtree is determined, allocated and output.

Abstract: In processing a game scene for display, in one embodiment input controller position information from a host memory is provided directly to a graphics processor rather than first being processed by a 3D application in a host processor. This results in more direct and timely processing of position information and reduces the number of 3D processing pipeline steps the controller position information must pass through thus reducing the user's perceived latency between moving the input controller and seeing the displayed results. In another embodiment, the input controller position information is provided directly from an input controller to a graphics card or subsystem rather than first going through a host processor or memory. This results in even more direct and timely processing of position information by further reducing the number of 3D processing pipeline steps the controller position information must pass through thus further reducing the user's perceived latency.

Abstract: A system includes a memory, a specialized processing unit and a processor. The processor receives data from a user and creates a first set of objects in a first structure based on the data. The system further creates, contemporaneously with the creation of the first set of objects and based on the first set of objects in the first structure, a second set of objects in a second structure, where the second set of objects is optimized for use by the specialized processing unit, and stores the first and second sets of objects in the memory. The specialized processing unit executes an algorithm based on the second set of objects.

Abstract: A circuit arrangement and method make state changes to shared state data in a highly multithreaded environment by propagating or streaming the changes to multiple parallel hardware threads of execution in the multithreaded environment using an on-chip communications network and without attempting to access any copy of the shared state data in a shared memory to which the parallel threads of execution are also coupled.

Abstract: A central processing unit (CPU) according to embodiments of the inventive concept may include an upper core allocated with a main thread and a plurality of lower cores, each of the plurality of the lower cores being allocated with at least one worker thread. The worker thread may perform simulation operations on operation units of a graphic processing unit (GPU) to generate simulation data, and the main thread may generate synchronization data based on the generated simulation data.

Abstract: A first software stack and a second software stack are run in a virtual environment. The virtual environment may be created by a hardware virtualizer. The hardware virtualizer may send the first software stack to the discrete graphics processing unit and the second software stack to the integrated graphics processing unit.

Abstract: A display system is disclosed that is capable of switching between graphics processing units (GPUs). Some embodiments may include a display system, including a display, a timing controller (T-CON) coupled to the display, the T-CON including a plurality of receivers, and a plurality of GPUs, where each GPU is coupled to at least one of the plurality of receivers, and where the T-CON selectively couples only one of the plurality of GPUs to the display at a time.

Abstract: A method of server site rendering 3D images on a server computer coupled to a client computer wherein the client computer instructs a server computer to load data for 3D rendering and sends a stream of rendering parameter sets to the server computer, each set of rendering parameters corresponding with an image to be rendered; next the render computer renders a stream of images corresponding to the stream of parameter sets and the stream of images is compressed with a video compression scheme and sent from the server computer to the client computer where the client computer decompresses the received compressed video stream and displays the result in a viewing port. The rendering and communication chain is subdivided in successive pipeline stages that work in parallel on successive rendered image information.

Abstract: A method includes performing a task in response to a request of a secondary user interface of a secondary device. The method also includes calculating a utilization of a graphics processing unit of a machine based on the task performed by the graphics processing unit. The method further includes determining the utilization, through a processor, based on a comparison of a consumption of a computing resource of the graphics processing unit and a sum of the computing resource available. The method furthermore includes performing another task in response to the request of another secondary user interface of another secondary device. The method furthermore includes calculating another utilization of another graphics processing unit based on the another task performed by the another graphics processing unit. The method furthermore includes determining the another utilization based on the comparison of a consumption of the computing resource of the another graphics processing unit.

Abstract: A method and an apparatus are provided for combining multiple independent tile-based graphic cores. An incoming geometry stream is split into a plurality of streams and sent to respective tile based graphics processing cores. Each one generates a separate tiled geometry list as described. These may be combined into a master tiling unit or, alternatively, markers may be inserted into the tiled geometry lists which are used in the rasterization phase to switch between tiling lists from different geometry processing cores.

Abstract: A multiple graphics processing unit (GPU) based parallel graphics system comprising multiple graphics processing pipelines with multiple GPUs supporting a parallel graphics rendering process having an object division mode of operation. Each GPU comprises video memory, a geometry processing subsystem and a pixel processing subsystem. According to the principles of the present invention, pixel (color and z depth) data buffered in the video memory of each GPU is communicated to the video memory of a primary GPU, and the video memory and the pixel processing subsystem in the primary GPU are used to carry out the image recomposition process, without the need for dedicated or specialized apparatus.

Abstract: One embodiment of the present invention sets forth a technique for performing low latency computation on a parallel processing subsystem. A low latency functional node is exposed to an operating system. The low latency functional node and a generic functional node are configured to target the same underlying processor resource within the parallel processing subsystem. The operating system stores low latency tasks generated by a user application within a low latency command buffer associated with the low latency functional node. The parallel processing subsystem advantageously executes tasks from the low latency command buffer prior to completing execution of tasks in the generic command buffer, thereby reducing completion latency for the low latency tasks.

Abstract: An image processing system in the medical field is provided. The system for processing image data includes at lest two graphics processors, at least one renderer module for rendering image data and at least one reconstruction module for volume reconstruction. In a first operating mode of the system in which at least one reconstruction module is inactive, the instructions of at least one renderer module is able to be executed by at least two of the graphics processors. In a second operating mode of the system in which at least one reconstruction module is active, the instructions of at least one renderer module and the instructions of at least one reconstruction module is able to be executed separately on different graphics processors of the said graphics processors. During operation in one of the two operating modes, a switch can be made to the other operating mode in each case.

Abstract: Disclosed are machine processors and methods performed thereby. The processor has access to processing units for performing data processing and to libraries. Functions in the libraries are implementable to perform parallel processing and graphics processing. The processor may be configured to acquire (e.g., to download from a web server) a download script, possibly with extensions specifying bindings to library functions. Running the script may cause the processor to create, for each processing unit, contexts in which functions may be run, and to run, on the processing units and within a respective context, a portion of the download script. Running the script may also cause the processor to create, for a processing unit, a memory object, transfer data into that memory object, and transfer data back to the processor in such a way that a memory address of the data in the memory object is not returned to the processor.

Abstract: An image processing apparatus includes: an image division section which divides input image data configuring one screen into N (N is an integer of 2 or more) image blocks; and N image processing sections which carry out image processings in parallel on every N image blocks, an ith (i is an integer of 1 to N) image processing section including: a first image block memory; K (K is an integer of 2 or more) image quality adjustment sections; (K?1) buffer memories; a second image block memory; and a pixel data acquisition section, wherein each image quality adjustment section selects processing subject pixels, in order from pixels positioned outside toward pixels positioned inside the ith image block, and carries out the image quality adjustment, and at least one of the second to Kth image quality adjustment sections is a filtering section which carries out a filtering process.

Abstract: There is provided an information processing apparatus, including a first processing unit capable of processing an image, a second processing unit capable of processing the image in parallel for each unit dividing the image, and a controller section configured to perform a control to select one of the first processing unit, the second processing unit, and both of them as a subject or subjects processing the image, to divide, in a case where both the first processing unit and the second processing unit are selected, the image into a first region and a second region, and to assign processing of an image of the first region and processing of an image of the second region, which are obtained by the division, to the first processing unit and the second processing unit, respectively, to cause the first processing unit and the second processing unit to perform the processing.

Abstract: A portable data terminal including a multi-core processor having at least a first core and a second core, at least one illumination assembly and at least one imaging assembly and data storage means configured to store a plurality of program instructions, the program instructions including at least one one-dimensional decoder and at least one two-dimensional decoder.

Abstract: This invention relates to a method of processing a plurality of graphical programs on a centralized computer system whereby the images produced by the programs are compressed and transmitted to remote processing devices where they are decompressed. Compression assistance data (CAD) is produced by inspecting instructions outputted by the programs and the CAD is then used in the compression step.

Abstract: A signal processing apparatus able to raise a processing capability in processing accompanying access to a storing means is provided. Stream control units (SCU) 203—0 to 203—3 access data at an external memory system or local memories 204—0 to 204—3 according to a thread under control from a host processor. Processor units (PU) arrays 202—0 to 202—3 perform image processing by a different thread from the thread of the SCUs 203—0 to 203—3.

Abstract: A method implemented by one or more computers may include receiving data for graphical rendering and distributing a first portion of the data to a first computation process. The method may further include distributing a second portion of the data to a second computation process, where the second computation process is different than the first computation process, creating a first object subtree via the first computation process based on the first portion of the data, and creating a second object subtree via the second computation process based on the second portion of the data. The method may further also include assembling an object tree via a third computation process based on the first object subtree and the second object subtree and rendering a graphical scene based on the assembled object tree.

Abstract: Systems, methods, and media for providing libraries within an OpenCL framework. Library source code is compiled into an intermediate representation and distributed to an end-user computing system. The computing system typically includes a CPU and one or more GPUs. The CPU compiles the intermediate representation of the library into an executable binary targeted to run on the GPUs. The CPU executes a host application, which invokes a kernel from the binary. The CPU retrieves the kernel from the binary and conveys the kernel to a GPU for execution.

Abstract: Methods for resolving a number of in-memory issues associated with parallel query execution of a database operation on a database utilizing a graphics processing unit (GPU) are presented including: tying a table choice to a number of accesses per second made to a table; and synchronizing threads in a same shared GPU multiprocessor to avoid compromising concurrency, and where the parallel query execution of the database operation is performed solely by the GPU. In some embodiments, methods further include storing data from the GPU to a disk to solve volatility; and enabling a user, at any time, to query the amount of memory being used by the table created by the user to monitor memory consumption.

Abstract: In a single-instruction-multiple-data (SIMD) processor having multiple lanes, and local memory dedicated to each lane, a method of processing an image is disclosed. The method comprises mapping consecutive rasters of the image to consecutive lanes such that groups of consecutive rasters form image strips, and vertical stacks of strips comprise strip columns. Local memory allocates memory to the image strips. A sequence of functions is processed for execution on the SIMD processor in a pipeline implementation, such that the pipeline loops over portions of the image in multiple iterations, and intermediate data processed during the functions is stored in the local memory. Data associated with the image is traversed by first processing image strips from top to bottom in a left-most strip column, then progressing to each adjacent unprocessed strip column.

Abstract: Systems and techniques for processing sequences of video images involve receiving, on a computer, data corresponding to a sequence of video images detected by an image sensor. The received data is processed using a graphics processor to adjust one or more visual characteristics of the video images corresponding to the received data. The received data can include video data defining pixel values and ancillary data relating to settings on the image sensor. The video data can be processed in accordance with ancillary data to adjust the visual characteristics, which can include filtering the images, blending images, and/or other processing operations.

Abstract: An image processing apparatus includes: a plurality of image processing units each of which is disposed so as to correspond to each of partial images and processes data of each of pixels composing the partial image with reference to data of peripheral pixels of the pixel, wherein the plurality of image processing units includes at least a first image processing unit which use data of pixels composing other partial images adjacent to a first partial image as the data of the peripheral pixels for the image processing on a first partial image, and a second image processing unit which performs the image processing on a second partial image and brokers data of pixels treated as the peripheral pixels by the first image processing unit from an image processing unit which processes the other partial image to the first image processing unit.

Abstract: A DGS (discrete graphics system) unit is disclosed. The DGS unit includes a system chassis configured to house a GPU, the GPU for executing 3-D graphics instructions, and a GPU mounting unit coupled to the system chassis and configured to receive the GPU. A serial bus connector is coupled to the chassis and is coupled to the GPU mounting unit, wherein the serial bus connector is configured removably connect the GPU to a computer system to enable the GPU to access the computer system via the serial bus connector and execute the 3-D graphics instructions for the computer system. A power supply coupled to the system chassis for supplying power to the GPU independent of the computer system.

Abstract: Disclosed is a system for producing images including techniques for reducing the memory and processing power required for such operations. The system provides techniques for programmatically representing a graphics problem. The system further provides techniques for reducing and optimizing graphics problems for rendering with consideration of the system resources, such as the availability of a compatible GPU.

Abstract: A multi-pass method of generating an image frame of a 3D scene, using a parallel graphics processing system having a plurality of graphics processing pipelines (GPPLs), including a primary GPPL. In the system, each GPPL includes a color frame buffer and Z depth buffer, and the GPPLs support an object-division based parallel graphics rendering process, in which the 3D scene is decomposed into objects that are assigned to particular GPPLs for processing. The multi-pass method involves, during a first pass, providing a Global Data Map (GDM) to the Z depth buffer of each GPPL. This step involves the transmission of graphics commands and data for all objects in the frame, to all GPPLs to be rendered. Then, during subsequent passes, a complementary-type partial image is generated within the color buffer of each GPPL using the GDM and a Z test filter supported by the Z depth buffer, and transmitting graphics commands and data of objects in the image frame, to only assigned GPPLs.

Abstract: A method and an apparatus for notifying a display driver to update a display with a graphics frame including multiple graphics data rendered separately by multiple graphics processing units (GPUs) substantially concurrently are described. Graphics commands may be received to dispatch to each GPU for rendering corresponding graphics data. The display driver may be notified when each graphics data has been completely rendered respectively by the corresponding GPU.

Abstract: A method is to implement a Scale Invariant Feature Transform algorithm in a shared memory multiprocessing system. The method comprises building differences of Gaussian (DoG) images for an input image, detecting keypoints in the DoG images; assigning orientations to the keypoints and computing keypoints descriptors and performing matrix operations. In the method, building differences of Gaussian (DoG) images for an input image and detecting keypoints in the DoG images are executed for all scales of the input image in parallel. And, orientation assignment and keypoints descriptions computation are executed for all octaves of the input image in parallel.

Abstract: Exemplary apparatus, method, and system embodiments provide for processing an action script for a graphical image for visual display. An exemplary apparatus comprises: a first memory; first circuitry configured to convert a plurality of descriptive elements of the action script into a plurality of operational codes; and second circuitry configured to execute the plurality of operational codes using corresponding data stored in the first memory to generate pixel data for the graphical image. Exemplary embodiments may further include third circuitry configured to parse the action script into the plurality of descriptive elements and the corresponding data, and fourth circuitry configured to extract data from the action script and to store the extracted data in the first memory as a plurality of control words having the corresponding data in predetermined fields.

Abstract: A device compiler and linker is configured to optimize program code of a co-processor enabled application by resolving generic memory access operations within that program code to target specific memory spaces. In situations where a generic memory access operation cannot be resolved and may target constant memory, constant variables associated with those generic memory access operations are transferred to reside in global memory.

Abstract: One embodiment of the present invention sets forth a method for enabling an intermediate code-based application program to access a target graphics processing unit (GPU) in a parallel processing environment. The method includes the steps of compiling a source code of the intermediate code-based application program to an intermediate code, translating the intermediate code to a PTX instruction code, and translating the PTX instruction code to a machine code executable by the target graphics processing unit before delivering the machine code to the target GPU.

Abstract: Methods and apparatuses are disclosed for improving switching between graphics processing units (GPUs). Some embodiments may include a display system, including a plurality of GPUs, a multiplexer coupled to the plurality of GPUs, a timing controller coupled to the multiplexer, where the timing controller may provide an indication signal to the multiplexer indicative of a period when a first GPU is experiencing a first blanking interval.

Abstract: A pipelined video pre-processor includes a plurality of configurable image-processing modules. The modules may be configured using direct processor control, DMA access, or both. A block-control list, accessible via DMA, facilitates configuration of the modules in a manner similar to direct processor control. Parameters in the modules may be updated on a frame-by-frame basis.

Abstract: Exemplary apparatus, method, and system embodiments provide for accelerated hardware processing of an action script for a graphical image for visual display. An exemplary apparatus comprises: a first memory; and a plurality of processors to separate the action script from other data, to convert a plurality of descriptive elements of the action script into a plurality of hardware-level operational or control codes, and to perform one or more operations corresponding to an operational code of the plurality of operational codes using corresponding data to generate pixel data for the graphical image. In an exemplary embodiment, at least one processor further is to parse the action script into the plurality of descriptive elements and the corresponding data, and to extract data from the action script and to store the extracted data in the first memory as a plurality of control words having the corresponding data in predetermined fields.

Abstract: Exemplary apparatus, method, and system embodiments provide for accelerated hardware processing of an action script for a graphical image for visual display. An exemplary method comprises: converting a plurality of descriptive elements into a plurality of operational codes which at least partially control at least one processor circuit; and using at least one processor circuit, performing one or more operations corresponding to an operational code to generate pixel data for the graphical image. Another exemplary method for processing a data file which has not been fully compiled to a machine code and comprising interpretable descriptions of the graphical image in a non-pixel-bitmap form, comprises: separating the data file from other data; parsing and converting the data file to a plurality of hardware-level operational codes and corresponding data; and performing a plurality of operations in response to at least some hardware-level operational codes to generate pixel data for the graphical image.

Abstract: A multiprocessor system includes a plurality of special purpose processors that perform different portions of a related processing task. A set of commands that cause each of the processors to perform the portions of the related task are distributed, and the set of commands includes a predicated execution command that precedes other commands within the set of commands. It is determined whether commands subsequent to the predicated execution command are intended to be executed by a first processor or a second processor based on information in the predicated execution command and the set of commands includes all commands to be executed by each processor.

Abstract: One embodiment of the present invention sets forth a method for dynamically load balancing rendering operations across an IGPU and a DGPU. For each frame, the graphics driver configures the IGPU to pre-compute Z-values for a portion of the display surface and to write feedback data to the system memory indicating the time that the IGPU used to process the frame. The graphics driver then configures the DGPU to use the pre-computed Z-values while rendering to the complete display surface and to write feedback data to the system memory indicating the time that the DGPU used to process the frame. The graphics driver uses the feedback data from the IGPU and DGPU in conjunction with the percentage of the display surface that the IGPU Z-rendered for the frame to scale the portion of the display surface that the IGPU Z-renders for one or more subsequent frames. In this fashion, overall processing within the graphics pipeline is optimized across the IGPU and DGPU.

Abstract: A multithreaded rendering software pipeline architecture utilizes a rolling texture context data structure to store multiple texture contexts that are associated with different textures that are being processed in the software pipeline. Each texture context stores state data for a particular texture, and facilitates the access to texture data by multiple, parallel stages in a software pipeline. In addition, texture contexts are capable of being “rolled”, or copied to enable different stages of a rendering pipeline that require different state data for a particular texture to separately access the texture data independently from one another, and without the necessity for stalling the pipeline to ensure synchronization of shared texture data among the stages of the pipeline.

Abstract: A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.

Abstract: Aspects include a multistage collector to receive outputs from plural processing elements. Processing elements may comprise (each or collectively) a plurality of clusters, with one or more ALUs that may perform SIMD operations on a data vector and produce outputs according to the instruction stream being used to configure the ALU(s). The multistage collector includes substituent components each with at least one input queue, a memory, a packing unit, and an output queue; these components can be sized to process groups of input elements of a given size, and can have multiple input queues and a single output queue. Some components couple to receive outputs from the ALUs and others receive outputs from other components. Ultimately, the multistage collector can output groupings of input elements. Each grouping of elements (e.g., at input queues, or stored in the memories of component) can be formed based on matching of index elements.

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: A method is provided for optimizing computer processes executing on a graphics processing unit (GPU) and a central processing unit (CPU). Process data is subdivided into sequentially processed data and parallel processed data. The parallel processed data is subdivided into a plurality of data blocks assigned to a plurality of processing cores of the GPU. The data blocks on the GPU are processed with other data blocks in parallel on the plurality of processing cores. Sequentially processed data is processed on the CPU. Result data processed on the CPU is returned.

Abstract: Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. An interlink module is coupled to receive processed data corresponding to the frames from each of the processors. The interlink module divides a first frame into multiple frame portions by dividing pixels of the first frame using at least one balance point. The interlink module dynamically determines a position for the balance point that minimizes differences between the workload of the processors during processing of commands and/or data of one or more subsequent frames.

Abstract: Image data is captured from a specified area of a rendered screen display from the video memory for a number of frames. The image data can be captured in another area of video memory, enabling a video memory to video memory copy to be performed, thus bypassing system memory. This captured image data can be synchronized with event trace data, or other metadata from the operating system, associated with the application. Analysis tools can read and analyze the captured image data in real time to detect and report render artifacts. A graphics processing unit can implement the analysis and operate on the image data directly in the video memory. Such analysis can include a statistical analysis of the images in a sequence of screen captures to identify outliers in the sequence. These outliers have render artifacts.

Abstract: Techniques are disclosed for parallel computing of a line of sight (LoS) map (e.g., view-shed) in a parallel computing system. For example, a method for computing an LoS map comprises the following steps. Data representing at least one image is obtained. An observation point in the at least one image is identified. A portion of the data that is associated with a given area in the image is partitioned into a plurality of sub-areas. The plurality of sub-areas are assigned to a plurality of processor elements of a parallel computing system, respectively, such that the data associated with each one of the plurality of sub-areas is processed independent from the data associated with each other of the plurality of sub-areas, wherein results of the processing by the processor elements represents the LoS map. The parallel computing system may be a multicore processor.

Abstract: An image display device includes: a storing section configured to store associating information that associates information indicating one or more providing sources of image data with each of one or more display areas set within a display screen; an obtaining section configured to obtain image data from a providing source corresponding to each of one or more display areas on the basis of the associating information stored in the storing section; a forming section configured to form display image data of a display image to be displayed on the display screen on the basis of the image data being obtained by said obtaining section for each of one or more display areas; and a display processing section configured to display the display image corresponding to the display image data formed by the forming section on the display screen.