Abstract: Methods and devices are described for a parallel multi-processor encoder system for encoding video data, wherein the video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system may divide the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks may be transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.

Abstract: A graphics system has a rendering space divided into a plurality of rectangular areas, each being sub-divided into a plurality of smaller rectangular areas of a plurality of pixels. Data is received representing a tiled set of polygons to be rendered in a selected one of the rectangular areas. For each polygon, a determination is made whether that polygon is located at least partially inside a selected one of the smaller rectangular areas in the selected rectangular area. If so, which pixels of the plurality of pixels in the selected smaller rectangular area are inside the polygon are identified. Or, if that polygon is not located at least partially inside the selected smaller rectangular area, no further processing of the polygon is performed at one or more of the plurality of pixels in the smaller rectangular area.

Abstract: Apparatus and method for a multi-frequency vertex shader. For example, one embodiment of a graphics processing apparatus comprises a plurality of vertex caches to store vertex data associated with graphics primitives; and graphics execution circuitry to execute vertex shaders operable at different processing rates for different sets of the vertex data, each of the different sets of vertex data to having a different type of identifier associated therewith to identify the vertex data.

Abstract: A fragment shader program to be executed by a fragment shader of a graphics processor can include a graphics texturing instruction that when executed by the fragment shader will cause the fragment shader to send a request to the texture mapper to perform a graphics texture mapping operation in which the texture mapper will perform plural lookups from the same texture in parallel. In response to the request from the fragment shader, the texture mapper of the graphics processor performs plural lookups from the same texture in parallel, and generates a texture mapping operation result using the results of the plural lookups from the same texture for returning to the fragment shader.

Abstract: A method and system for dynamically transferring graphical image processing operations from a graphical processing unit (GPU) to a digital signal processor (DSP). The method includes estimating the number of operations needed for the processing a set of image data; determining the operational limits of a GPU and compare with estimated number of operations and if the operational limits are exceeded; transfer the processing operations to the DSP from the GPU. The transfer can include transferring a portion of executable code for performing the processing operations, and generating a replacement code for the GPU. The DSP can then process a portion of the image data before sending it to the GPU for further processing.

Abstract: A cache system in a graphics processing system stores graphics data items for use in rendering primitives. It is determined whether graphics data items relating to primitives to be rendered are present in the cache, and if not then computation instances for generating the graphics data items are created. Computation instances are allocated to tasks using a task assembly unit which stores task entries for respective tasks. The task entries indicate which computation instances have been allocated to the respective tasks. The task entries are associated with characteristics of computation instances which can be allocated to the respective tasks. A computation instance to be executed is allocated to a task based on the characteristics of the computation instance. SIMD processing logic executes computation instances of a task outputted from the task assembly unit to thereby determine graphics data items, which can be used to render the primitives.

Abstract: Methods, systems, and apparatuses are described herein for providing an interactive application, such as a video game, with a hierarchy of avatar categories, each having a maximum and minimum progression value. Each avatar category may be associated with one or more avatars, items, and/or other portions of the interactive application. A beginner avatar category may be associated with a minimum progression value greater than an absolute minimum progression value and a maximum progression value lesser than an absolute maximum progression value. A second avatar category may be associated with a minimum and maximum progression value that are, respectively, lower and greater than that of the beginner avatar category. The interactive application may allow a user to select from the beginner avatar category and the second avatar category. An avatar category may be associated with game rewards.

Abstract: The disclosure provides an approach for modifying a kernel by adding conditional halting points. The disclosure also provides an approach for modifying a kernel by implementing a virtual shared memory between an application running on a CPU and a workload running on a compute accelerator. The disclosure provides an approach for setting up the kernel and its working set on a compute accelerator, executing the workload, suspending the workload, and then resuming the workload at a later time, optionally on a different host computer.

Abstract: Systems, apparatuses, and methods for implementing pixel wait synchronization techniques are disclosed. A system includes a host processor and a graphics processor which includes at least one graphics pipeline. During execution of a graphics application, the host processor determines that a second draw call is dependent on a first draw call. The host processor issues a wait sync event prior to issuing the second draw call to the graphics pipeline responsive to determining that the first draw call is still in-flight in the graphics pipeline. After the second draw call is issued to the graphics pipeline, the second draw call is processed by one or more stages of the graphics pipeline while the first draw call is still in-flight. The graphics pipeline stalls the second draw call at a given intermediate stage until a corresponding event counter equals a value specified by the wait sync event.

Abstract: Systems, methods, and computer readable media to improve the operation of graphics systems are described. In general, techniques are disclosed for determining the computational need of GPU-centric elements executing from within pages of another application, selecting one or more GPU's appropriate to the need, and transitioning the system to the selected GPUs.

Abstract: According to an embodiment of the present invention, a system filters a collection of application programming interfaces based on input data representing information of a document to be processed, and generates a pipeline of filtered application programming interfaces. Each filtered application programming interface is sequentially executed within the pipeline. The document may be processed through the pipeline and visualizations based on the processing of the document may be generated, allowing the pipeline to be refined to produce desired output data selected within the visualizations. Embodiments of the present invention further include a method and computer program product for generating a pipeline of filtered application programming interfaces in substantially the same manner described above.

Abstract: Display pipeline may manage allocation of total memory bandwidth to memory access requester blocks (e.g., display pipeline as a whole and/or a block in the display pipeline) by dynamically allocating the total memory bandwidth based at least in part on a calculated bandwidth floor to reduce the communication inefficiency (e.g., underruns), excessive power consumption, and image quality degradation of the display pipeline. Image fetch parameters, electronic display parameters, display pipeline parameters, and memory access requester block parameters may be used to determine the appropriate bandwidth floor for each memory access requester of the display pipeline. Additional memory bandwidth may be allocated to memory access requesters of the display pipeline when available bandwidth remains to further reduce likelihood of subsequent communication inefficiencies in the display pipeline.

Abstract: One aspect of the current disclosure provides a method of upscaling an image. The method includes: rendering an image, wherein the rendering includes generating color samples of the image at a first resolution and depth samples of the image at a second resolution, which is higher than the first resolution; and upscaling the image to an upscaled image at a third resolution, which is higher than the first resolution, using the color samples and the depth samples.

Abstract: Disclosed aspects relate to operation efficiency management in a shared pool of configurable computing resources. A first set of processing operations of a first application may be detected. A second set of processing operations of a second application may be detected. The first set of processing operations of the first application may be compared with the second set of processing operations of the second application. A substantial match of the first and second processing operations of the first and second applications may be determined. A single set of processing operations for both the first and second applications may be established.

Abstract: Multi-pass apparatus and method for ray tracing shading.

Abstract: Examples described herein generally relate to intercepting, from a graphics processing unit (GPU) or a graphics driver, a buffer that specifies one or more shader records of a shader table to use in generating the image using raytracing, determining, based at least in part on an identifier of the one or more shader records, a layout of the one or more shader records, interpreting, based at least in part on the layout, additional data in the buffer to determine one or more parameters corresponding to the one or more shader records, and displaying, via an application, an indication of the one or more parameters on an interface.

Abstract: Techniques are disclosed relating to controlling an operand cache in a pipelined fashion. An operand cache may cache operands fetched from the register file or generated by previous instructions to improve performance and/or reduce power consumption. In some embodiments, instructions are pipelined and separate tag information is maintained to indicate allocation of an operand cache entry and ownership of the operand cache entry. In some embodiments, this may allow an operand to remain in the operand cache (and potentially be retrieved or modified) during an interval between allocation of the entry for another operand and ownership of the entry by the other operand. This may improve operand cache efficiency by allowing the entry to be used while to retrieving the other operand from the register file, for example.

Abstract: Methods and devices for rendering visible primitives in a scene of an application may include loading a primitive visibility buffer that includes a plurality of primitives representing at least one instance in a scene of the application. The primitive visibility buffer may include for each primitive of the plurality of primitives a visibility bit that describes a visibility state as visible or not visible for each of the plurality primitives. The methods and devices may include determining whether each of the plurality of primitives are visible in the scene based on the visibility bit, rendering a primitive when the visibility bit for the primitive indicates that the primitive is visible, and skipping the rendering of the primitive when the visibility bit indicates that the primitive is not visible. The methods and devices may also include combing pre-computed visibility states with runtime visibility testing when rendering the visibility bits.

Abstract: The present disclosure relates generally to serial communication links and, more specifically, to events communicated on serial communication links and the timing of those events, for example, to achieve uniform delay among multiple event transmissions.

Abstract: A graphics processing unit (GPU) includes a plurality of programmable processing cores configured to process graphics primitives and corresponding data and a plurality of fixed-function hardware units. The plurality of processing cores and the plurality of fixed-function hardware units are configured to implement a configurable number of virtual pipelines to concurrently process different command flows. Each virtual pipeline includes a configurable number of fragments and an operational state of each virtual pipeline is specified by a different context. The configurable number of virtual pipelines can be modified from a first number to a second number that is different than the first number. An emulation of a fixed-function hardware unit can be instantiated on one or more of the graphics processing cores in response to detection of a bottleneck in a fixed-function hardware unit. One or more of the virtual pipelines can then be reconfigured to utilize the emulation instead of the fixed-function hardware unit.

Abstract: When processing graphics fragments within a processing stage of a graphics processing pipeline, wherein the graphics fragments each represent a set of one or more sampling points to be processed, comparing sampling points with each other at an input of the processing stage to determine whether multiple of the sampling points would give the same processing result when processed by the processing stage so that a first one of the sampling points can be processed and the processing result for that sampling point can then be duplicated at the output for other processing results determined to give the same processing result.

Abstract: The present disclosure describes techniques for removing unnecessary processing stages from a graphics processing pipeline based on the format of data passed between the stages. Starting with a stage at a middle point in a pipeline, formats of data that are input to and output from the middle stage may be compared to each other. If the formats match, the middle stage may be removed from the pipeline. Thereafter, the format of data input to a pair of middle stages of the pipeline and output from the pipeline may be compared and, if they match, the middle pair may be deleted. This process may repeat until a middle pair is found where no match occurs between the input and output format. The remaining stages of the pipeline may be retained. In cases where a pipeline is not symmetrical, the formats of data at each node may be compared to each other.

Abstract: The present disclosure relates generally to serial communication links and, more specifically, to events communicated on serial communication links and the timing of those events. The events may be communicated according to a prioritization process.

Abstract: A system for reducing non-linearity in mixed signal processing using complex polynomial vector processor 102 is provided. The complex polynomial vector processor 102 includes a data processing unit (104) and a co-efficient feeder unit (106). The data processing unit (104) converts a high-speed data stream into a polar-like format (PL) data and calculates required polynomial powers for the high-speed data stream using the PL format data. The data processing unit (104) includes a multiplier accumulator (MAC) unit (206) that generates processed high-speed data and a delay unit (208) that combines time separated input with the processed high-speed data to generate output data with reduced non-linearity.

Abstract: A data processing system replicates the operation of a target graphics processor under test by making use of a native graphics processor of the data processing system. The native graphics processor is provided with executable program instructions that replicate some or all of the fixed function operations of the target graphics processor. The programmable processing circuitry of the graphics processor of the data processing system can then generate an output by executing the executable program instructions, rather than by using fixed function processing circuitry of the graphics processor of the data processing system. The data processing system can provide a “bit-exact” testing environment when replicating the operation of the target graphics processor using the native graphics processor, for example where the target graphics processor and native graphics processor are configured very differently from one another.

Abstract: In one embodiment, an apparatus having an integrated circuit made of substrate, at least three light emitters arranged on the substrate, and driver circuitry located on the integrated circuit, the driver circuitry to drive an ultra low persistence display to remove ghosting and nausea.

Abstract: Performance counters provided in a graphics processor unit (GPU) are used to provide values used to make a determination of GPU activity so that power management can be exercised. In preferred embodiments counter values relating to computation unit idle times, computation unit stall times, DRAM bandwidth and computation unit stall times due to a sampler wait are utilized to determine performance level. If performance is above a minimum level but the GPU is above certain idleness determinations provided by those values, the GPU can have portions powered down to reduce power consumption while not having a noticeable effect on operations. Based on the various counter values, portions of the GPU can be turned off or disabled to reduce power consumption without having a noticeable effect on perceived GPU performance.

Abstract: A clip-cull-viewport (CCV) unit manages information associated with vertices of a primitive as the primitive passes through the CCV unit. The CCV unit includes an index cache and a cache-status table. Vertices of a received primitive are stored in locations within the index cache based on attribute and index fields of the primitive. If a vertex is a reused vertex of another primitive that matches a valid entry in the cache-status table and if the primitive survives being culled, the valid entry in the cache-status table is preserved, the attribute field of the primitive is set to indicate that the vertex is a reused vertex, and the primitive is sent to an output interface for a downstream unit. Otherwise, the attribute field is set to indicate that the vertex is not reused, and the primitive is sent to the output interface for the downstream unit.

Abstract: The present invention relates to a method for high-speed parallel processing for an ultrasonic signal, the method used for generation of an ultrasonic image by a smart device, which is provided with a mobile graphic processing unit (GPU), by receiving an input of an ultrasonic signal.

Abstract: A method of rendering an image of three-dimensional laser scan data is described. The method includes providing a set of laser scan data for a given scan as a spherical displacement map and generating a tessellation pattern by sampling the spherical displacement map. A graphics processing unit may generate the tessellation pattern.

Abstract: A method for packet processing on a multi-core processor. According to one embodiment of the invention, a first set of one or more processing cores are configured to include the capability to process packets belonging to a first set of one or more packet types, and a second set of one or more processing cores are configured to include the capability to process packets belonging to a second set of one or more packet types, where the second set of packet types is a subset of the first set of packet types. Packets belonging to the first set of packet types are processed at a processing core of either the first or second set of processing cores. Packets belonging to the second set of packet types are processed at a processing core of the first set of processing cores.

Abstract: Systems, methods, and apparatuses relating to integrated control and data processing in a configurable spatial accelerator are described.

Abstract: Improvements to graphics processing pipelines are disclosed. More specifically, the vertex shader stage, which performs vertex transformations, and the hull or geometry shader stages, are combined. If tessellation is disabled and geometry shading is enabled, then the graphics processing pipeline includes a combined vertex and graphics shader stage. If tessellation is enabled, then the graphics processing pipeline includes a combined vertex and hull shader stage. If tessellation and geometry shading are both disabled, then the graphics processing pipeline does not use a combined shader stage. The combined shader stages improve efficiency by reducing the number of executing instances of shader programs and associated resources reserved.

Abstract: According to an aspect, a display apparatus includes: a plurality of pixels each of which includes a memory for storing a signal; a plurality of image signal lines each of which is configured to supply the signal; a plurality of switches each of which is included in a corresponding one of the pixels and couples a corresponding one of the image signal lines to the memory of the corresponding one of the pixels; a plurality of gate signal lines; a plurality of logic circuits coupled in series, the logic circuit at a most upstream stage being configured to receive a control signal, and each of the logic circuits being configured to output an output signal; and a plurality of control circuits each of which is configured to output a gate signal to a corresponding one of the gate signal lines based on the control signal or the output signal.

Abstract: An electro-optical sensor chip assembly (SCA) that includes a detection device that includes an array of detector unit cells arranged in a matrix and that produce an electrical output in response to light. The SCA also includes an integrated control circuit in electrical communication with the detection device that includes a control word store to store a dataword. The control word store includes at least three sub-latches to redundantly store at least one bit of the dataword. The at least three sub-latches include a first sub-latch, a second sub-latch and a third sub-latch, each of the first sub-latch, the second sub-latch and the third sub-latch including an output and two recovery inputs, and the output of the first and third sub-latches are connected to the recovery inputs of the second sub-latch.

Abstract: An image processing device includes a viewpoint separating unit configured to separate multi-viewpoint image data, including images of multiple viewpoints and representing intensity distribution of light and the direction of travel of light according to positions and pixel values of pixels, into a plurality of single-viewpoint image data for each of the individual viewpoints; and a parallax control unit configured to control amount of parallax between the plurality of single-viewpoint image data obtained by separation into individual viewpoints by the viewpoint separating unit.

Abstract: A method of processing a print job where a distribution strategy is determined for how a print job is to be distributed to a plurality of image processors for image processing based on at least one predetermined rule, and where distribution of the print job to at least one image processor of the plurality of image processors is controlled using the determined distribution strategy.

Abstract: A holographic display system for generating a super hologram with full parallax in different fields of view in the horizontal and vertical directions. The display system includes assemblies or subsystems each adapted to combine holographic displays and coarse integral displays to produce or display a coarse integral hologram. Briefly, the display system described herein teaches techniques for enhancing operations of coarse integral holographic (CIH) displays. The enhanced CIH displays may utilize ganged scanners, may operate scanners to provide boustrophedon scanning, may be configured to add color information such by view sequential color hologram display and scanning, may replace or supplement X-Y scanning abilities with a resonant scanner, and may replace physical lenslet arrays by generating and displaying a holographic lenslet for each elemental hologram used to create the super hologram.

Abstract: An image coding method in which a chroma component and a luma component of an input image including one or more transform blocks are transformed to code the input image. The luma component has the same size as the current transform block. The chroma component is smaller than the current transform block. In the method, when the current transform block has a first minimum size, the chroma component is transformed on a basis of a block resulting from binding a plurality of the chroma blocks to has the same size as the luma block, and when the current transform block has a size other than the first minimum size, a CBF flag indicating whether or not coefficients of the chroma component include a non-zero coefficient is not coded.

Abstract: A program is analyzed to identify instructions that will load external data and to determine whether such instructions are followed by a sequence of instructions that will produce the same result for each thread in a thread group if the data loaded by the load instruction is the same for each thread in the thread group. Each time there is an external load instruction, it is determined whether the data loaded by the external load instruction is the same for all threads of the thread group, and whether the external load instruction was indicated as being followed by a sequence of instructions that produce the same result if the external load instruction loads the same data value for each thread of a thread group. The subsequent instructions are then executed for only a single thread of the thread group, or for all the threads of the thread group.

Abstract: Various embodiments provide methods, devices, and non-transitory processor-readable storage media enabling joint goals, such as joint power and performance goals, to be realized on a per heterogeneous processing device basis for heterogeneous parallel computing constructs. Various embodiments may enable assignments of power states for heterogeneous processing devices on a per heterogeneous processing device basis to satisfy an overall goal on the heterogeneous processing construct. Various embodiments may enable dynamic adjustment of power states for heterogeneous processing devices on a per heterogeneous processing device basis.

Abstract: Examples of methods, systems, apparatus, and machine-readable storage media are provided to facilitate access and control of a remote desktop of a remote machine by a windows web browser of a client device through a web server without installing proprietary plug-ins or protocols on the client device. A web server may translate user input requests from a web browser into input calls compatible with a remote desktop display protocol. The web server may receive remote desktop drawing commands from the remote machine and translate the remote desktop drawing commands into web browser drawing updates compatible with the windows web browser. A web server may communicate with the windows web browser via HTTP and communicate with the remote machine via a remote desktop display protocol.

Abstract: An apparatus has processing circuitry to execute instructions from multiple threads and hardware registers to store context data for the multiple threads concurrently. At a given time a certain number of software-scheduled threads may be scheduled for execution by software executed by the processing circuitry. Hardware thread scheduling circuitry is provided to select one or more active threads to be executed from among the software-scheduled threads. The hardware thread scheduling circuitry adjusts the number of active threads in dependence on at least one performance metric indicating performance of the threads.

Abstract: A cache system in a graphics processing system stores graphics data items for use in rendering primitives. It is determined whether graphics data items relating to primitives to be rendered are present in the cache, and if not then computation instances for generating the graphics data items are created. Computation instances are allocated to tasks using a task assembly unit which stores task entries for respective tasks. The task entries indicate which computation instances have been allocated to the respective tasks. The task entries are associated with characteristics of computation instances which can be allocated to the respective tasks. A computation instance to be executed is allocated to a task based on the characteristics of the computation instance. SIMD processing logic executes computation instances of a task outputted from the task assembly unit to thereby determine graphics data items, which can be used to render the primitives.

Abstract: Examples of methods, systems, apparatus, and machine-readable storage media are provided to facilitate access and control of a remote desktop of a remote machine by a web browser of a client device through a web server without installing proprietary plug-ins or protocols on the client device. A web server may translate user input requests from a web browser into input calls compatible with a remote desktop display protocol. The web server may receive remote desktop drawing commands from the remote machine and translate the remote desktop drawing commands into web browser drawing updates compatible with the web browser. A web server may communicate with the web browser and the remote machine via HTTP and a remote desk top display protocol, respectively.

Abstract: In the cull pipe, positions of the vertices of a triangle have already been computed and these coordinates may be exploited by taking and sorting triangle groups based on these coordinates. As one example, all the triangles in a tile may constitute a group. The triangle groups are sorted into bins. Within each bin the triangles are sorted based on their depths.

Abstract: An index is assigned to each entry in the set of possible coverage masks and two functions are generated. One function translates an index to a coverage mask. Also, a sparse function generates an index from a coverage mask. These functions may be realized in hardware and are used during decompression and compression, respectively.

Abstract: A system, method, and computer-readable medium to receive a request to render a visualization, the visualization being defined by at least one dimension of a data set and being one of multiple visualizations belonging to a story; determine whether the at least one dimension of the visualization has a color assigned thereto; automatically assign, in an instance the at least one dimension of the visualization lacks a color assignment, a color to the at least one dimension of the visualization; store the color assigned to the at least one dimension in a color synchronization map; render, in response to the request, all visualizations in the story with the at least one dimension in the color assigned thereto in the color synchronization map.

Abstract: Systems, apparatus and methods are described including distributing batches of geometric objects to a multi-core system, at each processor core, performing vertex processing and geometry setup processing on the corresponding batch of geometric objects, storing the vertex processing results shared memory accessible to all of the cores, and storing the geometry setup processing results in local storage. Each particular core may then perform rasterization using geometry setup results obtained from local storage within the particular core and from local storage of at least one of the other processor cores.

Abstract: A mapping apparatus comprises a mapper that translates from an input key to an output key in one or more storage devices. A pre-mapper for processing update operations comprises a plurality of mapping tablets and an in-memory look-up filter to identify a given mapping table storing a given input key. The mapping tablets comprise at least one dynamic in-memory ingress tablet and a plurality of persisted frozen tablets. For a given update operation, a first entry is added to one dynamic in-memory ingress tablet comprising the input key for the given update operation and a corresponding output key where data for the given update operation is stored; and a second entry is added to the look-up filter comprising the input key of the first entry and an identifier of the dynamic in-memory ingress tablet storing the first entry for the given update operation. The dynamic in-memory ingress tablet is persisted as a persisted frozen tablet.