Abstract: The graphics processing unit described herein is configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles. The graphics processing unit comprises a tiling unit and rendering logic. The tiling unit is arranged to generate a tile control list for each tile, the tile control list identifying each graphics data item present in the tile. The rendering logic is arranged to render the tiles using the tile control lists generated by the tiling unit. The tiling unit comprises per-tile hash generation logic arranged to generate, for each tile, a per-tile hash value based on a set of textures that will be accessed when processing the tile in the rendering logic, and the tiling unit is further arranged to store the per-tile hash value for a tile within the tile control list for the tile.

Abstract: In an example method, a computer system accesses first data representing three-dimensional content and a plurality of bounding boxes. Each of the bounding boxes encloses at least a portion of the three-dimensional content. The computer system also access second data representing a viewing frustum for rendering the three-dimensional content. Based on the first and the second data, the computer system identifies a subset of the bounding boxes that are visible according to the viewing frustum. For each of the one or more bounding boxes of the subset, the computer system identifies an image tile from among a plurality of image tiles corresponding to the bounding box, and renders one or more video frames in a frame buffer based on the identified image tile.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including applying an ordered set of error-handling operations to be performed on data residing in a segment of the memory device as an input to a trained machine learning model, wherein the trained machine learning model is based on latency data for previously-performed error-handling operations; and obtaining an output of the trained machine learning model, the output comprising a reordered set of error-handling operations to be performed on the data residing in the segment of the memory device, and wherein the reordered set adjusts an order of one or more error-handling operations of the ordered set of error-handling operations.

Abstract: Systems and methods are provided for performing random walk graph computing. One method may comprise generating a subset of walkers on a graph, maintaining the generated subset of walkers in a walker pool in a memory, loading a coarse-grained block of the graph from a non-volatile storage into a block buffer of the memory, generating pre-sampled edges for vertices in the coarse-grained block, storing the pre-sampled edges into a pre-sampled edge buffer allocated for the coarse-grained block and moving one or more walkers of the generated subset of walkers using the pre-sampled edges stored in the pre-sampled edge buffer. The generated subset of walkers may have an initial number determined based on a memory space allocated to the walker pool.

Abstract: A network architecture including network storage. The network architecture includes a plurality of streaming arrays, each streaming array including a plurality of compute sleds, wherein each compute sled includes one or more compute nodes. The network architecture includes a PCI Express (PCIe) fabric configured to provide direct access to the network storage from compute nodes of each of the plurality of streaming arrays, the PCIe fabric including a plurality of array-level PCIe switches, each array-level PCIe switch communicatively coupled to compute nodes of compute sleds of a corresponding streaming array and communicatively coupled to the storage server. The network storage is shared by the plurality of streaming arrays.

Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may process a first workload of a plurality of workloads at each of multiple clusters in a GPU pipeline. The apparatus may also increment a plurality of performance counters during the processing of the first workload at each of the multiple clusters. Further, the apparatus may determine, at each of the multiple clusters, whether the first workload is finished processing. The apparatus may also read, upon determining that the first workload is finished processing, a value of each of the multiple clusters for each of the plurality of performance counters. Additionally, the apparatus may transmit an indication of the read value of each of the multiple clusters for all of the plurality of performance counters.

Abstract: A computing device may receive a set of user documents. Data may be extracted from the documents to generate a first graph data structure with one or more initial graphs containing key-value pairs. A model may be trained on the first graph data structure to classify the pairs. Until a set of evaluation metrics for the model exceeds a set of deployment thresholds: generating, a set of evaluation metrics may be generated for the model. The set of evaluation metrics may be compared to the set of deployment thresholds. In response to a determination that the set of evaluation metrics are below the set of deployment thresholds: one or more new graphs may be generated from the one or more initial graphs in the first graph data structure to produce a second graph data structure. The first and second graph can be used to train the model.

Abstract: An image display method includes: displaying, on a user interface, a first image loaded into a first image container in a sliding container; adding a second image container to the sliding container in response to an image switching instruction; loading a second image into the second image container, and the second image being an image located behind the first image in a queue of images to be played; and displaying the second image on the user interface.

Abstract: Disclosed are an image processing method and device using a line-wise operation. The image processing device, according to one embodiment, comprises: a receiver for receiving an image; a first convolution operator for generating a feature map by performing a convolution operation on the basis of the image; and a compressor for compressing the feature map into units of at least one line; and a decompressor for reconstructing the feature map compressed into units of lines.

Abstract: A system includes a display subsystem. The display subsystem includes a shared buffer having allocated portions, each allocated to one of a plurality of display threads, each display thread associated with a display peripheral. The display subsystem also includes a direct memory access (DMA) engine configured to receive a request from a main processor to deallocate an amount of space from a first allocated portion associated with a first display thread. In response to receiving the request, the DMA engine deallocates the amount of space from the first allocated portion and shifts the allocated portions of at least some of other display threads to maintain contiguity of the allocated portions and concatenate free space at an end of the shared buffer.

Abstract: There is described a method of shading a group of pixels in a fragment shader in a raster graphics pipeline. At least one first pilot pixel of the group of pixels is shaded under a first precision. At least one second pilot pixel of the group of pixels is shaded under a second precision. An error value representing a difference between the first and second pilot pixels is calculated. At least one other pixel of the group of pixels is shaded under the first precision if the error value is greater than an error threshold. The at least one other pixel is shaded under the second precision if the error value is smaller than the error threshold.

Abstract: A processing system concurrency optimization system includes a processing system having first and second processing subsystems, a power system that is coupled to the first and second processing subsystems, a processing system concurrency optimization database, and a processing system concurrency optimization subsystem that is coupled to the power system and the processing system concurrency optimization database. The processing system concurrency optimization subsystem determines that a first workload has been provided for performance by the processing system, and identifies a first processing system concurrency optimization profile that is associated with the first workload in the processing system concurrency optimization database.

Abstract: A graphics rendering method includes obtaining, by a central processing unit (CPU), to-be-processed vertex data. The to-be-processed vertex data is vertex data used by a graphics processing unit (GPU) for graphics rendering processing. The method also includes processing, by the CPU, the to-be-processed vertex data to obtain vertex data within a field of view of a user. The method additionally includes sending, by the CPU, the vertex data within the field of view of the user to the GPU for the graphics rendering processing.

Abstract: A processing device having a graphical user interface includes a touch screen display that receives touch gesture commands from a vehicle operator and a controller. In operation, computer code implements a set of widgets such that at least one widget is normally viewable on the touch screen display. The set of widgets are organized to include at least one home screen, such as a motion home screen that displays at least one travel related widget, a lift home screen that displays at least one lift related widget, etc. When a current operating state of a control module of the industrial vehicle indicates that a designated control is engaged, the controller causes the display to snap to the associated home screen position.

Abstract: An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.

Abstract: A graphics processing unit having multiple groups of processor cores for rendering graphics data for allocated tiles and outputting the processed data to regions of a memory resource. Scheduling logic allocates sets of tiles to the groups of processor cores to perform a first render, and at a time when at least one of the groups has not completed processing its allocated sets of one or more tiles as part of the first render, allocates at least one set of tiles for a second render to one of the other groups of processor cores for processing. Progress indication logic indicates progress of the first render, indicating regions of the memory resource for which processing for the first render has been completed. Progress check logic checks the progress indication in response to a request for access to a region of the memory resource as part of the second render and enables access that region of the resource in response to an indication that processing for the first render has been completed for that region.

Abstract: A driving signal processing method for a large touch display integrated (LTDI) system is provided. The LTDI system includes plural LTDI chips that are concatenated. The LTDI chips include a master LTDI chip and plural slave LTDI chips. The driving signal processing method includes: receiving, by the LTDI chips, display data from a timing controller; and dispersedly outputting, by the master LTDI chip and at least one of the slave LTDI chips, M gate control signals respectively corresponding to M gate lines of a display panel of the LTDI system according to the display data during the display stage of the display panel.

Abstract: Techniques for rendering two-dimensional vector graphics are described. The techniques include using a central processing unit to generate tessellate triangles along a vector path in which each of the tessellate triangles is represented by a set of vertices. From the tessellate triangles, an index buffer and a compressed vertex buffer are generated. The index buffer includes a vertex index for each vertex of each of the tessellate triangles. The compressed vertex buffer includes a vertex buffer entry for each unique vertex that maps to one or more vertex indices of the index buffer. The index buffer and the compressed vertex buffer are provided to a graphics processing unit to render the vector path with anti-aliasing.

Abstract: A method of operating a tile-based graphics processor that executes a graphics processing pipeline is disclosed. When there are no more primitives left to be provided for processing to the pipeline for a rendering tile, it is determined whether any remaining processing steps for the rendering tile can be omitted, e.g. because they will not affect a buffer that will be output when the rendering tile is complete. When it is determined that a processing step can be omitted, that processing step is omitted.

Abstract: A data path interface circuit includes: a writing path module, connected to an internal port and an external port and configured to transmit stored data to the internal port from the external port; a reading path module, connected to the internal port and external port respectively and configured to transmit the stored data to the external port from the internal port; a first delay module, connected to the external port and internal port respectively, and configured to obtain the stored data from the external port or internal port, perform delay processing on the stored data, and transmit the delayed stored data to the writing path module and/or reading path module; and a delay control module, connected to the first delay module and configured to receive a signal instruction from external and control delay time for the first delay module to perform the delay processing according to the signal instruction.

Abstract: Methods and tiling engines for storing tiling primitives in a graphics processing system.

Abstract: A decoder is configured to decode a plurality of texels from a received block of texture data encoded according to the Adaptive Scalable Texture Compression (ASTC) format, and includes a parameter decode unit configured to decode configuration data for the received block of texture data, a colour decode unit configured to decode colour endpoint data for the plurality of texels of the received block in dependence on the configuration data, a weight decode unit configured to decode interpolation weight data for each of the plurality of texels of the received block in dependence on the configuration data, and at least one interpolator unit configured to calculate a colour value for each of the plurality of texels of the received block using the interpolation weight data for that texel and a pair of colour endpoints from the colour endpoint data.

Abstract: Methods and systems of routing a design layout include setting an inner region and an outer region for modification of structures in an original design layout, in accordance with a minimum spacing that is based on a fabrication process. Routing of trim positions and conductive wire extents is performed within the inner region, based on positions of shapes within the outer region, including node folding of a new constraint graph to minimize perturbations from a previous constraint graph, to generate an updated design layout that can be manufactured using the fabrication process.

Abstract: A computing device may access visually rich documents comprising an image and metadata. A graph, based on the image or metadata, can be generated for a visually rich document. The graph's nodes can correspond to words from the visually rich document. Features for nodes can be determined by the device. The device may generate model labeled graphs by assigning a pseudo-label to nodes using a pretrained model. The device may generate a plurality of graph labeled graphs by assigning a pseudo-label to nodes by matching a first node from a first graph to at least a second node from a second graph. The device may generate a plurality of updated graphs by cross referencing labels from the model labeled graphs and the graph labeled graphs. Until a change in labels is below a threshold, a model can be trained to perform key-value extraction using the updated graphs.

Abstract: An image dataset is processed with a shadow map generated from objects in a virtual scene that can cast shadows and the scene is rendered independent of the shadows. The shadow might be edited separately, and then applied to a post-render image of the scene to form a shadowed image. Light factor values for pixels of the shadow map might be stored as summed-area table values.

Abstract: Methods for graphics processing are provided. One example method includes executing a plurality of kernels using a plurality of graphics processing units (GPUs), wherein responsibility for executing a corresponding kernel is divided into one or more portions each of which being assigned to a corresponding GPU. The method includes generating a plurality of dependency data at a first kernel as each of a first plurality of portions of the first kernel completes processing. The method includes checking dependency data from one or more portions of the first kernel prior to execution of a portion of a second kernel. The method includes delaying execution of the portion of the second kernel as long as the corresponding dependency data of the first kernel has not been met.

Abstract: Systems and methods may provide for receiving a pixel shader and sending the pixel shader to shader bypass hardware if the pixel shader and a render target associated with the pixel shader satisfy a simplicity condition. In one example, the shader bypass hardware is dedicated to pixel shaders and associated render targets that satisfy the simplicity condition.

Abstract: A host computer for emulating a target system includes a host memory, a CPU, and a host GPU. The host memory is configured to store a library of graphics functions and a VM. The VM includes a section of emulated memory storing target code configured to execute on the target system. The CPU is configured to execute the VM to emulate the target system. The VM is configured to execute the target code and intercept a graphics function call in the target code. The VM is further configured to redirect the graphics function call to a corresponding graphics function in the library of graphics functions stored in the host memory. The host GPU is configured to execute the corresponding graphics function to determine at least one feature configured to be rendered on a display coupled to the host GPU.

Abstract: A method of operating a tile-based graphics processing pipeline, in which the pipeline maintains information indicating whether sample values of rendered fragment data stored in the tile buffer for a set of plural pixels (or for each set of a plurality of sets of plural pixels) have the same value.

Abstract: An apparatus comprises receivers (201, 203) receiving texture maps and meshes representing a scene from a first and second view point. An image generator (205) determines a light intensity image for a third view point based on the received data. A first view transformer (207) determines first image positions and depth values in the image for vertices of the first mesh and a second view transformer (209) determines second image positions and depth values for vertices of the second mesh. A first shader (211) determines a first light intensity value and a first depth value based on the first image positions and depth value, and a second shader (213) determines a second light intensity value and a second depth value from the second image positions depth values. A combiner (215) generates an output value as a weighted combination of the first and second light intensity values where the weighting of a light intensity value increases for an increasing depth value.

Abstract: Disclosed is a security controller for a content distribution system that generates and encodes point clouds with invisible, visually undetectable, and/or tamperproof watermarks. The controller selects a set of data points from the point cloud, and changes at least one specific bit of a set of bits that define a value for a particular non-positional element of the set of data points. The controller encodes point cloud with a first watermark that is unique to a requesting client based on the changing of the at least one specific bit. The controller distributes the file encoded with the first watermark to the requesting client and tracks the set of data points that were encoded with the first watermark in order to subsequently verify that the requesting client was the original recipient of the point cloud encoded with the first watermark.

Abstract: Disclosed herein is a processor for deep learning. In one embodiment, the processor comprises: a load and store unit configured to load and store image pixel data and stencil data; a register unit, implementing a banked register file, configured to: load and store a subset of the image pixel data from the load and store unit, and concurrently provide access to image pixel values stored in a register file entry of the banked register file, wherein the subset of the image pixel data comprises the image pixel values stored in the register file entry; and a plurality of arithmetic logic units configured to concurrently perform one or more operations on the image pixel values stored in the register file entry and corresponding stencil data of the stencil data.

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

Abstract: A method and apparatus for vascular assessment are disclosed. The apparatus, in some embodiments, receives a plurality of 2-D angiographic images of a portion of a vasculature of a subject, and processes the images to produce a stenotic model over the vasculature. The stenotic model has measurements of the vasculature at one or more locations along vessels of the vasculature. The apparatus, in some embodiments, determines a flow characteristic of the stenotic model and calculates an index indicative of vascular function, based, at least in part, on the flow characteristic in the stenotic model.

Abstract: A method of deferred vertex attribute shading includes computing, at a graphics processing pipeline of a graphics processing unit (GPU), a plurality of vertex attributes for vertices of each primitive of a set of primitives. The plurality of vertex attributes to be computed includes a vertex position attribute and at least a first non-position attribute for each primitive. One or more primitives of the set of primitives that do not contribute to a rendered image are discarded based upon the vertex position attribute for vertices of the set of primitives. A set of surviving primitives is generated based on the culling and deferred attribute shading is performed for at least a second non-position attribute for vertices of the set of surviving primitives.

Abstract: Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in at least a form of decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and destination memory information, and execution circuitry to execute the decoded instruction to store each data element of configured rows of the identified source matrix operand to memory based on the destination memory information.

Abstract: One embodiment provides a method, including: receiving a process flow diagram element of a process flow diagram; identifying a context of the process flow diagram element, wherein the identifying a context comprises identifying (i) categories of elements connected to the process flow diagram element, (ii) swimlanes within the process flow diagram, and (iii) text included in the process flow diagram; encoding features of the process flow diagram element into a semantic vector, wherein the features are identified from the context of the process flow diagram element; and predicting, utilizing a process flow diagram model, a process flow diagram element for the process flow diagram based upon the at least one process flow diagram element, wherein the process flow diagram model receives and analyzes the features of the at least one process flow diagram and outputs the predicted process flow diagram element.

Abstract: A computer program compiled for a machine learning accelerator hardware and associated with a default input data size is received. An execution of an operation of the computer program is initiated. It is identified that a data size of an input data of the operation is smaller than the default input data size. The smaller data size of the input data of the operation rather than the default input data size is caused to be transferred to the machine learning accelerator hardware for the input data of the operation.

Abstract: Embodiments are provided for providing workflow pipeline optimization in a computing environment. Execution of a workflow containing dependencies between one or more subject nodes and one or more observer nodes may be dynamically optimized by determining a wait time between successive executions of the workflow for the one or more observer nodes.

Abstract: This method for generating graphic surfaces to be displayed on a screen is implemented by a graphics processor and comprises: generating a first graphic surface to be displayed on the screen; switching between generating the first graphic surface and generating a second graphic surface; generating the second graphic surface to be displayed on the screen; the switching including saving a graphic execution context of the first graphic surface; and if the generation of the second graphic surface had been interrupted during a preceding switch with the generation of another graphic surface, restoring a graphic execution context of the second graphic surface, the restored context having been saved during said preceding switch.

Abstract: One embodiment provides a method, including: obtaining a business process model representing a process flow having a plurality of steps for performing a business process, the business process model being a graphical representation of the process flow and including geometrical shapes representing activities of the process flow and edges representing a temporal ordering of the activities of the process flow; identifying important activities of the business process model; and generating a summary business process model from the business process model, wherein the summary business process model comprises nodes representing the important activities and excludes other nodes included within the business process model.

Abstract: A method and apparatus for vascular assessment are disclosed. The apparatus, in some embodiments, receives, from a medical imaging device, a medical image of a coronary vessel tree of a subject and calculates a plurality of geometric measurements associated with individual portions of a vascular segment of the coronary vessel tree. The apparatus also determines a plurality of resistances associated with the plurality of geometric measurements associated with the individual portions of the vascular segment and determines a plurality of pressure drops across the individual portions of the vascular segment based on the determined resistances and a calculated or estimated blood flow. The apparatus further calculates based on the plurality of pressure drops, a functional index indicative of a presence or an absence of a stenosis within the vascular segment.

Abstract: A system of video steganalyzer is provided. The system includes a display and a processor. The processor is configured to generate a motion vector map from a video, extract a morphological feature from the motion vector map, evaluate the morphological feature of the motion vector map, and determine if the video includes embedded information.

Abstract: Exemplary methods, apparatuses, and systems include identifying that a first cache line from a first cache is subject to an operation that copies data from the first cache to a non-volatile memory. A first portion of the first cache line stores clean data and a second portion of the first cache line stores dirty data. A redundant copy of the dirty data is stored in a second cache line of the first cache. In response to identifying that the first cache line is subject to the operation, metadata associated with the redundant copy of the dirty data is used to copy the dirty data to a non-volatile memory while omitting the clean data.

Abstract: The present disclosure is directed to dynamically prioritizing, selecting or ordering a plurality threads for execution by processor circuitry based on a quality of service and/or class of service value/indicia assigned to the thread by an operating system executed by the processor circuitry. As threads are executed by processor circuitry, the operating system dynamically updates/associates respective class of service data with each of the plurality of threads. The current quality of service/class of service data assigned to the thread by the operating system is stored in a manufacturer specific register (MSR) associated with the respective thread. Selection circuitry polls the MSRs on a periodic, aperiodic, intermittent, continuous, or event-driven basis and determines an execution sequence based on the current class of service value associated with each of the plurality of threads.

Abstract: Techniques for refinement of data pipelines are provided. An original file of serialized objects is received, and an original pipeline comprising a plurality of transformations is identified based on the original file. A first computing cost is determined for a first transformation of the plurality of transformations. The first transformation is modified using a predefined optimization, and a second cost of the modified first transformation is determined. Upon determining that the second cost is lower than the first cost, the first transformation is replaced, in the original pipeline, with the optimized first transformation.

Abstract: A decoder is configured to decode a plurality of texels from a received block of texture data encoded according to the Adaptive Scalable Texture Compression (ASTC) format, and includes a parameter decode unit configured to decode configuration data for the received block of texture data, a colour decode unit configured to decode colour endpoint data for the plurality of texels of the received block in dependence on the configuration data, a weight decode unit configured to decode interpolation weight data for each of the plurality of texels of the received block in dependence on the configuration data, and at least one interpolator unit configured to calculate a colour value for each of the plurality of texels of the received block using the interpolation weight data for that texel and a pair of colour endpoints from the colour endpoint data.

Abstract: A graphics pipeline includes a tessellator stage having a sub-patch distributor and a plurality of tessellators. The sub-patch distributor divides an input patch into a plurality of sub-primitive groups, with the primitive group limit governing the maximum permissible size for a given group of sub-primitives to be assigned to a tessellator. The sub-patch distributor recursively identifies a plurality of regions of the input patch, with the size and number of primitives of each region based on the specified primitive group limit. The sub-patch distributor assigns different regions to different sub-patch groups and distributes the sub-patch groups among the plurality of tessellators.

Abstract: A method for graphics processing including rendering graphics for an application using a plurality of graphics processing units (GPUs). The method including dividing responsibility for rendering geometry of the graphics between the GPUs based on screen regions, each GPU having a corresponding division of the responsibility which is known to the GPUs. The method including determining a Z-value for a piece of geometry during a pre-pass phase of rendering at a first GPU for an image, wherein the piece of geometry overlaps a first screen region for which the first GPU has a division of responsibility. The method including comparing the Z-value against a Z-buffer value for the piece of geometry. The method including generating information including a result of the comparing the Z-value against the Z-buffer value for use by the GPU when rendering the piece of geometry during a full render phase of rendering.

Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.