Pipeline Processors Patents (Class 345/506)
  • Patent number: 10310856
    Abstract: A program is analyzed to identify instructions that will load external data and to determine whether such instructions are followed by a sequence of instructions that will produce the same result for each thread in a thread group if the data loaded by the load instruction is the same for each thread in the thread group. Each time there is an external load instruction, it is determined whether the data loaded by the external load instruction is the same for all threads of the thread group, and whether the external load instruction was indicated as being followed by a sequence of instructions that produce the same result if the external load instruction loads the same data value for each thread of a thread group. The subsequent instructions are then executed for only a single thread of the thread group, or for all the threads of the thread group.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: June 4, 2019
    Assignee: Arm Limited
    Inventor: Kenneth Edvard Østby
  • Patent number: 10313688
    Abstract: An image coding method in which a chroma component and a luma component of an input image including one or more transform blocks are transformed to code the input image. The luma component has the same size as the current transform block. The chroma component is smaller than the current transform block. In the method, when the current transform block has a first minimum size, the chroma component is transformed on a basis of a block resulting from binding a plurality of the chroma blocks to has the same size as the luma block, and when the current transform block has a size other than the first minimum size, a CBF flag indicating whether or not coefficients of the chroma component include a non-zero coefficient is not coded.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 4, 2019
    Assignee: SUN PATENT TRUST
    Inventors: Kengo Terada, Youji Shibahara, Kyoko Tanikawa, Hisao Sasai, Toshiyasu Sugio, Toru Matsunobu
  • Patent number: 10296074
    Abstract: Various embodiments provide methods, devices, and non-transitory processor-readable storage media enabling joint goals, such as joint power and performance goals, to be realized on a per heterogeneous processing device basis for heterogeneous parallel computing constructs. Various embodiments may enable assignments of power states for heterogeneous processing devices on a per heterogeneous processing device basis to satisfy an overall goal on the heterogeneous processing construct. Various embodiments may enable dynamic adjustment of power states for heterogeneous processing devices on a per heterogeneous processing device basis.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: May 21, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Wenjia Ruan, Han Zhao, Tushar Kumar
  • Patent number: 10268332
    Abstract: Examples of methods, systems, apparatus, and machine-readable storage media are provided to facilitate access and control of a remote desktop of a remote machine by a windows web browser of a client device through a web server without installing proprietary plug-ins or protocols on the client device. A web server may translate user input requests from a web browser into input calls compatible with a remote desktop display protocol. The web server may receive remote desktop drawing commands from the remote machine and translate the remote desktop drawing commands into web browser drawing updates compatible with the windows web browser. A web server may communicate with the windows web browser via HTTP and communicate with the remote machine via a remote desktop display protocol.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: April 23, 2019
    Assignee: Wyse Technology L.L.C.
    Inventors: Stevan Kominac, Jeremy Michael Stanley, Curtis Schwebke
  • Patent number: 10261835
    Abstract: An apparatus has processing circuitry to execute instructions from multiple threads and hardware registers to store context data for the multiple threads concurrently. At a given time a certain number of software-scheduled threads may be scheduled for execution by software executed by the processing circuitry. Hardware thread scheduling circuitry is provided to select one or more active threads to be executed from among the software-scheduled threads. The hardware thread scheduling circuitry adjusts the number of active threads in dependence on at least one performance metric indicating performance of the threads.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: April 16, 2019
    Assignee: ARM Limited
    Inventors: Jose Alberto Joao, Alejandro Rico Carro, Ziqiang Huang
  • Patent number: 10255653
    Abstract: A cache system in a graphics processing system stores graphics data items for use in rendering primitives. It is determined whether graphics data items relating to primitives to be rendered are present in the cache, and if not then computation instances for generating the graphics data items are created. Computation instances are allocated to tasks using a task assembly unit which stores task entries for respective tasks. The task entries indicate which computation instances have been allocated to the respective tasks. The task entries are associated with characteristics of computation instances which can be allocated to the respective tasks. A computation instance to be executed is allocated to a task based on the characteristics of the computation instance. SIMD processing logic executes computation instances of a task outputted from the task assembly unit to thereby determine graphics data items, which can be used to render the primitives.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: April 9, 2019
    Assignee: Imagination Technologies Limited
    Inventors: Andrea Sansottera, Xile Yang, John Howson, Jonathan Redshaw
  • Patent number: 10248374
    Abstract: Examples of methods, systems, apparatus, and machine-readable storage media are provided to facilitate access and control of a remote desktop of a remote machine by a web browser of a client device through a web server without installing proprietary plug-ins or protocols on the client device. A web server may translate user input requests from a web browser into input calls compatible with a remote desktop display protocol. The web server may receive remote desktop drawing commands from the remote machine and translate the remote desktop drawing commands into web browser drawing updates compatible with the web browser. A web server may communicate with the web browser and the remote machine via HTTP and a remote desk top display protocol, respectively.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: April 2, 2019
    Assignee: Wyse Technology L.L.C.
    Inventors: Stevan Kominac, Jeremy Michael Stanley, Curtis Schwebke
  • Patent number: 10249079
    Abstract: In the cull pipe, positions of the vertices of a triangle have already been computed and these coordinates may be exploited by taking and sorting triangle groups based on these coordinates. As one example, all the triangles in a tile may constitute a group. The triangle groups are sorted into bins. Within each bin the triangles are sorted based on their depths.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Magnus Andersson, Bjorn Johnsson
  • Patent number: 10242286
    Abstract: An index is assigned to each entry in the set of possible coverage masks and two functions are generated. One function translates an index to a coverage mask. Also, a sparse function generates an index from a coverage mask. These functions may be realized in hardware and are used during decompression and compression, respectively.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: Jon N. Hasselgren, Magnus Andersson, Robert M. Toth
  • Patent number: 10235784
    Abstract: A system, method, and computer-readable medium to receive a request to render a visualization, the visualization being defined by at least one dimension of a data set and being one of multiple visualizations belonging to a story; determine whether the at least one dimension of the visualization has a color assigned thereto; automatically assign, in an instance the at least one dimension of the visualization lacks a color assignment, a color to the at least one dimension of the visualization; store the color assigned to the at least one dimension in a color synchronization map; render, in response to the request, all visualizations in the story with the at least one dimension in the color assigned thereto in the color synchronization map.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: March 19, 2019
    Assignee: SAP SE
    Inventors: Jie Yu, Sarah Menard, Tianhan Zhang, Guang Yang
  • Patent number: 10217270
    Abstract: Systems, apparatus and methods are described including distributing batches of geometric objects to a multi-core system, at each processor core, performing vertex processing and geometry setup processing on the corresponding batch of geometric objects, storing the vertex processing results shared memory accessible to all of the cores, and storing the geometry setup processing results in local storage. Each particular core may then perform rasterization using geometry setup results obtained from local storage within the particular core and from local storage of at least one of the other processor cores.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: February 26, 2019
    Assignee: INTEL CORPORATION
    Inventors: Peter L. Doyle, Jeffery S. Boles, Arthur D. Hunter, Jr., Altug Koker, Aditya Navale
  • Patent number: 10209909
    Abstract: A mapping apparatus comprises a mapper that translates from an input key to an output key in one or more storage devices. A pre-mapper for processing update operations comprises a plurality of mapping tablets and an in-memory look-up filter to identify a given mapping table storing a given input key. The mapping tablets comprise at least one dynamic in-memory ingress tablet and a plurality of persisted frozen tablets. For a given update operation, a first entry is added to one dynamic in-memory ingress tablet comprising the input key for the given update operation and a corresponding output key where data for the given update operation is stored; and a second entry is added to the look-up filter comprising the input key of the first entry and an identifier of the dynamic in-memory ingress tablet storing the first entry for the given update operation. The dynamic in-memory ingress tablet is persisted as a persisted frozen tablet.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: February 19, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Joris Wils, Peter Puhov, William C. Davenport
  • Patent number: 10210655
    Abstract: By scheduling/managing workload submission to a position only shading pipe one can exploit parallelism with minimum impact to the software scheduler in some embodiments. An interface submits workloads to a slave engine running in one parallel pipe to assist a main engine running in another parallel pipe. Command sequences for each parallel pipe are separated to enable the slave engine to run ahead of the main engine. The slave engine is a position only shader and the main engine is a render engine.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: February 19, 2019
    Assignee: Intel Corporation
    Inventors: Murali Ramadoss, Balaji Vembu, Hema C. Nalluri, Michael Apodaca, Jeffery S. Boles
  • Patent number: 10191743
    Abstract: A processor including a decode unit to decode a versatile packed data compare instruction to indicate a first source packed data operand to include a first plurality of data elements, a second source packed data operand to include a second plurality of corresponding data elements. The instruction to indicate a source comparison operation indication operand to include comparison operation indicators each to indicate a potentially different comparison operation for a different corresponding pair of data elements from the first and second source operands. An execution unit, in response to the instruction, to store a result in a destination storage location indicated by the instruction. Result to include result indicators each to correspond to a different one of the comparison operation indicators. Each result indicator to indicate a result of a comparison operation, indicated by the corresponding comparison operation indicator, performed on the corresponding pair of data elements.
    Type: Grant
    Filed: December 29, 2013
    Date of Patent: January 29, 2019
    Assignee: Intel Corporation
    Inventor: Mikhail Plotnikov
  • Patent number: 10157132
    Abstract: A method of operating a data processing system comprises maintaining record of a set of processing passes to be performed by processing pass circuitry of the data processing system. The method comprises performing cycles of operation in which it is considered whether or not the data required for a subset of processing passes is stored in a local cache. The subset of processing passes that is considered in a subsequent scan of the record comprises at least one processing pass that was not considered in the previous scan of the record, regardless of whether or not the data considered in the previous scan is determined as being stored in the cache. The method provides an efficient way to identify processing passes that are ready to be performed.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: December 18, 2018
    Assignee: Arm Limited
    Inventors: Edvard Fielding, Andreas Due Engh-Halstvedt, Jorn Nystad, Antonio Garcia Guirado, William Robert Stoye, Ian Rudolf Bratt
  • Patent number: 10152294
    Abstract: A mobile device and methods of running two platform systems or applications on the mobile device are disclosed in this invention. The mobile device includes a processing unit, a display unit and an I/O interface unit. The processing unit is configured to execute a first application of a first platform system and a second application of a second platform system different from the first platform system. The display unit is configured to display a graphic user interface of the first application. The I/O interface unit is configured to build connection to an external device and transmit data of a graphic user interface data of the second application to the external device.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: December 11, 2018
    Assignee: HTC CORPORATION
    Inventors: Ren-Jung Jan, Yi-Hsuan Feng, Hsu-Hong Feng, Ludovic Romain Guegan, Hsin-Ti Chueh
  • Patent number: 10120705
    Abstract: A method for implementing GPU virtualization. The method is applied to a physical host and the physical host includes: a hardware layer including a GPU, a Host running on the hardware layer, and N back-end GPU Domains and M front-end VMs that run on the Host, where there are service channels between the N back-end GPU Domains and the M front-end VMs. The method includes: transferring, by an mth front-end VM, a GPU command to an nth back-end GPU Domain based on the service channels; and processing, by the nth back-end GPU Domain, the GPU command by using a GPU, to obtain corresponding processing result data, where the type of the operating systems running on the nth back-end GPU Domain and the mth front-end VM is same. The invention helps to optimize performance of a GPU virtualization system.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: November 6, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Weidong Han, Yingdong Liu
  • Patent number: 10102603
    Abstract: A graphics processing may include implementing a vertex shader and a pixel shader with a GPU. Vertex parameter values may be compressed with the vertex shader and compressed vertex parameter values may be written to a cache. The pixel shader may access the compressed vertex parameter values that were written to the cache and decompress the compressed vertex parameter values. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: October 16, 2018
    Assignee: Sony Interactive Entertainment Inc.
    Inventors: Mark Evan Cerny, David Simpson, Jason Scanlin
  • Patent number: 10084864
    Abstract: Examples of methods, systems, apparatus, and machine-readable storage media are provided to facilitate access and control of a remote desktop of a remote machine by a web browser at a client device through a transcoding server without installing proprietary plug-ins or protocols on the client device. A transcoding server may translate user input requests from a web browser into input calls compatible with a remote desktop display protocol. The transcoding server may receive remote desktop drawing commands from the remote machine and translate the remote desktop drawing commands into web browser drawing updates compatible with the web browser. A transcoding server may communicate with a web browser via HTTP and communicate with a remote machine via a remote desktop display protocol. A web browser may be an HTML5 browser. A transcoding server may send drawing coordinates to the web browser via an HTTP header and may use long polling.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: September 25, 2018
    Assignee: Wyse Technology L.L.C.
    Inventors: Stevan Kominac, Jeremy Michael Stanley, Curtis Schwebke
  • Patent number: 10049424
    Abstract: The present invention relates to the field of processing a video stream, and more particular to the field of post processing of a video stream using shaders. The processing of the video stream is divided between a video stream processing device and a client device.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: August 14, 2018
    Assignee: AXIS AB
    Inventor: Song Yuan
  • Patent number: 10025367
    Abstract: In one embodiment execution units, graphics cores, or graphics sub-cores can be dynamically scaled across a frame of graphics operations. Available execution units within each graphics core may be scaled using utilization metrics such as the current utilization rate of the execution units and the submission of new draw calls. In one embodiment, one of more of the sub-cores within each graphics core may be enable or disabled based on current or past utilization of the sub-cores based on a set of current graphics operations.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: July 17, 2018
    Assignee: INTEL CORPORATION
    Inventors: Nikos Kaburlasos, Eric Samson
  • Patent number: 10019219
    Abstract: A method for controlling a display device that displays a frame buffer on a plurality of screens is provided. The method includes receiving a multi-screen mode execution command to display a single frame buffer on a plurality of screens, acquiring the frame buffer, splitting the frame buffer into a plurality of frame buffers to correspond to the plurality of screens, setting an offset for each of the plurality of split frame buffers, and displaying each of the plurality of split frame buffers on an associated one of the plurality of screens based on the set offset.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: July 10, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sung-Jin Yoon
  • Patent number: 10004983
    Abstract: A moving image distribution system for performing load balancing is provided. The system determines communication delay amounts between a user terminal and each of a plurality of moving image distribution servers. The system further determines whether a specified content, for distribution to the user terminal, requires a predetermined type of distribution. When the specified content requires the predetermined type of distribution, the system determines whether processing of the content requires a predetermined type of processing. The system specifies one of the plurality of moving image distribution servers for distributing the specified content to the user terminal based on a first determination of whether the specified content requires the predetermined type of distribution and a second determination of whether the content requires the predetermined type of processing.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: June 26, 2018
    Assignee: SQUARE ENIX HOLDINGS CO., LTD.
    Inventor: Tetsuji Iwasaki
  • Patent number: 10002403
    Abstract: Various techniques for remoting graphics are described in the claims, drawings, and text forming a part of the present disclosure.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: June 19, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Nadim Y. Abdo, Asael Dror, Max Alan McMullen, Stuart Raymond Patrick
  • Patent number: 9978343
    Abstract: Performance counters provided in a graphics processor unit (GPU) are used to provide values used to make a determination of GPU activity so that power management can be exercised. In preferred embodiments counter values relating to computation unit idle times, computation unit stall times, DRAM bandwidth and computation unit stall times due to a sampler wait are utilized to determine performance level. If performance is above a minimum level but the GPU is above certain idleness determinations provided by those values, the GPU can have portions powered down to reduce power consumption while not having a noticeable effect on operations. Based on the various counter values, portions of the GPU can be turned off or disabled to reduce power consumption without having a noticeable effect on perceived GPU performance.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: May 22, 2018
    Assignee: Apple Inc.
    Inventors: Ashwini Simha, Bin Lin, Christopher T. Weaver, Frederick B. Fisher, Ramkumar Srinivasan
  • Patent number: 9953395
    Abstract: The tessellation processing rate of a graphics processor may be increased using of local tessellation work redistribution. The redistribution mechanism may avoid the need for large on-die buffers and, as the distribution is local, the performance and power penalty incurred by use of off-chip memory accesses may also avoided in some embodiments.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventor: Peter L. Doyle
  • Patent number: 9916675
    Abstract: In a tile-based graphics processing system, when a tile for a render output is to be generated, the fragment data storage requirements for each fragment to be generated for the tile is determined 51, and a color and/or depth buffer in the tile buffer is allocated for use by the fragments for the tile based on the determination 57. The graphics processing pipeline then, when generating rendered fragment data for the tile, stores the rendered fragment data in the color buffer and/or depth buffer of the tile buffer allocated to the fragments for the tile 58.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: March 13, 2018
    Assignee: Arm Limited
    Inventors: Edward Charles Plowman, Sean Tristram Ellis
  • Patent number: 9898853
    Abstract: A rendering method includes receiving resolution information including an optimal resolution for rendering images constituting a frame, a number of multi-samples, and resolution factors of the respective images, rendering the images at the optimal resolution, and adjusting a resolution of each of the rendered images based on the resolution factors and the number of multi-samples.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: February 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangoak Woo, Minsu Ahn, Changmoo Kim, Seungin Park, Haewoo Park, Soojung Ryu, Hyongeuk Lee
  • Patent number: 9894334
    Abstract: An image processing circuit includes a front stage signal processing circuit that performs processing of input data and outputs the data and a rear stage signal processing circuit that performs processing which is to be performed on the data obtained after processing of the input data performed by the front stage signal processing circuit and outputs the data. The image processing circuit is configured to be switchable to one state of a first state that performs processing of the input data using the front stage signal processing circuit, subsequently performs processing of the data using the rear stage signal processing circuit, and outputs the data, a second state that performs processing of the input data using the front stage signal processing circuit and outputs the data, and a third state that performs processing of the input data using the rear stage signal processing circuit and outputs the data.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: February 13, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Tatsuhiro Hasu, Takekuni Yamamoto
  • Patent number: 9875516
    Abstract: Systems and methods are provided for frequency adjustment of graphics process units (GPUs). A system includes: a command parser configured to parse one or more first commands associated with one or more future GPU operations to obtain command information, a processing component configured to determine an operation time for the future GPU operations based at least in part on the command information, and a frequency control component configured to adjust a GPU frequency based at least in part on the operation time for the future GPU operations.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: January 23, 2018
    Assignee: MARVELL WORLD TRADE LTD.
    Inventors: Juntao Li, Steven Gao
  • Patent number: 9870046
    Abstract: Techniques to control power and processing among a plurality of asymmetric processing elements are disclosed.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: January 16, 2018
    Assignee: Intel Corporation
    Inventors: Herbert Hum, Eric Sprangle, Doug Carmean, Rajesh Kumar
  • Patent number: 9853919
    Abstract: A data processing apparatus includes a shared buffer; an issuing unit that issues a write address for writing incoming data to the shared buffer; a receiving unit that receives a returned read address for the data read from the shared buffer; a monitoring buffer that saves information indicating use status of an address for the shared buffer; and a monitoring unit that monitors write address issuance and returned read address reception, changes the information for the write address, from an unused state to a used state, when the write address is issued, and changes the information for a read address to be returned, from a used state to an unused state when the returned read address is received. The monitoring unit determines the address for the shared buffer is overlapping, when the information for the write address indicates a used state when the write address is issued.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: December 26, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Hiroshi Kurosaki
  • Patent number: 9842376
    Abstract: Techniques are described with respect to preemption in which a graphics processing unit (GPU) may execute a first set of commands in response to receiving a draw call, the draw call defining a plurality of primitives that are to be rendered by the first set of commands, receive a preemption notification during execution of the first set of commands, and preempt the execution of the first set of commands, prior to completing the execution of the first set of commands to render the plurality of primitives of the draw call, for executing a second set of commands.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: December 12, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Anirudh Rajendra Acharya, Gang Zhong, Vineet Goel
  • Patent number: 9792722
    Abstract: A depth processing method and associated graphic processing circuit is provided. The method comprises loading geometry data of a scene and performing a vertex transformation thereof. After the geometry data is segmented in a tile resolution, pre-depth data of the scene are obtained. After the geometry data are segmented in a bin resolution, plural bin tables are generated. Then, the plural bin tables are converted into plural tiles, the plural converted tiles are classified into a first portion of tiles and a second portion of tiles according to depth data of the converted tiles and the pre-depth data of the scene, and the second portion of tiles are discarded. After the first portion of tiles are processed, a color value and a depth value of each pixel of the scene are generated.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: October 17, 2017
    Assignee: MediaTek Inc.
    Inventors: Ming-Hao Liao, Chih-Ching Chen, Hung-Wei Wu
  • Patent number: 9779469
    Abstract: Techniques are described for copying data only from a subset of memory locations allocated to a set of instructions to free memory locations for higher priority instructions to execute. Data from a dynamic portion of one or more general purpose registers (GPRs) allocated to the set of instructions may be copied and stored to another memory unit while data from a static portion of the one or more GPRs allocated to the set of instructions may not be copied and stored to another memory unit.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: October 3, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Lee Howes, Maxim Kazakov
  • Patent number: 9767770
    Abstract: A computer system for processing of data received from a remote device. The computer system includes a master device and at least one slave device. The master device is communicably coupled to the remote device and has a display and a memory. The master device partitions the data into one or more sub data. The at least one slave device is coupled to the master device. The master device delegates processing of the one or more sub data to one or more of the at least one slave device, and the one or more of the at least one slave device correspondingly to the one or more sub data generate processed sub data. The master device stores the processed sub data and outputs the processed sub data to the display.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: September 19, 2017
    Assignee: AMERICAN MEGATRENDS INC.
    Inventors: Chih-Kai Hu, Xuan-Ming Huang
  • Patent number: 9760376
    Abstract: An apparatus may include a processor and storage to store instructions that cause the processor to perform operations including: in response to a determination that a GPU of a node device is available, determine whether a task routine can be compiled to generate a GPU task routine for execution by the GPU to cause performance of multiple instances of a task of the task routine at least partially in parallel without dependencies thereamong; and in response to a determination that the task routine is able to be compiled to generate the GPU task routine: employ a conversion rule to convert the task routine into the GPU task routine; compile the GPU task routine for execution by the GPU; and assign performance of the task with a data set partition to the node device to enable performance of the multiple instances with the data set partition by the GPU.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: September 12, 2017
    Assignee: SAS Institute Inc.
    Inventors: Henry Gabriel Victor Bequet, Huina Chen
  • Patent number: 9741156
    Abstract: A materials trouble shooter is provided for use with 3D models in computer graphics. An error texture is displayed that is distinguishable from textures without errors. If a texture is missing or is applied incorrectly to the 3D model, an error texture is displayed using an error shader instead of a regular shader for the texture for which an error in loading or application has been detected.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: August 22, 2017
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC.
    Inventors: Scott Marison, Jean-Pierre Duplessis, Jacob Meyer, Tito Pagán, Boris S. Jabes
  • Patent number: 9734545
    Abstract: One embodiment of the present invention sets forth a technique for executing a software method within a graphics processing unit (GPU) that minimizes the number of clock cycles during which the graphics engine is idled. The function of the software method is performed by a firmware method that is executed by a processor within the GPU. The firmware method is executed to access and optionally update the state stored in the GPU. Unlike execution of a conventional software method, execution of the firmware method does not require an exchange of information between a CPU and the GPU. Therefore, the CPU is not interrupted and throughput of the CPU is not reduced.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: August 15, 2017
    Assignee: NVIDIA Corporation
    Inventors: Jerome F. Duluk, Jr., John Christopher Cook, Fred Gruner, Gregory Scott Palmer
  • Patent number: 9727944
    Abstract: Techniques are disclosed relating to low-level instruction storage in a graphics unit. In some embodiments, a graphics unit includes execution circuitry, decode circuitry, hazard circuitry, and caching circuitry. In some embodiments the execution circuitry is configured to execute clauses of graphics instructions. In some embodiments, the decode circuitry is configured to receive graphics instructions and a clause identifier for each received graphics instruction and to decode the received graphics instructions. In some embodiments, the hazard circuitry is configured to generate hazard information that specifies dependencies between ones of the decoded graphics instructions in the same clause. In some embodiments, the caching circuitry includes a plurality of entries each configured to store a set of decoded instructions in the same clause and hazard information generated by the decode circuitry for the clause.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: August 8, 2017
    Assignee: Apple Inc.
    Inventors: Andrew M. Havlir, Dzung Q. Vu, Liang Kai Wang
  • Patent number: 9720769
    Abstract: A method of operating a data storage device having a memory includes reading error location data associated with a first region of the memory. The memory includes the first region and a second region. The method also includes generating one or more parameters based on the error location data. The method includes receiving data to be written to the memory and encoding the data to produce a codeword. The method also includes partitioning the codeword based on the one or more parameters to generate a first portion and a second portion. The method further includes performing a write operation to store the first portion at the first region and to store the second portion at the second region.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: August 1, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Abhijeet Manohar, Daniel Edward Tuers, Dana Lee
  • Patent number: 9699426
    Abstract: A method and device for processing a picture comprises estimating a color mapping between a first and a second color-graded version of the picture by estimating a color mapping function that maps the color values of the first color-graded version of the picture onto the color values of the second color-graded version of the picture.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: July 4, 2017
    Assignee: THOMSON LICENSING
    Inventors: Philippe Bordes, Sebastien Lasserre, Pierre Andrivon
  • Patent number: 9696993
    Abstract: A processing device to provide vectorization of conditional loops includes vector physical registers to store a source vector having a first plurality of n data fields, and a destination vector comprising a second plurality of data fields corresponding to the first plurality of data fields, wherein each of the second plurality of data fields corresponds to a mask value in a vector conditions mask. The processing device includes a decode stage to decode a first processor instruction specifying a vector expand operation and a data partition size, and execution units to set elements of the source vector to n count values, obtain a decisions vector, generate the vector conditions mask according to the decisions vector, and copy data from consecutive vector elements in the source vector, into unmasked vector elements of the destination vector, without copying data from the source vector into masked vector elements of the destination vector.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: July 4, 2017
    Assignee: Intel Corporation
    Inventors: Tal Uliel, Elmoustapha Ould-Ahmed-Vall, Bret L. Toll
  • Patent number: 9659340
    Abstract: A graphics processing chip includes multiple graphics pipeline cores and multi-pipeline core logic circuitry to process graphic data streams received from a processor and to drive multiple GPUs on the multiple graphics pipeline cores.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: May 23, 2017
    Assignee: LUCIDLOGIX TECHNOLOGIES LTD
    Inventors: Offir Remez, Yoel Shoshan, Guy Sela
  • Patent number: 9652239
    Abstract: A method decodes instructions based in part on one or more decode-related attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection with a decode of an instruction stored in a page of memory, such that one or more attributes associated with the page in the data structure may be used to control how that instruction is decoded.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: May 16, 2017
    Assignee: International Business Machines Corporation
    Inventors: Adam J. Muff, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs
  • Patent number: 9542189
    Abstract: One embodiment of the present invention includes a technique for processing graphics primitives in a tile-based architecture. The technique includes storing, in a buffer, a first plurality of graphics primitives and a first plurality of state bundles received from a world-space pipeline, and transmitting the first plurality of graphics primitives to a screen-space pipeline for processing while a tiling function is enabled. The technique further includes storing, in the buffer, a second plurality of graphics primitives and a second plurality of state bundles received from the world-space pipeline. The technique further includes determining, based on a first condition, that the tiling function should be disabled and that the second plurality of graphics primitives should be flushed from the buffer, and transmitting the second plurality of graphics primitives to the screen-space pipeline for processing while the tiling function is disabled.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: January 10, 2017
    Assignee: NVIDIA Corporation
    Inventors: Ziyad S. Hakura, Cynthia Ann Edgeworth Allison, Joseph Cavanaugh, Dale L. Kirkland, Emmett M. Kilgariff
  • Patent number: 9535560
    Abstract: Examples of methods, systems, apparatus, and machine-readable storage media are provided to facilitate access and control of a remote desktop of a remote machine by a web browser of a client device through a web server without installing proprietary plug-ins or protocols on the client device. A web server may translate user input requests from a windows web browser into input calls compatible with a remote desktop display protocol. The web server may receive remote desktop drawing commands from the remote machine and translate the remote desktop drawing commands into web browser drawing updates compatible with the windows web browser. A web server may communicate with the windows web browser and a remote machine via HTTP and a remote desktop display protocol, accordingly.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: January 3, 2017
    Assignee: WYSE TECHNOLOGY L.L.C.
    Inventors: Stevan Kominac, Curtis Schwebke
  • Patent number: 9536341
    Abstract: One embodiment of the present invention sets forth a technique for parallel distribution of primitives to multiple rasterizers. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives from the multiple geometry units concurrently to multiple rasterizers at rates of multiple primitives per clock. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: January 3, 2017
    Assignee: NVIDIA Corporation
    Inventors: Johnny S. Rhoades, Emmett M. Kilgariff, Michael C. Shebanow, Ziyad S. Hakura, Dale L. Kirkland, James Daniel Kelly
  • Patent number: 9501276
    Abstract: Instructions and logic provide vectorization of conditional loops. A vector expand instruction has a parameter to specify a source vector, a parameter to specify a conditions mask register, and a destination parameter to specify a destination vector to hold n consecutive vector elements, each of the plurality of n consecutive vector elements having a same variable partition size of m bytes. In response to the processor instruction, data is copied from consecutive vector elements in the source vector, and expanded into unmasked vector elements of the specified destination vector, without copying data into masked vector elements of the destination vector, wherein n varies responsive to the processor instruction executed. The source vector may be a register and the destination vector may be in memory. Some embodiments store counts of the condition decisions. Alternative embodiments may store other data, for example such as target addresses, or table offsets, or indicators of processing directives, etc.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: November 22, 2016
    Assignee: Intel Corporation
    Inventors: Tal Uliel, Elmoustapha Ould-Ahmed-Vall, Bret L. Toll
  • Patent number: 9501847
    Abstract: One embodiment of the present invention sets forth a technique for computing line stipple using a parallel rasterizer. Stipple phases are computed in parallel for individual line segments of a line strip during the viewport scale, cull, and clipping operations. The line segments are distributed to multiple parallel rasterizers. Each line segment may be sent to only one of the parallel rasterizers. Update phase messages that include an accumulated stipple phase for a batch of line segments are broadcast to all of the multiple parallel rasterizers. The update phase messages are used by the multiple parallel rasterizers to reconstruct the stipple phases for each line segment of a line strip in order to correctly render stippled line strips and produce a continuous stippled line.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: November 22, 2016
    Assignee: NVIDIA Corporation
    Inventors: Timothy John Purcell, Ziyad S. Hakura