Pipeline Processors Patents (Class 345/506)
  • Patent number: 11366752
    Abstract: A memory module system with a global shared context. A memory module system can include a plurality of memory modules and at least one processor, which can implement the global shared context. The memory modules of the system can provide the global shared context at least in part by providing an address space shared between the modules and applications running on the modules. The address space sharing can be achieved by having logical addresses global to the modules, and each logical address can be associated with a certain physical address of a specific module.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: June 21, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Dmitri Yudanov
  • Patent number: 11341601
    Abstract: A cache system in a graphics processing system stores graphics data items for use in rendering primitives. It is determined whether graphics data items relating to primitives to be rendered are present in the cache, and if not then computation instances for generating the graphics data items are created. Computation instances are allocated to tasks using a task assembly unit which stores task entries for respective tasks. The task entries indicate which computation instances have been allocated to the respective tasks. The task entries are associated with characteristics of computation instances which can be allocated to the respective tasks. A computation instance to be executed is allocated to a task based on the characteristics of the computation instance. SIMD processing logic executes computation instances of a task outputted from the task assembly unit to thereby determine graphics data items, which can be used to render the primitives.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: May 24, 2022
    Assignee: Imagination Technologies Limited
    Inventors: Andrea Sansottera, Xile Yang, John Howson, Jonathan Redshaw
  • Patent number: 11288765
    Abstract: Methods for graphics processing are provided. One example method includes executing a plurality of kernels using a plurality of graphics processing units (GPUs), wherein responsibility for executing a corresponding kernel is divided into one or more portions each of which being assigned to a corresponding GPU. The method includes generating a plurality of dependency data at a first kernel as each of a first plurality of portions of the first kernel completes processing. The method includes checking dependency data from one or more portions of the first kernel prior to execution of a portion of a second kernel. The method includes delaying execution of the portion of the second kernel as long as the corresponding dependency data of the first kernel has not been met.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: March 29, 2022
    Assignee: Sony Interactive Entertainment LLC
    Inventors: Florian A. Strauss, Mark Evan Cerny
  • Patent number: 11283864
    Abstract: A fail-safe system for a cluster application is disclosed. The system includes a first subsystem comprising a graphic processing unit (GPU) that executes a high-level operating system renders a first set of parameter data, and a second subsystem that executes a real-time operating system and renders a second set of parameter data. The system also includes a controller area network connected to a parameter data source input and to the first subsystem and the second subsystem. The system further includes a quality of service (QoS) switch executing a QoS monitor module that decides to display the first set of parameter data being rendered by the first subsystem or the second set of parameter data being rendered by the second subsystem depending on an availability and load of the first subsystem as determined by a lag and a stability threshold. The system further includes a display connected to the QoS switch.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: March 22, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Nikhil Nandkishor Devshatwar, Shravan Karthik, Santhana Bharathi N, Subhajit Paul
  • Patent number: 11281495
    Abstract: A system and method for providing security of sensitive information within chips using SIMD micro-architecture are described. A command processor within a parallel data processing unit, such as a graphics processing unit (GPU), schedules commands across multiple compute units based on state information. When the command processor determines a rescheduling condition is satisfied, it causes the overwriting of at least a portion of data stored in each of the one or more local memories used by the multiple compute units. The command processor also stores in the secure memory a copy of state information associated with a given group of commands and later checks it to ensure corruption by a malicious or careless program is prevented.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: March 22, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Rex Eldon McCrary
  • Patent number: 11270675
    Abstract: Disclosed are an image data reading method and apparatus, an electronic device, and a readable storage medium, relating to the technical field of LED image display. The image data reading method includes: storing image data in each row of image blocks into a number of v storage blocks, where each of the v storage blocks stores a number of h rows, each row of data including image data stored at a same position of each group in a same row of every image block; and sequentially outputting from each of the v storage blocks by: sequentially reading each row of the image data in a vertical order, and simultaneously outputting the image data stored at the same position.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: March 8, 2022
    Assignee: ZHEJIANG UNIVIEW TECHNOLOGIES CO., LTD.
    Inventors: Deqian Mo, Hailong Yang, Yuguang Yuan, Wenhui Qin
  • Patent number: 11250627
    Abstract: An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: February 15, 2022
    Assignee: Intel Corporation
    Inventors: Subramaniam Maiyuran, Saurabh Sharma, Jorge F. Garcia Pabon, Raghavendra Kamath Miyar, Sudheendra Srivathsa, Justin Decell, Aditya Navale
  • Patent number: 11227430
    Abstract: According to one general aspect, an apparatus may include a graphical processing engine comprising a pipeline having a plurality of substantially sequential circuit stages, the pipeline comprising a front-end output logic circuit configured to substantially separate position information into a position information pipeline portion, and non-position information in a non-position information pipeline portion. Wherein the pipeline is configured to perform a multi-stage culling of data.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: January 18, 2022
    Inventors: Derek Lentz, Chris Goodman
  • Patent number: 11217007
    Abstract: Methods and primitive block generators for generating primitive blocks in a graphics processing system. The methods comprise: receiving transformed position data for a current primitive, the transformed position data indicating a position of the current primitive in rendering space; determining a distance between the position of the current primitive and a position of a current primitive block based on the transformed position data for the current primitive; determining whether to add the current primitive to the current primitive block based on the distance and a fullness of the current primitive block; in response to determining that the current primitive is to be added to the current primitive block, adding the current primitive to the current primitive block; and in response to determining that the current primitive is not to be added to the current primitive block, flushing the current primitive block and adding the current primitive to a new current primitive block.
    Type: Grant
    Filed: December 21, 2019
    Date of Patent: January 4, 2022
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, Robert Brigg, John W. Howson
  • Patent number: 11200063
    Abstract: Methods, systems and apparatuses may provide for technology that triggers an idle state in a first command streamer in response to a request to reset a second command streamer that shares graphics hardware with the first command streamer. The technology may also determine an event type associated with the request and conduct the request based on the event type.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: December 14, 2021
    Assignee: Intel Corporation
    Inventors: Harsh Chheda, Nishanth Reddy Pendluru, Joseph Koston, Eric R. Crawford
  • Patent number: 11194377
    Abstract: An information handling system includes a processor, a graphics processing unit (GPU), and a baseboard management controller (BMC). The BMC includes a power ratio table with a plurality of entries, each correlating a workload with a power ratio of a power level of the processor when the particular workload is instantiated on the information handing system to a power level of the GPU when the particular workload is instantiated on the information handling system. The BMC determines that the power ratio table includes an entry associated with a workload instantiated on the information handling system, determines that a total power level of the information handling system is greater than a power level threshold, and throttles a power level of the processor and a power level of the GPU based upon a power ratio of the entry in response to determining that the total power level is greater than the power level threshold.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: December 7, 2021
    Assignee: Dell Products L.P.
    Inventors: Balaji Bapu Gururaja Rao, Elie Antoun Jreij, John Erven Jenne
  • Patent number: 11170564
    Abstract: An apparatus and method are described for performing an early depth test on graphics data. For example, one embodiment of a graphics processing apparatus comprises: early depth test circuitry to perform an early depth test on blocks of pixels to determine whether all pixels in the block of pixels can be resolved by the early depth test; a plurality of execution circuits to execute pixel shading operations on the blocks of pixels; and a scheduler circuit to schedule the blocks of pixels for the pixel shading operations, the scheduler circuit to prioritize the blocks of pixels in accordance with the determination as to whether all pixels in the block of pixels can be resolved by the early depth test.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: November 9, 2021
    Assignee: INTEL CORPORATION
    Inventors: Brent E. Insko, Prasoonkumar Surti
  • Patent number: 11170460
    Abstract: Systems and methods may provide for receiving a pixel shader and sending the pixel shader to shader bypass hardware if the pixel shader and a render target associated with the pixel shader satisfy a simplicity condition. In one example, the shader bypass hardware is dedicated to pixel shaders and associated render targets that satisfy the simplicity condition.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: November 9, 2021
    Assignee: Intel Corporation
    Inventors: Prasoonkumar Surti, Larry Seiler, Adam Z. Leibel
  • Patent number: 11157065
    Abstract: A method is provided for electric low-energy operation of motor vehicle functions during the operation of a motor vehicle equipped with an information display. The method deactivates the information display of the motor vehicle; degrades a functionality of at least one vehicle component that uses the information display to visually represent specific information of the vehicle component; and deactivates a graphics processing unit of the motor vehicle as an energy-saving measure. The graphics processing unit is configured to prepare the specific information of the vehicle component such that this information can be visually represented on the information display. The functionality of the vehicle component is degraded such that the vehicle component continues to determine its associated specific information in accordance with the function and keep the information ready in a prepared manner for graphical processing.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: October 26, 2021
    Assignees: Bayerische Motoren Werke Aktiengesellschaft, Siemens Industry Software Inc.
    Inventors: Daniel Franze, Hans-Peter Reichert, Georg Spoerlein, Reiner Striebel
  • Patent number: 11132835
    Abstract: To suspend processing of a sequence of primitives being processed in a graphics processing pipeline the processing of primitives in a second section of the graphics processing pipeline in which the primitives are processed into graphics fragments is continued to generate respective sets of fragments. For each respective set of graphics fragments generated from this continued processing the set of fragments is passed from the second section of the graphics processing pipeline to a rendering circuit and the processing in respect of the respective fragments is then suspended. A set of suspend operation state information for the set of fragments indicating that the processing was suspended is then written out.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: September 28, 2021
    Assignee: Arm Limited
    Inventor: Olof Henrik Uhrenholt
  • Patent number: 11127109
    Abstract: A method for avoiding lockup in a graphics pipeline may include accumulating position information in an accumulating stage of the pipeline, passing position information from a first preceding stage of the pipeline to the accumulating stage, determining a condition in the first preceding stage, and draining accumulated position information from the accumulating stage in response to the condition in the first preceding stage. The method may further include passing position information from the first preceding stage to a second preceding stage of the pipeline, passing position information from the second preceding stage to the accumulating stage, determining a condition in the second preceding stage, and draining accumulated position information from the accumulating stage in response to the condition in the first preceding stage and the condition in the second preceding stage.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: September 21, 2021
    Inventors: Derek J. Lentz, Chiachi Chao
  • Patent number: 11127188
    Abstract: To suspend the processing of primitives in a graphics processing pipeline the graphics processor selects a suspend operation “boundary” primitive having a position within a sequence of graphics primitives being processed such that it can be guaranteed that all primitives in the sequence of primitives that are behind the position of the selected boundary primitive within the sequence of primitives are in their initial specified order, whereas any primitives in the sequence of primitives that may be out of order are ahead of the selected boundary primitive. The processing of primitives behind the boundary primitive is then stopped, whereas processing for primitives ahead of boundary primitive is continued.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: September 21, 2021
    Assignee: Arm Limited
    Inventor: Olof Henrik Uhrenholt
  • Patent number: 11107176
    Abstract: A tile-based system for processing graphics data. The tile based system includes a first screen-space pipeline, a cache unit, and a first tiling unit. The first tiling unit is configured to transmit a first set of primitives that overlap a first cache tile and a first prefetch command to the first screen-space pipeline for processing, and transmit a second set of primitives that overlap a second cache tile to the first screen-space pipeline for processing. The first prefetch command is configured to cause the cache unit to fetch data associated with the second cache tile from an external memory unit. The first tiling unit may also be configured to transmit a first flush command to the screen-space pipeline for processing with the first set of primitives. The first flush command is configured to cause the cache unit to flush data associated with the first cache tile.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: August 31, 2021
    Assignee: NVIDIA Corporation
    Inventors: Ziyad S. Hakura, Rouslan Dimitrov
  • Patent number: 11093579
    Abstract: Disclosed embodiments relate to mixed-precision vector multiply-accumulate (MPVMAC) In one example, a processor includes fetch circuitry to fetch a compress instruction having fields to specify locations of a source vector having N single-precision formatted elements, and a compressed vector having N neural half-precision (NHP) formatted elements, decode circuitry to decode the fetched compress instruction, execution circuitry to respond to the decoded compress instruction by: converting each element of the source vector into the NHP format and writing each converted element to a corresponding compressed vector element, wherein the processor is further to fetch, decode, and execute a MPVMAC instruction to multiply corresponding NHP-formatted elements using a 16-bit multiplier, and accumulate each of the products with previous contents of a corresponding destination using a 32-bit accumulator.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: August 17, 2021
    Assignee: Intel Corporation
    Inventors: Sidharth N. Kashyap, Angus Lepper, Peter Boyle
  • Patent number: 11068401
    Abstract: Methods and apparatus to improve shared memory efficiency are described. In an embodiment, a first version of a code to access one or more registers as shared local memory is compiled. A second version of the same code is also compiled to access a cache as the shared local memory. The first version of the code is executed in response to comparison of a work group size of the code with a threshold value. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 20, 2021
    Assignee: INTEL CORPORATION
    Inventors: Jianghong Du, Yong Jiang, Lei Shen, Yuanyuan Li, Ruijia Li, Lingyi Kong
  • Patent number: 11017494
    Abstract: An embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass. The resolver may be configured to exclude a sample location not covered by the mask in the resolve pass. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventors: Hugues Labbe, Tomer Bar-On, Kai Xiao, Ankur N. Shah, John G. Gierach
  • Patent number: 11010859
    Abstract: The present disclosure relates to a display resource scheduling method and device for an embedded system, a computer readable storage medium and an electronic device. The embodiment of the present disclosure provides a display resource scheduling method for an embedded system, at least a host operating system and a first guest operating system running on the embedded system, and the embedded system including a graphics processing unit and a display-specific hardware accelerator. The method includes: receiving a graphic to be displayed of the first guest operating system; preferentially scheduling the display-specific hardware accelerator to perform a display operation on the graphic to be displayed; if resources of the display-specific hardware accelerator are exhausted, scheduling the graphics processing unit to perform a display operation on the graphic to be displayed.
    Type: Grant
    Filed: September 21, 2019
    Date of Patent: May 18, 2021
    Assignee: CLOUDMINDS (SHENZHEN) ROBOTICS SYSTEMS CO., LTD.
    Inventor: Yangang Li
  • Patent number: 11010863
    Abstract: A computer-implemented technique for accessing textures by a graphics processing unit (GPU), includes determining a frequency with which a first texture is expected to be accessed by an application executing on a GPU, determining a frequency with which a second texture is expected to be accessed by an application executing on the GPU, determining to load memory address information associated with the first texture into a GPU register when the frequency is greater than or equal to a threshold frequency value, determining to load memory address information associated with the second texture into a buffer memory when the frequency is less than the threshold frequency value, receiving a draw call utilizing the texture, rendering the draw call using the first texture by accessing the memory address information in the GPU register, and the second texture by accessing the memory address information in the buffer memory.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: May 18, 2021
    Assignee: Apple Inc.
    Inventors: Michael Imbrogno, Sivert Berg, Nicholas H. Smith
  • Patent number: 11004255
    Abstract: Examples are disclosed that relate to culling of polygons for efficient rendering of a high-density polygon mesh using one or more compute shaders. Examples include monoscopic and stereoscopic rendering, foveated and non-foveated rendering, and selectively utilizing one or more computer shaders to rasterize very small triangles instead of using a regular rendering pipeline for increased performance.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: May 11, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Adam Andrzej Cichocki, Marc Schirski, Dag Birger Frommhold
  • Patent number: 11004258
    Abstract: Improvements to graphics processing pipelines are disclosed. More specifically, the vertex shader stage, which performs vertex transformations, and the hull or geometry shader stages, are combined. If tessellation is disabled and geometry shading is enabled, then the graphics processing pipeline includes a combined vertex and graphics shader stage. If tessellation is enabled, then the graphics processing pipeline includes a combined vertex and hull shader stage. If tessellation and geometry shading are both disabled, then the graphics processing pipeline does not use a combined shader stage. The combined shader stages improve efficiency by reducing the number of executing instances of shader programs and associated resources reserved.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 11, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mangesh P. Nijasure, Randy W. Ramsey, Todd Martin
  • Patent number: 10997756
    Abstract: When processing a primitive when generating a render output in a graphics processor, the vertices for the primitive are loaded by a vertex loader, but before a primitive setup stage generates per-primitive data for the primitive using the loaded vertices for the primitive, an early culling test is performed for the primitive using data of the loaded vertices for the primitive. When the primitive passes the early culling test, the primitive is sent onwards to the primitive setup stage and to a rasteriser for rasterising the primitive, but when the primitive fails the early culling test, it is discarded from further processing at the early culling test.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: May 4, 2021
    Assignee: Arm Limited
    Inventor: Olof Henrik Uhrenholt
  • Patent number: 10985985
    Abstract: A cloud service system includes an overlay cloud managing unit to totally control an overlay cloud which is the cloud for a developer, a cloud provider to provide an infrastructure in which the overlay cloud is configured, and a direct connection point to physically directly connect the overlay cloud managing unit with the cloud provider.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: April 20, 2021
    Assignee: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jong Won Kim, Jung su Han
  • Patent number: 10981059
    Abstract: A method for executing a game by a computing system that uses a central processing unit (CPU) and graphics processing unit (GPU) for generating video frames. A draw call is generated for a video frame by the CPU. At bind time, i.e. writing of the GPU commands by the CPU using a GPU API, asset aware data (AAD) is written to the command buffer, and loading of one or more level of detail (LOD) data from an asset store to system memory is requested. The GPU executes the draw call for the frame using LOD data written to the system memory, the GPU using at least a minimum of LOD data based on the AAD. Additionally, the GPU uses information regarding the LOD load state when executing the draw call, in order to avoid access to LODs not yet loaded.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: April 20, 2021
    Assignee: Sony Interactive Entertainment LLC
    Inventor: Mark E. Cerny
  • Patent number: 10956126
    Abstract: Execution of a machine instruction in a central processing unit. A perform floating-point operation instruction and a test bit are obtained. If the test bit has a first value, a specified floating-point operation function is performed, and a condition code is set to a value determined by the specified function. If the test bit has a second value, a check is made to determine if the specified function is valid and installed on the machine. If the specified function is valid and installed on the machine, the condition code is set to one code value, and if the specified function is either not valid or not installed on the machine, the condition code is set to a second code value.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michel H. T. Hack, Ronald M. Smith, Sr.
  • Patent number: 10937233
    Abstract: Disclosed herein is a bounding box that can be generated for a set of one or more primitive(s) and then passed to a rasteriser circuit for use thereby when generating the graphics fragments to be processed. The bounding box generation integrates a scissor test and allows primitives for which an initial bounding box has zero intersection with a specified scissor box to be discarded, whereas for primitives whose initial bounding box does intersect the scissor box, a new bounding box can be generated for output based on the area of intersection.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: March 2, 2021
    Assignee: Arm Limited
    Inventors: Ole Magnus Ruud, Frode Heggelund
  • Patent number: 10937198
    Abstract: A decoder is configured to decode a plurality of texels from a received block of texture data encoded according to the Adaptive Scalable Texture Compression (ASTC) format, and includes a parameter decode unit configured to decode configuration data for the received block of texture data, a colour decode unit configured to decode colour endpoint data for the plurality of texels of the received block in dependence on the configuration data, a weight decode unit configured to decode interpolation weight data for each of the plurality of texels of the received block in dependence on the configuration data, and at least one interpolator unit configured to calculate a colour value for each of the plurality of texels of the received block using the interpolation weight data for that texel and a pair of colour endpoints from the colour endpoint data.
    Type: Grant
    Filed: April 28, 2018
    Date of Patent: March 2, 2021
    Assignee: Imagination Technologies Limited
    Inventors: Kenneth Rovers, Yoong Chert Foo
  • Patent number: 10873754
    Abstract: Methods and devices are described for a parallel multi-processor encoder system for encoding video data, wherein the video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system may divide the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks may be transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: December 22, 2020
    Assignee: Coherent Logix, Incorporated
    Inventors: Michael W. Bruns, Martin A. Hunt, Manjunath H. Siddaiah, John C. Sievers
  • Patent number: 10861231
    Abstract: A graphics system has a rendering space divided into a plurality of rectangular areas, each being sub-divided into a plurality of smaller rectangular areas of a plurality of pixels. Data is received representing a tiled set of polygons to be rendered in a selected one of the rectangular areas. For each polygon, a determination is made whether that polygon is located at least partially inside a selected one of the smaller rectangular areas in the selected rectangular area. If so, which pixels of the plurality of pixels in the selected smaller rectangular area are inside the polygon are identified. Or, if that polygon is not located at least partially inside the selected smaller rectangular area, no further processing of the polygon is performed at one or more of the plurality of pixels in the smaller rectangular area.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: December 8, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Piers Barber, Simon Fenney
  • Patent number: 10839597
    Abstract: Apparatus and method for a multi-frequency vertex shader. For example, one embodiment of a graphics processing apparatus comprises a plurality of vertex caches to store vertex data associated with graphics primitives; and graphics execution circuitry to execute vertex shaders operable at different processing rates for different sets of the vertex data, each of the different sets of vertex data to having a different type of identifier associated therewith to identify the vertex data.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: November 17, 2020
    Assignee: Intel Corporation
    Inventors: John Gierach, Daniel Walsh, John Feit, Devan Burke
  • Patent number: 10825207
    Abstract: A fragment shader program to be executed by a fragment shader of a graphics processor can include a graphics texturing instruction that when executed by the fragment shader will cause the fragment shader to send a request to the texture mapper to perform a graphics texture mapping operation in which the texture mapper will perform plural lookups from the same texture in parallel. In response to the request from the fragment shader, the texture mapper of the graphics processor performs plural lookups from the same texture in parallel, and generates a texture mapping operation result using the results of the plural lookups from the same texture for returning to the fragment shader.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: November 3, 2020
    Assignee: Arm Limited
    Inventor: Edvard Fielding
  • Patent number: 10818067
    Abstract: A method and system for dynamically transferring graphical image processing operations from a graphical processing unit (GPU) to a digital signal processor (DSP). The method includes estimating the number of operations needed for the processing a set of image data; determining the operational limits of a GPU and compare with estimated number of operations and if the operational limits are exceeded; transfer the processing operations to the DSP from the GPU. The transfer can include transferring a portion of executable code for performing the processing operations, and generating a replacement code for the GPU. The DSP can then process a portion of the image data before sending it to the GPU for further processing.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: October 27, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mihir Mody, Hemant Hariyani, Anand Balagopalakrishnan, Jason Jones, Ajay Jayaraj, Manoj Koul
  • Patent number: 10817973
    Abstract: A cache system in a graphics processing system stores graphics data items for use in rendering primitives. It is determined whether graphics data items relating to primitives to be rendered are present in the cache, and if not then computation instances for generating the graphics data items are created. Computation instances are allocated to tasks using a task assembly unit which stores task entries for respective tasks. The task entries indicate which computation instances have been allocated to the respective tasks. The task entries are associated with characteristics of computation instances which can be allocated to the respective tasks. A computation instance to be executed is allocated to a task based on the characteristics of the computation instance. SIMD processing logic executes computation instances of a task outputted from the task assembly unit to thereby determine graphics data items, which can be used to render the primitives.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: October 27, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Andrea Sansottera, Xile Yang, John Howson, Jonathan Redshaw
  • Patent number: 10799797
    Abstract: Methods, systems, and apparatuses are described herein for providing an interactive application, such as a video game, with a hierarchy of avatar categories, each having a maximum and minimum progression value. Each avatar category may be associated with one or more avatars, items, and/or other portions of the interactive application. A beginner avatar category may be associated with a minimum progression value greater than an absolute minimum progression value and a maximum progression value lesser than an absolute maximum progression value. A second avatar category may be associated with a minimum and maximum progression value that are, respectively, lower and greater than that of the beginner avatar category. The interactive application may allow a user to select from the beginner avatar category and the second avatar category. An avatar category may be associated with game rewards.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: October 13, 2020
    Assignee: Wargaming.net Limited
    Inventor: Sergey Burkatovskiy
  • Patent number: 10795713
    Abstract: The disclosure provides an approach for modifying a kernel by adding conditional halting points. The disclosure also provides an approach for modifying a kernel by implementing a virtual shared memory between an application running on a CPU and a workload running on a compute accelerator. The disclosure provides an approach for setting up the kernel and its working set on a compute accelerator, executing the workload, suspending the workload, and then resuming the workload at a later time, optionally on a different host computer.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: October 6, 2020
    Assignee: VMware, Inc.
    Inventor: Matthew D. McClure
  • Patent number: 10796399
    Abstract: Systems, apparatuses, and methods for implementing pixel wait synchronization techniques are disclosed. A system includes a host processor and a graphics processor which includes at least one graphics pipeline. During execution of a graphics application, the host processor determines that a second draw call is dependent on a first draw call. The host processor issues a wait sync event prior to issuing the second draw call to the graphics pipeline responsive to determining that the first draw call is still in-flight in the graphics pipeline. After the second draw call is issued to the graphics pipeline, the second draw call is processed by one or more stages of the graphics pipeline while the first draw call is still in-flight. The graphics pipeline stalls the second draw call at a given intermediate stage until a corresponding event counter equals a value specified by the wait sync event.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: October 6, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Pazhani Pillai
  • Patent number: 10776895
    Abstract: Systems, methods, and computer readable media to improve the operation of graphics systems are described. In general, techniques are disclosed for determining the computational need of GPU-centric elements executing from within pages of another application, selecting one or more GPU's appropriate to the need, and transitioning the system to the selected GPUs.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: September 15, 2020
    Assignee: Apple Inc.
    Inventors: Dean Jackson, Jonathan J. Lee, Christopher C. Niederauer, Gavin Barraclough
  • Patent number: 10754659
    Abstract: According to an embodiment of the present invention, a system filters a collection of application programming interfaces based on input data representing information of a document to be processed, and generates a pipeline of filtered application programming interfaces. Each filtered application programming interface is sequentially executed within the pipeline. The document may be processed through the pipeline and visualizations based on the processing of the document may be generated, allowing the pipeline to be refined to produce desired output data selected within the visualizations. Embodiments of the present invention further include a method and computer program product for generating a pipeline of filtered application programming interfaces in substantially the same manner described above.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: August 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Scott R. Carrier, Jennifer L. La Rocca, Mario J. Lorenzo, Mark G. Megerian
  • Patent number: 10713748
    Abstract: Display pipeline may manage allocation of total memory bandwidth to memory access requester blocks (e.g., display pipeline as a whole and/or a block in the display pipeline) by dynamically allocating the total memory bandwidth based at least in part on a calculated bandwidth floor to reduce the communication inefficiency (e.g., underruns), excessive power consumption, and image quality degradation of the display pipeline. Image fetch parameters, electronic display parameters, display pipeline parameters, and memory access requester block parameters may be used to determine the appropriate bandwidth floor for each memory access requester of the display pipeline. Additional memory bandwidth may be allocated to memory access requesters of the display pipeline when available bandwidth remains to further reduce likelihood of subsequent communication inefficiencies in the display pipeline.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: July 14, 2020
    Assignee: Apple Inc.
    Inventors: Peter F. Holland, Mahesh B. Chappalli
  • Patent number: 10713756
    Abstract: One aspect of the current disclosure provides a method of upscaling an image. The method includes: rendering an image, wherein the rendering includes generating color samples of the image at a first resolution and depth samples of the image at a second resolution, which is higher than the first resolution; and upscaling the image to an upscaled image at a third resolution, which is higher than the first resolution, using the color samples and the depth samples.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: July 14, 2020
    Assignee: Nvidia Corporation
    Inventors: Rouslan Dimitrov, Lei Yang, Chris Amsinck, Walter Donovan, Eric Lum, Rui Bastos
  • Patent number: 10706102
    Abstract: Disclosed aspects relate to operation efficiency management in a shared pool of configurable computing resources. A first set of processing operations of a first application may be detected. A second set of processing operations of a second application may be detected. The first set of processing operations of the first application may be compared with the second set of processing operations of the second application. A substantial match of the first and second processing operations of the first and second applications may be determined. A single set of processing operations for both the first and second applications may be established.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: July 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Eric L. Barsness, Daniel E. Beuch, Michael J. Branson, John M. Santosuosso
  • Patent number: 10699475
    Abstract: Multi-pass apparatus and method for ray tracing shading.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Joshua Barczak, Kai Xiao, Michael Apodaca, Thomas Raoux, Carson Brownlee, Gabor Liktor
  • Patent number: 10679317
    Abstract: Examples described herein generally relate to intercepting, from a graphics processing unit (GPU) or a graphics driver, a buffer that specifies one or more shader records of a shader table to use in generating the image using raytracing, determining, based at least in part on an identifier of the one or more shader records, a layout of the one or more shader records, interpreting, based at least in part on the layout, additional data in the buffer to determine one or more parameters corresponding to the one or more shader records, and displaying, via an application, an indication of the one or more parameters on an interface.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: June 9, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Austin Neil Kinross, Amar Patel
  • Patent number: 10678548
    Abstract: Techniques are disclosed relating to controlling an operand cache in a pipelined fashion. An operand cache may cache operands fetched from the register file or generated by previous instructions to improve performance and/or reduce power consumption. In some embodiments, instructions are pipelined and separate tag information is maintained to indicate allocation of an operand cache entry and ownership of the operand cache entry. In some embodiments, this may allow an operand to remain in the operand cache (and potentially be retrieved or modified) during an interval between allocation of the entry for another operand and ownership of the entry by the other operand. This may improve operand cache efficiency by allowing the entry to be used while to retrieving the other operand from the register file, for example.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: June 9, 2020
    Assignee: Apple Inc.
    Inventors: Robert D. Kenney, Terence M. Potter, Andrew M. Havlir, Sivayya V. Ayinala
  • Patent number: 10672182
    Abstract: Methods and devices for rendering visible primitives in a scene of an application may include loading a primitive visibility buffer that includes a plurality of primitives representing at least one instance in a scene of the application. The primitive visibility buffer may include for each primitive of the plurality of primitives a visibility bit that describes a visibility state as visible or not visible for each of the plurality primitives. The methods and devices may include determining whether each of the plurality of primitives are visible in the scene based on the visibility bit, rendering a primitive when the visibility bit for the primitive indicates that the primitive is visible, and skipping the rendering of the primitive when the visibility bit indicates that the primitive is not visible. The methods and devices may also include combing pre-computed visibility states with runtime visibility testing when rendering the visibility bits.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: June 2, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: John David White, Martin Jon Irwin Fuller
  • Patent number: 10664942
    Abstract: A graphics processing unit (GPU) includes a plurality of programmable processing cores configured to process graphics primitives and corresponding data and a plurality of fixed-function hardware units. The plurality of processing cores and the plurality of fixed-function hardware units are configured to implement a configurable number of virtual pipelines to concurrently process different command flows. Each virtual pipeline includes a configurable number of fragments and an operational state of each virtual pipeline is specified by a different context. The configurable number of virtual pipelines can be modified from a first number to a second number that is different than the first number. An emulation of a fixed-function hardware unit can be instantiated on one or more of the graphics processing cores in response to detection of a bottleneck in a fixed-function hardware unit. One or more of the virtual pipelines can then be reconfigured to utilize the emulation instead of the fixed-function hardware unit.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: May 26, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Timour T. Paltashev, Michael Mantor, Rex Eldon McCrary