Abstract: A three-dimensional computer graphics rendering system allows a tile-based rendering system to operate with a reduced amount of storage required for tiled screen space geometry by using an untransformed display list to represent the screen's geometry.

Abstract: An input output connector for a graphics processing unit having a graphics pipeline including fixed function units and programmable function units is disclosed. Additionally, a graphics processing unit and a method of operating a graphics pipeline are disclosed. In one embodiment, the input output connector includes: (1) a request arbiter configured to connect to each of the programmable function units, receive fixed function requests therefrom and arbitrate the requests and (2) fixed unit converters, wherein each of the fixed unit converters is dedicated to a single one of the fixed function units and is configured to convert the requests directed to the single one to an input format for the single one.

Abstract: A pipeline system includes input buffers, a relay for controlling withdrawal of data stored in the input buffers, and functional blocks for performing one or more processing operations. A method of operating a pipeline system includes withdrawing data from one of input buffers and performing different one or more processing operations.

Abstract: Data may be streamed out of a graphics pipeline during run time without preprogramming the stream out. A command stream may be captured, draw commands monitored, and shader output definitions may be parsed to determine how to stream out shader data, for example for debugging.

Abstract: An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache to store a multiplicity of processed vertices of the mesh. The apparatus may further include a processor circuit, and a vertex manager for execution on the processor circuit to read a reference bitstream comprising a multiplicity of bitstream entries, each bitstream entry corresponding to an index entry of the index stream, and to remove a processed vertex from the vertex cache when a value of the reference bitstream entry corresponding to the processed vertex is equal to a defined value.

Abstract: A system on chip (SoC) including a configurable image processing pipeline is provided. The SoC includes a bus; a first image processing module configured to be connected to the bus and to process image data; a first image processing stage configured to transmit either first image data or second image data received from the bus to at least one of the bus and the first image processing module through a first bypass path in response to first control signals; and a second image processing stage configured to transmit either third image data received from the first image processing module or fourth image data received from the bus to the bus through one of a second bypass path and a second scaler path in response to second control signals.

Abstract: A knight's order processing method for block processing pipelines in which the next block input to the pipeline is taken from the row below and one or more columns to the left in the frame. The knight's order method may provide spacing between adjacent blocks in the pipeline to facilitate feedback of data from a downstream stage to an upstream stage. The rows of blocks in the input frame may be divided into sets of rows that constrain the knight's order method to maintain locality of neighbor block data. Invalid blocks may be input to the pipeline at the left of the first set of rows and at the right of the last set of rows, and the sets of rows may be treated as if they are horizontally arranged rather than vertically arranged, to maintain continuity of the knight's order algorithm.

Abstract: Methods and apparatus relating to a current change mitigation policy for limiting voltage droop in graphics logic are described. In an embodiment, logic inserts one or more bubbles in one or more Execution Unit (EU) logic pipelines or one or more sampler logic pipelines of a processor. The bubbles at least temporarily reduce execution of operations in one or more subsystems of the processor based at least partially on a comparison of a first value and one or more clamping threshold values. The first value is determined based at least partially on a summation of products of one or more event counts and dynamic capacitance weights for one or more subsystems of the processor. Other embodiments are also disclosed and claimed.

Abstract: A block processing pipeline in which blocks are input to and processed according to row groups so that adjacent blocks on a row are not concurrently at adjacent stages of the pipeline. A stage of the pipeline may process a current block according to neighbor pixels from one or more neighbor blocks. Since adjacent blocks are not concurrently at adjacent stages, the left neighbor of the current block is at least two stages downstream from the stage. Thus, processed pixels from the left neighbor can be passed back to the stage for use in processing the current block without the need to wait for the left neighbor to complete processing at a next stage of the pipeline. In addition, the neighbor blocks may include blocks from the row above the current block. Information from these neighbor blocks may be passed to the stage from an upstream stage of the pipeline.

Abstract: Block processing pipeline methods and apparatus in which pixel data from a reference frame is prefetched into a search window memory. The search window may include two or more overlapping regions of pixels from the reference frame corresponding to blocks from the rows in the input frame that are currently being processed in the pipeline. Thus, the pipeline may process blocks from multiple rows of an input frame using one set of pixel data from a reference frame that is stored in a shared search window memory. The search window may be advanced by one column of blocks by initiating a prefetch for a next column of reference data from a memory. The pipeline may also include a reference data cache that may be used to cache a portion of a reference frame and from which at least a portion of a prefetch for the search window may be satisfied.

Abstract: Methods and apparatus for caching neighbor data in a block processing pipeline that processes blocks in knight's order with quadrow constraints. Stages of the pipeline may maintain two local buffers that contain data from neighbor blocks of a current block. A first buffer contains data from the last C blocks processed at the stage. A second buffer contains data from neighbor blocks on the last row of a previous quadrow. Data for blocks on the bottom row of a quadrow are stored to an external memory at the end of the pipeline. When a block on the top row of a quadrow is input to the pipeline, neighbor data from the bottom row of the previous quadrow is read from the external memory and passed down the pipeline, each stage storing the data in its second buffer and using the neighbor data in the second buffer when processing the block.

Abstract: Briefly, in accordance with one or more embodiments, a reconfigurable 3D graphics processor includes a pipeline configuration manager, a rasterizer, and a memory coupled to the triangle rasterizer. The pipeline configuration manager is capable of configuring the graphics processor to operate in a direct rasterizing mode or a tiling mode to process a sequence of drawing commands received from a processing unit.

Abstract: Independently processing planes of display data is provided by a method of outputting a video stream. The method includes retrieving from memory a first plane of display data having a first set of display parameters and post-processing the first plane of display data to adjust the first set of display parameters. The method further includes retrieving from memory a second plane of display data having a second set of display parameters and post-processing the second plane of display data independently of the first plane of display data. The method further includes blending the first plane of display data with the second plane of display data to form blended display data and outputting the blended display data.

Abstract: Embodiments of an apparatus and method are disclosed that may allow for arbitrating multiple read requests to fetch pixel data from a memory. The apparatus may include a first and a second processing pipeline, and a control unit. Each of the processing pipelines may be configured to generate a plurality of read requests to fetch a respective one of a plurality of portions of stored pixel data. The control unit may be configured to determine a priority for each read request dependent upon display coordinates of one or more pixels corresponding to each of the plurality of portions of stored pixel data, and determine an order for the plurality of read requests dependent upon the determined priority for each read request.

Abstract: One embodiment of the present invention sets forth a technique for executing an operation once work associated with a version of a state object has been completed. The method includes receiving the version of the state object at a first stage in a processing pipeline, where the version of the state object is associated with a reference count object, determining that the version of the state object is relevant to the first stage, incrementing a counter included in the reference count object, transmitting the version of the state object to a second stage in the processing pipeline, processing work associated with the version of the state object, decrementing the counter, determining that the counter is equal to zero, and in response, executing an operation specified by the reference count object.

Abstract: A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve a top frame packet from the parameter buffer and determine if the frame packet is an internal type, i.e., intended for internal registers in a respective processing unit or if it is an external type, i.e., intended for an external register elsewhere in the graphics system. Based on the type of frame packet, the control circuit may update one or more register values accordingly.

Abstract: An information processing apparatus includes a first graphics chip having a first drawing processing capacity and being capable of producing a first image signal; a second graphics chip having a second drawing processing capacity higher than the first drawing processing capacity and being capable of producing a second image signal; an output changeover section capable of selectively outputting one of the first or second image signals; an inputting section configured to input a user operation to select one of the first graphics chip or the second graphics chip; and a control section configured to control the output of the output changeover section in response to the inputted user operation.

Abstract: The efficiency of shading and rendering processes can be improved through implementing object oriented programming for shading program languages. Computer graphics data representing a geometric model in a scene are determined and assigned to object oriented classes and subclasses and are subsequently sorted and grouped into several (e.g., two or more) groups based on the classification information. Once the computer graphics data are assigned in a class and/or subclasses and grouped, a shader interpreter implements SIMD operators on each group of data values.

Abstract: Techniques are disclosed relating to predication. In one embodiment, a graphics processing unit is disclosed that includes a first set of architecturally-defined registers configured to store predication information. The graphics processing unit further includes a second set of registers configured to mirror the first set of registers and an execution pipeline configured to discontinue execution of an instruction sequence based on predication information in the second set of registers. In one embodiment, the second set of registers includes one or more registers proximal to an output of the execution pipeline. In some embodiments, the execution pipeline writes back a predicate value determined for a predicate writer to the second set of registers. The first set of architecturally-defined registers is then updated with the predicate value written back to the second set of registers. In some embodiments, the execution pipeline discontinues execution of the instruction sequence without stalling.

Abstract: A method of calculating performance parameters for a type of data being executed by a unified processing subunit. In one embodiment, a task (e.g., a draw call) is executed by a processing pipeline (e.g., a GPU). An ALU within a unified processing subunit (e.g., a unified shader processing unit) is queried to determine a type of data (e.g., vertex processing, pixel shading) being processed by the ALU. Performance parameters (e.g., bottleneck and utilization) for the type of data being processed by the ALU is calculated and displayed (e.g., stacked graph). Accordingly, software developers can visualize component workloads of a unified processing subunit architecture. As a result, utilization of the unified processing subunit processing a particular data may be maximized while bottleneck is reduced. Therefore, the efficiency of the unified processing subunit and the processing pipeline is improved.

Abstract: A display driving architecture that can include two graphics pipelines with an optional connection between them to provide a mirrored mode. In one embodiment, one of the two pipelines can be automatically configured (e.g. routed in one of a plurality of ways, such as routing to do color conversion) based upon the type of cable that is coupled to a connector of the one pipeline. In another embodiment, a connection of a cable can cause display information (e.g. resolutions of an external display) to be provided to an application which can select a display mode while one of the graphics pipelines is kept in a low power state.

Abstract: A digital signal processor 1 is provided for performing digital image processing operations such as forward texture mapping. A first logic unit 21 receives input sample coordinates xr and xl, and determines a first color weight value “w” and a second color weight value “wN”. A second logic unit 23 weights an input sample color with the color weight value wN, with the resultant weighted sample color being added to accumulated weighted sample colors from one or more previous iterations, thereby producing a new accumulated weighted sample color, ie the rgbaPartOut signal 13. A third logic unit 25 is configured to weight the input sample color with the first color weight value w, with the resultant weighted sample color being added to the accumulated weighted sample colors rgbaPartIn to produce the output color signal rgbaOut 11.

Abstract: The desire to use an Accelerated Processing Device (APD) for general computation has increased due to the APD's exemplary performance characteristics. However, current systems incur high overhead when dispatching work to the APD because a process cannot be efficiently identified or preempted. The occupying of the APD by a rogue process for arbitrary amounts of time can prevent the effective utilization of the available system capacity and can reduce the processing progress of the system. Embodiments described herein can overcome this deficiency by enabling the system software to pre-empt a process executing on the APD for any reason. The APD provides an interface for initiating such a pre-emption. This interface exposes an urgency of the request which determines whether the process being preempted is allowed a grace period to complete its issued work before being forced off the hardware.

Abstract: A game server comprising a central processing unit to process video game program code and a graphics processing unit (GPU) to process graphics commands; back buffers to store video frames in response to the execution of the graphics commands; a front buffer to receive a video frame for rendering on a display after the video frame has been completed in one of the one or more back buffers, the front buffer outputting the video frame for display one scan line at a time at a designated scan out frequency, a subset of scan lines stored in the front buffer being associated with a VBI; a frame processing module to increase the number of scan lines to increase the likelihood that a new frame will be completed in a back buffer and ready for transfer to the front buffer at a time during the VBI.

Abstract: A system for handling graphics processing requests that includes a hypervisor having access to one or more graphics processing units (GPUs) and a network communication pipeline which transmits unprocessed graphics data and processed graphics data between virtual machines. The system further includes a first virtual machine (VM) having software installed thereon capable of obtaining graphics processing requests and associated unprocessed graphics data generated by the first VM, and transmitting the unprocessed graphics data and receiving processed graphics data via the network communication pipeline, and a second VM having access to the one or more graphics processing units (GPUs) via the hypervisor, and having software installed thereon capable of receiving transmitted unprocessed graphics data and transmitting processed graphics data via the network communication pipeline.

Abstract: Provided is a graphics processing method and apparatus using a post fragment shader. A rendering pipeline of the graphics processing apparatus may include a fragment shader that operates before a raster operator, and a post fragment shader that operates after the raster operator. Each of the fragment shader and the post fragment shader may apply a different effect to each of a plurality of fragments.

Abstract: A method and apparatus for managing operation of graphics processing units in a computer system. A processing thread in the computer system controls processing of a set of sinogram data by a graphics processing unit to form a set of graphics data. An output thread in the computer system controls writing of the set of graphics data to a storage system. The graphics processing unit is available to perform processing of another set of sonogram data while the set of graphics data is written to the storage system such that the increased availability of a plurality of graphics processing units is present.

Abstract: The present invention extends to methods, systems, and computer program products for para-virtualized GPGPU computation and GDI acceleration. Some embodiments provide a compute shader to a guest application within a para-virtualized environment. A vGPU in a child partition presents compute shader DDIs for performing GPGPU computations to a guest application. A render component in a root partition receives compute shader commands from the vGPU and schedules the commands for execution at the physical GPU. Other embodiments provide GPU-accelerated GDI rendering capabilities to a guest application within a para-virtualized environment. A vGPU in a child partition provides an API for receiving GDI commands, and sends GDI commands and data to a render component in a root partition. The render component schedules the GDI commands on a 3D rendering device. The 3D rendering device executes the GDI commands at the physical GPU using a sharable GDI surface.

Abstract: The present invention extends to methods, systems, and computer program products for providing domain, hull, and geometry shaders in a para-virtualized environment. As such, a guest application executing in a child partition is enabled use a programmable GPU pipeline of a physical GPU. A vGPU (executing in the child partition) is presented to the guest application. The vGPU exposes DDIs of a rendering framework. The DDIs enable the guest application to send graphics commands to the vGPU, including commands for utilizing a domain shader, a hull shader, and/or a geometric shader at a physical GPU. A render component (executing within the root partition) receives physical GPU-specific commands from the vGPU, including commands for using the domain shader, the hull shader, and/or the geometric shader. The render component schedules the physical GPU-specific command(s) for execution at the physical GPU.

Abstract: Analyzing an application executing on a target device. An application may be executed on a target device. Low cost measurement may be gathered regarding the application executing on the target device. In response to a trigger, high cost measurement data may be gathered regarding the application executing on the target device. The high cost measurement data may include graphics commands provided by the application. The graphics commands and related information may be stored and provided to a host. The host may modify the graphics commands to perform experiments to determine performance issues of the application executing on the target device. The host may determine whether the performance is limited by the CPU or the GPU and may determine specific operations that are causing performance issues. The host may provide suggestions for overcoming the performance issues.

Abstract: A graphics processing circuit includes at least two pipelines operative to process data in a corresponding set of tiles of a repeating tile pattern, a respective one of the at least two pipelines operative to process data in a dedicated tile, wherein the repeating tile pattern includes a horizontally and vertically repeating pattern of square regions. A graphics processing method includes receiving vertex data for a primitive to be rendered; generating pixel data in response to the vertex data; determining the pixels within a set of tiles of a repeating tile pattern to be processed by a corresponding one of at least two graphics pipelines in response to the pixel data, the repeating tile pattern including a horizontally and vertically repeating pattern of square regions; and performing pixel operations on the pixels within the determined set of tiles by the corresponding one of the at least two graphics pipelines.

Abstract: A system, method and a computer program product are provided for distributing prim groups for parallel processing in a single clock cycle. A work distributor divides a draw call for primitive processing into a plurality of prim groups according to a prim group size. The work distributor then distributes the plurality of prim groups to a plurality of shader engines for parallel processing of the plurality of prim groups during a clock cycle. The size of a prim group and a number of prim groups are scaled to the plurality of shader engines.

Abstract: Provided herein is a method for implementing antialiasing including independently operating different portions of a graphics pipeline at different sampling rates in accordance with pixel color details.

Abstract: Generating a tag layout from a set of tags and an ordering of the set of tags, wherein each tag includes a text label and a size for the text label, is disclosed. The system includes a processor accessible memory for receiving an ordered set of tags, each tag including a text label and a size for the text label, and at least one closed shape corresponding to a space for the tag layout. The system further includes a processor for generating the tag layout by computing a scale factor for either the closed shape or the size of the text labels in the set of tags such that all the tags in the set of tags fit within the closed shape, and the processor stores the generated tag layout in the memory.

Abstract: One embodiment of the present invention sets forth a technique for performing low latency computation on a parallel processing subsystem. A low latency functional node is exposed to an operating system. The low latency functional node and a generic functional node are configured to target the same underlying processor resource within the parallel processing subsystem. The operating system stores low latency tasks generated by a user application within a low latency command buffer associated with the low latency functional node. The parallel processing subsystem advantageously executes tasks from the low latency command buffer prior to completing execution of tasks in the generic command buffer, thereby reducing completion latency for the low latency tasks.

Abstract: A system and process is provided for the conversion of a stream of two-dimensional images into a pair of streams of images for providing the perception of a stream of three-dimensional images. Each complimentary image in the image stream undergoes the application of a selection and remapping process to independently alter portions of the image, so that the remappings shift the image elements in a manner which produces a stereo depth effect when the images are viewed through the appropriate viewing device.

Abstract: A system and method for efficiently scheduling memory access requests. A semiconductor chip includes a memory controller for controlling accesses to a shared memory and a display controller for processing frame data. In response to detecting an idle state for the system and the supported one or more displays, the display controller aggregates memory requests for a given display pipeline of one or more display pipelines prior to attempting to send any memory requests from the given display pipeline to the memory controller. Arbitration may be performed while the given display pipeline sends the aggregated memory requests. In response to not receiving memory access requests from the functional blocks or the display controller, the memory controller may transition to a low-power mode.

Abstract: A system, method and apparatus are disclosed, in which a processing unit is configured to perform secondary processing on graphics pipeline data outside the graphics pipeline, with the output from the secondary processing being integrated into the graphics pipeline so that it is made available to the graphics pipeline. A determination is made whether to use secondary processing, and in a case that secondary processing is to be used, a command stream, which can comprise one or more commands, is provided to the secondary processing unit, so that the unit can locate and operate on buffered graphics pipeline data. Secondary processing is managed and monitored so as to synchronize data access by the secondary processing unit with the graphics pipeline processing modules.

Abstract: Concurrent display of graphic content on multiple displays is described. A frame of graphic content to be displayed on multiple displays can be written to a single memory location. Previously written graphic content can be read to multiple displays having misaligned synchronization signals and new graphic content can be written to a different memory location concurrently.

Abstract: A data processing system determines for a stream of instructions to be executed, whether there are any instructions that can be re-ordered in the instruction stream 41 and assigns each such instruction to an instruction completion tracker and includes in the encoding for the instruction an indication of the instruction completion tracker it has been assigned to 42. For each instruction in the instruction stream, an indication of which instruction completion trackers, if any, the instruction depends on is also provided 43, 44. Then, when an instruction that is indicated as being dependent on an instruction completion tracker is to be executed, the status of the relevant instruction completion tracker is checked before executing the instruction.

Abstract: This image processing circuit performs, with reduced power consumption, pipeline processing of image data. This image processing circuit has an image processing unit which performs pipeline processing of image data having N-bit pixel data. The image processing unit has a pipeline register (400) having upper bit flip-flop circuits (401), lower-order bit flip-flop circuits (402), a comparison circuit (403) which determines whether the input values and the output values of the upper bit flip-flop circuits (401) are the same, and a clock gating control circuit (404) which controls supply of the clock signal such that, when the aforementioned input and output values are the same, the clock signal is not supplied to the upper bit flip-flop circuits (401). The pipeline register (400) does not have a circuit for controlling supply of the clock signal to the lower 1-bit flip-flop circuits (402), and holds pixel data or calculation results during pipeline processing.

Abstract: In at least some embodiments, an apparatus includes a hardware accelerator subsystem with a pipeline. The hardware accelerator subsystem is configured to perform error recovery operations in response to a bit stream error. The error recovery operations comprise a pipe-down process to completely decode a data block that is already in the pipeline, an overwrite process to overwrite commands in the hardware accelerator subsystem with null operations (NOPs) once the pipe-down process is complete, and a pipe-up process to restart decoding operations of the pipeline at a next synchronization point.

Abstract: An internal bus bridge architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus root via a host bus bridge that is internal to at least one bus endpoint. In addition, the bus endpoints are directly coupled to each other. Embodiments are usable with known bus protocols.

Abstract: A projector is provided with: an input line memory which holds an input image signal corresponding to one line; an image processor which generates an intermediate image signal correction-processed according to distortion of a projection lens, using the input image signal transferred from the input line memory; an output line memory which holds the intermediate image signal corresponding to one line; and an LCOS which guides light radiated from a light source to the projection lens in accordance with the intermediate image signal. The image processor is provided with an input supplementation buffer which stores the input image signals of a plurality of lines, an input data buffer which stores input image signals required to generate the intermediate image signal corresponding to one line, and a number-of-supplementary-lines calculator which calculates the number of supplementary lines of the input image signals.

Abstract: The present disclosure includes systems and techniques relating to processing of high resolution images, such as digital painting on high resolution images. In general, one aspect of the subject matter described in this specification can be embodied in a method that includes receiving input defining a modification to a target image; determining, at a first processor, a low resolution proxy result of the modification applied to the target image; determining, at a second processor, a higher resolution result of the modification applied to the target image; displaying the low resolution proxy result before completion of the determining at the second processor; and updating the displayed low resolution proxy result with the higher resolution result. Other embodiments of this aspect include corresponding systems, apparatus, and computer program products.

Abstract: A tile-based graphics processing system comprises a host processor 1 and a graphics processing pipeline 3. The graphics processing pipeline 3 includes a rasteriser, a renderer, a tile buffer comprising an allocated amount of memory for use as the tile buffer, and a write out stage configured to write data stored in the tile buffer to an external memory. The driver 4 for the graphics processing pipeline 3 on the host processor 1 determines the tile data storage requirements for each render target to be generated for a render output to be generated by the graphics processing system and allocates portions of the memory allocated for use as the tile buffer to respective ones of the render targets based on the determination.

Abstract: Embodiments of the present invention provide graphic processing techniques and configurations including an apparatus comprising a storage medium having stored therein a table comprising information about respective positions and sizes of a number of rectangular blocks, the rectangular blocks to substantially form at least one plane having an arbitrary shape object, and at least one overlay engine operatively coupled with the table and associated with the at least one plane to request the information about the respective positions and the sizes of the number of rectangular blocks to provide graphics overlay of the arbitrary shape object. Other embodiments may be described and/or claimed.

Abstract: An apparatus includes a plurality of image processing circuits. Each image processing circuit generates an image frame corresponding to a single large surface. The first image processing circuit provides a portion of the generated image frame for a first display or plurality of displays and provides a remaining portion of the image frame to the remaining image processing circuits. The next image processing circuits provides the remaining portion of the image frame for the next plurality of displays.

Abstract: A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.

Abstract: In general, aspects of this disclosure describe example techniques for efficient usage of the fixed data rate processing of a graphics processing unit (GPU) for a variable data rate processing. For example, the GPU may be coupled to a pixel value processing unit that receives pixel values for pixels in an image processed by the GPU. The pixel value processing unit may determine whether the pixel values are for pixels that require further processing, and store the pixel values for the pixels that are required for further processing in a buffer.