Abstract: Video conversion using a 3D graphics pipeline of a graphical processing unit (GPU) is disclosed. A plurality of video data formatted in a first video format is accessed from a memory unit. Moreover, the plurality of video data is converted from the first video format to a second video format using a 3D graphics pipeline of the GPU. The plurality of video data formatted in the second video format is sent to the memory unit. The 3D graphics pipeline applies a filtering technique. In an embodiment, the filtering technique is an interpolation technique.

Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).

Abstract: A system and method for processing graphics data which improves utilization of read and write bandwidth of a graphics processing system. The graphics processing system includes an embedded memory array having at least three separate banks of single ported memory in which graphics data are stored in memory page format. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory concurrently with reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to the bank of memory from which the pre-processed data was read. The processing pipeline is capable of concurrently processing an amount of graphics data at least equal to the amount of graphics data included in a page of memory.

Abstract: The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration between the video and graphics and processor requests sent to the system. The arbiter has three output ports coupled to the combined engine. The combined engine is a hardware engine capable of processing either video data or graphics data. The output of the combined engine is provided to the frame buffer for the storage of pixel data. The output of the frame buffer is coupled to a display processing unit that renders the pixel data for display.

Abstract: A pixel processing system and method which permits rendering of complicated three dimensional images using a shallow graphics pipeline including reduced gate counts and low power operation. Pixel packet information includes pixel surface attribute values retrieved in a single unified data fetch stage. A determination is made if the pixel packet information contributes to an image display presentation (e.g., a depth comparison of Z values may be performed). The pixel packet information processing is handled in accordance with results of the determining. The pixel surface attribute values and pixel packet information are removed from further processing if the pixel surface attribute values are occluded. In one exemplary implementation, the pixel packet includes a plurality of rows and the handling is coordinated for the plurality of rows.

Abstract: A rendering method, medium and apparatus for sequentially performing one or more third raster operations to test whether a fragment can be displayed as a pixel after sequentially performing one or more second raster operations to test whether the fragment can be displayed as the pixel, so as to provide efficient power consumption and rapid completion of rendering.

Abstract: A mechanism for synchronizing state variables used by texture pipelines in a multi-pipeline graphics texture engine. The mechanism ensures that, as polygons are processed by a texture engine, the state variables associated with each polygon are distributed in parallel to each texture pipeline, regardless of whether the texture engine is processing a single texture or a blend of different textures. When the texture engine processes a blend of different textures, signals controlling the operation of multiple texture pipelines are asserted. However, when the texture engine processes a single texture for a polygon, an embodiment of the invention continues to distribute received state variables to each of the texture pipelines, but only triggers the processing portion of the texture pipeline performing the single texture operation. The processing portions of the remaining texture pipelines may not be not triggered.

Abstract: Techniques are described for processing computerized images with a graphics processing unit (GPU) using a unified vertex cache and shader register file. The techniques include creating a shared shader coupled to the GPU pipeline and a unified vertex cache and shader register file coupled to the shared shader to substantially eliminate data movement within the GPU pipeline. The GPU pipeline sends image geometry information based on an image geometry for an image to the shared shader. The shared shader performs vertex shading to generate vertex coordinates and attributes of vertices in the image. The shared shader then stores the vertex attributes in the unified vertex cache and shader register file, and sends only the vertex coordinates of the vertices back to the GPU pipeline. The GPU pipeline processes the image based on the vertex coordinates, and the shared shader processes the image based on the vertex attributes.

Abstract: A graphical display system utilizes a plurality of display devices and a plurality of graphical acceleration units for rendering graphical data to the display devices. More specifically, each of the plurality of graphical acceleration units respectively interfaces a portion of graphical data defining an image to one of the display devices. Each of the display devices displays a portion of the image based on the graphical data rendered to it. To make the system more efficient and/or to improve image quality, at least one of the graphical acceleration units includes a plurality of graphical pipelines for rendering the graphical data to be displayed by the display device that is interfaced with the one graphical acceleration unit.

Abstract: A computer system includes a computer system having a system memory and a bridging device coupled to the system memory, the bridging device including a memory controller. The computer system also includes a graphics processor unit (GPU) coupled to one port of the bridging device and a central processing unit (CPU) coupled to another port of the bridging device. The GPU and the CPU access the system memory via the memory controller.

Abstract: A computer-implemented method and user interface for organizing graphical operations and displaying performance data of a graphics processing pipeline. More specifically, embodiments provide a convenient and effective mechanism for enhancing graphics processing by automatically determining and grouping graphical operations with similar state attributes relating to one or more units of the graphics pipeline. As such, pipeline adjustments for reducing execution time of one graphical operation may benefit other graphical operations with similar state attributes, thereby reducing the number of pipeline adjustments and allowing more careful selection of graphical operations to increase performance and reduce image degradation. Also, the display of the grouped graphical operations also provides information for determining the troublesome operations. In one embodiment, the groups are ranked by their respective execution time.

Abstract: This disclosure describes a graphics processing unit (GPU) pipeline that uses one or more shared arithmetic logic units (ALUs). In order to facilitate such sharing of ALUs, the stages of the disclosed GPU pipeline may be rearranged relative to conventional GPU pipelines. In addition, by rearranging the stages of the GPU pipeline, efficiencies may be achieved in the image processing. Unlike conventional GPU pipelines, for example, an attribute gradient setup stage can be located much later in the pipeline, and the attribute interpolator stage may immediately follow the attribute gradient setup stage. This allows sharing of an ALU by the attribute gradient setup and attribute interpolator stages. Several other techniques and features for the GPU pipeline are also described, which may improve performance and possibly achieve additional processing efficiencies.

Abstract: A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.

Abstract: A method for processing divergent samples in a programmable graphics processing unit is described. In one embodiment, the method includes the step of incrementing a subroutine depth of a first sample to designate that first call instructions are to be executed on the first sample. The method also includes the steps of pushing state data of a second sample upon which the first call instructions are not to be executed onto a global stack and executing the first call instructions on the first sample.

Abstract: Systems and methods that optimize GPU processing by front loading activities from a set time/binding time to creation time via enhancements to an API that configures the GPU. Such enhancements to the API include: implementing layering arrangements, employing state objects and view components for data objects; incorporating a pipeline stage linkage/signature, employing a detection mechanism to mitigate error conditions. Such an arrangement enables front loading of the work and reduction of associated API calls.

Abstract: A graphics processor includes an embedded frame buffer for storing frame data prior to sending the frame data to an external location, such as main memory. A copy pipeline is provided which converts the data from one format to another format prior to writing the data to the external location. The conversion may be from one RGB color format to another RGB color format, from one YUV format to another YUV format, from an RGB color format to a YUV color format, or from a YUV color format to an RGB color format. MPEG image data initially stored in main memory in a YUV format as a texture is transferred to the embedded frame buffer prior to initiating a copy-out process via the copy pipeline from the embedded frame buffer to an external frame buffer in main memory. During the copy-out process, pixels are converted from YUV format to an RGB format.

Abstract: In a raster stage of a graphics pipeline, a method for rasterizing non-rectangular tile groups. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor. The graphics primitive is rasterized at a first level by generating a non-rectangular footprint comprising a set of pixels related to the graphics primitive. The graphics primitive is then rasterized at a second level by accessing the set of pixels and determining covered pixels out of the set of pixels. The raster stage subsequently outputs the covered pixels for rendering operations in a subsequent stage of the graphics processor.

Abstract: An efficient graphics pipeline with a pixel cache and data pre-fetching. By combining the use of a pixel cache in the graphics pipeline and the pre-fetching of data into the pixel cache, the graphics pipeline of the present invention is able to take best advantage of the high bandwidth of the memory system while effectively masking the latency of the memory system. More particularly, advantageous reuse of pixel data is enabled by caching, which when combined with pre-fetching masks the memory latency and delivers high throughput. As such, the present invention provides a novel and superior graphics pipeline over the prior art in terms of more efficient data access and much greater throughput. In one embodiment, the present invention is practiced within a computer system having a processor for issuing commands; a memory sub-system for storing information including graphics data; and a graphics sub-system for processing the graphics data according to the commands from the processor.

Abstract: A method for efficiently processing graphics data for graphics primitives, the graphics data including vertex coordinate information and vertex attribute data. Coordinate information, in the form of homogeneous coordinates, of the graphics primitive determines whether the graphics primitive is to be rendered. If the primitive is to be rendered, then attribute data associated with the location information is retrieved. However, if the data is not to be rendered, then the location information is discarded. By only retrieving parameters for a primitive that is rendered, performance is increased. In one embodiment, the attribute data is fetched before it is known whether or not the graphics primitive is to be rendered, and if not, the prefetch is aborted, and new location information is fetched.

Abstract: An arithmetic logic stage in a graphics pipeline is described. The arithmetic logic stage includes a plurality of series-coupled scalar arithmetic logic units, each unit for performing an arithmetic logic operation on a set of input operands and for producing a result based thereon.

Abstract: The VPC unit and setup unit of a graphics processing subsystem perform culling operations. The VPC unit performs culling operations on geometric primitives falling within a specific criteria, such as having a property within a numerical range limit of the VPC unit. This limitation reduces the complexity of the VPC unit. As increasing rendering complexity typically produces a large number of small primitives, the VPC unit can cull many primitives despite its culling limitations. The VPC unit also includes a cache for storing previously processed vertices in their transformed form, along with culling information previously computed for the vertices. To minimize memory bandwidth, the VPC unit retrieves vertex data used for culling operations first. After completing the culling operations, the VPC unit retrieves the attributes of a vertex only if the primitive has not been culled. The VPC unit applies a perspective correction factor to the vertex attributes.

Abstract: An image processing apparatus including an image processing unit structured to include one or more image processing modules and one or more buffer modules each having a buffer for storing image data, the respective modules being connected in a pipe line mode or a directed acyclic graph mode. Each of the buffer modules including a write unit that when image data to be written is input from the module at the proceeding stage, switches a write method depending on whether or not the input image data is compressed and writes the image data to the buffer; and a read unit that when image data is requested from the module at the following stage, switches an output method depending on whether or not the read image data is compressed, reads the image data from the buffer, and outputs the image data to the module at the following stage.

Abstract: A system, method and computer program product are provided for programmable processing of fragment data in a computer hardware graphics pipeline. Initially, fragment data is received in a hardware graphics pipeline. It is then determined whether the hardware graphics pipeline is operating in a programmable mode. If it is determined that the hardware graphics pipeline is operating in the programmable mode, programmable operations are performed on the fragment data in order to generate output. The programmable operations are performed in a manner/sequence specified in a graphics application program interface. If it is determined that the hardware graphics pipeline is not operating in the programmable mode, standard graphics application program interface (API) operations are performed on the fragment data in order to generate output.

Abstract: A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video data. The video decoder includes multiple row decoding engines for decoding the MPEG-2 video data. Each row decoding engine concurrently decodes two or more rows of the MPEG-2 video data. The row decoding engines have a pipelined architecture for concurrently decoding multiple rows of MPEG-2 video data. The video decoder may be integrated on an integrated circuit chip with other video and graphics system components such as transport processors for receiving one or more compressed data streams and for extracting video data, and a video compositor for blending processed video data with graphics.

Abstract: Digital Image compositing using a programmable graphics processor is described. The programmable graphics processor supports high-precision data formats and can be programmed to complete a plurality of compositing operations in a single pass through a fragment processing pipeline within the programmable graphics processor. Source images for one or more compositing operations are stored in graphics memory, and a resulting composited image is output or stored in graphics memory. More-complex compositing operations, such as blur, warping, morphing, and the like, can be completed in multiple passes through the fragment processing pipeline. A composited image produced during a pass through the fragment processing pipeline is stored in graphics memory and is available as a source image for a subsequent pass.

Abstract: A system and method for interfacing graphics program modules written to execute on a plurality of functional units of a graphics processor using a shared memory. A central processing unit (CPU) receives a first graphics program module that outputs a first parameter referenced by a first graphics program module identifier, a second graphics program module that inputs the first parameter by referencing the first graphics program module identifier, and a first data structure that includes, in a pre-defined order, a list of first data structure identifiers. The CPU identifies a memory location in the shared memory, based on the pre-defined order of the first data structure identifiers, for one of the first data structure identifiers that is the same as the first graphics program module identifier. The CPU modifies the first and second graphics program modules to reference the first parameter by the identified memory location in the shared memory.

Abstract: An improved image data processing architecture utilizes a negotiation protocol with an information push technique to provide a more efficient and effective image data rendering pipeline. The improved image data processing architecture allows the optimization of data transfer through the use of image transfer parameters and flags. In another aspect of the invention, a selection mechanism is provided to allow a client application to easily select an image frame as the current frame in a multi-dimensional image. Image sinks within the invention may further support non-blocking behavior.

Abstract: A three-dimensional graphics data rendering method. The method divides initially inputted first graphics data into a static object and a dynamic object, performs a rendering process with respect to the static object, and updates a predetermined buffer with the rendering result. Then the method performs a transformation process, a portion of the rendering process with respect to the dynamic object, determines an updating area, and stores a rendering result of the buffer corresponding to the updating area in a predetermined storage unit; performs a remaining rendering process with respect to the dynamic object, updates the buffer and outputs a first image whose rendering is completed. Finally, the method restores a rendering result of the updating area to the buffer by referring to the storage unit and utilizes a rendering result of the restored buffer as a rendering result of subsequently inputted second graphics data.

Abstract: A graphics processor includes a graphics pipeline having a set of tap points. A configurable test point selector monitors a selected subset of tap points and counts statistics for at least one condition associated with each tap point of the subset of tap points.

Abstract: A system, method and computer program product are provided for depth clamping in a hardware graphics pipeline. Initially, a depth value is identified. It is then determined as to whether a hardware graphics pipeline is operating in a depth clamping mode. If the hardware graphics pipeline is operating in the depth clamping mode, the depth value is clamped within a predetermined range utilizing the hardware graphics pipeline.

Abstract: An improved raster engine adapted to render video data from a frame buffer to one of a plurality of disparate displays is disclosed which comprises apparatus for detecting one or more video underflow conditions. The raster engine includes a first in first out (FIFO) memory, which obtains video data from a frame buffer and provides video data to a video pipeline, along with input and output counters associated with the FIFO memory. A control logic system is associated with the FIFO memory and adapted to provide an underflow indication according to the input and output counter values. A method for detecting video underflow in a video controller raster engine is also disclosed.

Abstract: The present invention provides data processing technology for making two or more processing units cooperate with one another such that output data from respective groups of processing units (GSM) are merged by a respective sub-MG (merger), data from the sub-MGs are merged by a main MG, and the merged output data are displayed on a display unit. Each GSM initiates drawing processing assigned thereto in response to the reception of a drawing enable signal and, after execution of the processing, outputs a drawing end signal. The GSMs to which the drawing enable signal is to be sent, and the GSMs from which the drawing end signal is to be received, are set for each application. A main SYNC sends the drawing enable signal to corresponding GSMs in the order of setting for an application in response to the reception of a processing request from the application, while it receives the drawing end signal from the corresponding GSMs so that the processing results of the GSMs will be displayed on the display unit.

Abstract: A system, method and article of manufacture are provided for programmable processing in a computer graphics pipeline. Initially, data is received from a source buffer. Thereafter, programmable operations are performed on the data in order to generate output. The operations are programmable in that a user may utilize instructions from a predetermined instruction set for generating the same. Such output is stored in a register. During operation, the output stored in the register is used in performing the programmable operations on the data.

Abstract: An arbitration mechanism for balancing memory requests issued by parallel texture pipelines in a multiple pipeline texture engine. The mechanism ensures that, as polygon textures are processed by a texture engine, all of the memory requests associated with a portion of a given graphics texture are issued by all texture pipelines before any texture pipeline may issue a memory request for another portion of a graphics texture. Thus, the invention balances graphics texture processing between parallel texture pipelines operating together, thereby improving processing efficiency and preventing deadlock conditions.

Abstract: A graphics processor includes an arithmetic logic unit (ALU) stage for processing pixel packets. Pixels are assigned as either even pixels or odd pixels. The pixel packets of odd and even pixels are interleaved to account for ALU latency.

Abstract: A video platform architecture provides video processing using parallel vector processing. The video platform architecture includes a plurality of video processing modules, each module including a plurality of processing elements (PEs). Each PE provides parallel vector processing. Specifically, means are provided to read all elements of one or two source vector registers in each PE simultaneously, process the read elements by a set of arithmetic-logical units (ALUs), and write back all results to one of the vector registers, all of which occurs in one PE cycle. To provide such parallel vector processing capabilities, the datapath of each PE is built as a set of identical PE processing slices, each of which includes an integer arithmetic-logical unit (ALU), a vector register bank, and a block register bank. A block/vector register bank holds all I elements of row J in a two-dimensional I×J data blocks for all block/vector registers provided by the architecture.

Abstract: A method, apparatus, and system for rendering are disclosed. A rendering request is defined, where the rendering request describes an object to be rendered. A progressive cache is queried to determine a cached element most representing a display image satisfying the rendering request. The cached element is sent to a starting stage of a rendering pipeline for the object, where the starting stage is associated with the cached element. An output of the starting stage is sent to an input of a next stage of the rendering pipeline. A final stage of the rendering pipeline determines the display image satisfying the rendering request.

Abstract: A method and system for a general instruction capable raster stage that generates flexible pixel packets is disclosed. In one embodiment, the rasterizing of a geometric primitive comprising a plurality of vertices wherein each vertex comprises a respective color value, is performed by a rasterization module of a graphics pipeline. The rasterizing includes a plurality of programmable interpolators for computing pixel parameters for pixels of a geometric primitive. The rasterizing module further includes a memory for storing a first instruction associated with a first programmable interpolator for indicating a first parameter on which said first programmable interpolator is to operate and for indicating a first portion of a pixel packet in which to store its results.

Abstract: A graphics processing chip which includes parallel texturing pipelines, with task allocation units which can bypass inoperative ones of said pipelines. Chips which have some but not all pipelines operative can still have full functionality, although performance is reduced.

Abstract: A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. The graphics processor includes an embedded frame buffer for storing frame data prior to sending the frame data to an external location, such as main memory. A copy pipeline is provided which converts the data from one format to another format prior to writing the data to the external location. The conversion may be from one RGB color format to another RGB color format, from one YUV format to another YUV format, from an RGB color format to a YUV color format, or from a YUV color format to an RGB color format. The formatted data is either transferred to a display buffer, for use by the video interface, or to a texture buffer, for use as a texture by the graphics pipeline in a subsequent rendering process.

Abstract: In a pipeline process in which plural image processing sections (image processing modules), for example, an image inputting section 131, a histogram producing section 132, and a binarizing section 133 are connected in a pipeline manner, each of the image processing sections 131, 132, and 133 is provided with a function of reinitializing a state to cause each process to be again performed with being started from the beginning of an image, whereby image data to be processed can be reread.

Abstract: A system and method are provided for directing the flow of data and instructions into at least one functional unit. In one embodiment of a system of components defining a plurality of nodes, a queue network manager (QNM) forming a part of each node, is provided. In this embodiment, the QNM comprises an interface to a network that supports intercommunication among the plurality of nodes, an interface configured to pass messages with a functional unit within the node, a random access memory (RAM) configured to store at least one of a message and a programmable instruction, and logic configured to control an operational aspect of a functional unit based on contents of the programmable instruction.

Abstract: A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. A relatively low chip-footprint, versatile texture environment (TEV) processing subsystem is implemented in a pipelined graphics system circulates computed color and alpha data over multiple texture blending/shading cycles (stages). The texture-environment subsystem combines per-vertex lighting, textures and constant (rasterized) colors to form computed pixel color prior to fogging and final pixel blending. Blending operations for color (RGB) and alpha components are independently processed by a single sub-blend unit that is reused over multiple processing stages to combine multiple textures.

Abstract: A three-dimensional (3D) graphics pipeline renders a sequence of images of 3D scenes each composed of a plural set of objects. The pipeline comprises an antialiasing oversampling mechanism to perform for a given image, at an early stage of the pipeline, oversampling on a portion of the objects of the given image.

Abstract: An image processing circuit comprising plural line buffers is provided. Each line buffer stores pixel data of plural pixels as line data. A first image processing part performs a first image processing task on original image data provided from the exterior by using the line data stored in at least one of the line buffers. A second image processing part performs a second image processing task on the processed image data from the first image processing part by using the line data stored in at least one of the line buffers. A line buffer selector selectively connects the first image processing part and the second image processing part to any number of line buffers. An output path selector selects one of an output path that skips the second image processing task and an output path that performs the second image processing task.

Abstract: A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Abstract: A multiple-level graphics processing system and method (e.g., of an operating system) for providing improved graphics output including, for example, smooth animation. One such multiple-level graphics processing system comprises two components, including a tick-on-demand or slow-tick high-level component, and a fast-tick (e.g., at the graphics hardware frame refresh rate) low-level component. In general, the high-level, less frequent component performs computationally intensive aspects of updating animation parameters and traversing scene data structures, in order to pass simplified data structures to the low-level component. The low-level component operates at a higher frequency, such as the frame refresh rate of the graphics subsystem, to process the data structures into constant output data for the graphics subsystem. The low-level processing includes interpolating any parameter intervals as necessary to obtain instantaneous values to render the scene for each frame of animation.

Abstract: A programmable graphics pipeline and method for processing multiple partitioned multimedia data, such as graphics data, image data, video data, or audio data. A preferred embodiment of the programmable graphics pipeline includes an instruction cache, a register file, and a vector functional unit that perform partitioned instructions. In addition, an enhanced rasterization unit is used to generate inverse-mapped source coordinates in addition to destination output coordinates for graphics and other media processing. An enhanced texture address unit generates corresponding memory addresses of source texture data for graphics processing and source media data for media processing. Data retrieved from memory are stored in an enhanced texture cache for use by the vector functional unit. A vector output unit includes a blending unit for graphics data and an output buffer for wide media data.

Abstract: A 3D graphics architecture in which interfaces to memory are combined with pipeline processing. The rendering units are not all connected in a straight-through pipeline relationship: instead the rendering pipeline is “broken,” so that the stream of fragments (e.g. triangles) being processed is parked in memory. This turns out to be surprisingly efficient as a way to separate rendering processes where the workload balance is different. Preferably a first write to memory is performed after transformation and lighting calculations and before double-pass Z-buffering, and a second write to memory is performed before texturing. If Z-buffering or texturing is not being used for a particular rendering task, one or both of the memory interfaces can be switched off for that task. This economizes on memory bandwidth while retaining full flexibility.

Abstract: A graphics and video controller 105 is provided which includes a dual aperture interface 206 for receiving words of graphics and video pixel data, each word of such data associated with an address directing that word to be processed as either graphics or video data. Circuitry 200, 201, 202, 207, 208 is provided for writing a word of the pixel data received from the interface 206 to a one of the on- and off-screen memory areas corresponding to the address associated with the received word. Circuitry 201, 202 is provided for selectively retrieving graphics and video data from the on-screen and off-screen memory areas. A first pipeline 205 is provided for processing data received from the on-screen area of frame buffer 107 while a second pipeline 204 is provided for processing data retrieved from the off-screen area of the frame buffer.