Abstract: A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using the available processing resources to produce resulting data, and the resulting data is passed to an input/output device.

Abstract: Systems and methods that provide for a common device enumeration point to a class of software objects, which represent hardware and can emit 2D bitmaps, via a presentation interface component. Such presentation interface component can further include a factory component that centralizes enumeration and creation for any components that control or communicate with the frame buffer of the graphics display subsystems. Accordingly, a smooth transition can be supplied between full screen and window models, within desktop composition systems, wherein applications can readily support such transitions.

Abstract: A silicon chip of a monolithic construction for use in implementing a multiple core graphics processing and display subsystem in a computing system having a CPU, a system memory, an operating system (OS), a CPU bus, and a display device with a display surface. The computing system supports (i) one or more software applications for issuing graphics commands, (ii) one or more graphics libraries for storing data used to implement said graphics commands. The silicon chip comprises multiple graphic pipeline cores, a partial frame buffer for buffering pixels corresponding to image fragments, a routing center, control unit, and a display interface, for displaying composited images on the display surface of the computing system.

Abstract: A display driving architecture that can include two graphics pipelines with an optional connection between them to provide a mirrored mode. In one embodiment, one of the two pipelines can be automatically configured (e.g. routed in one of a plurality of ways, such as routing to do color conversion) based upon the type of cable that is coupled to a connector of the one pipeline. In another embodiment, a connection of a cable can cause display information (e.g. resolutions of an external display) to be provided to an application which can select a display mode while one of the graphics pipelines is kept in a low power state.

Abstract: Methods and apparatus for improving the effects of display underflow using a variable horizontal blanking interval are disclosed. One embodiment of the present invention is a method of display that includes detecting a data ready signal that indicates availability of display data for transmission from a display pipeline, and generating a line-transmit signal based upon a clock signal and the data ready signal. The line-transmit signal is provided to the display pipeline. The line-transmit signal is substantially coincident with the clock signal if the data ready signal is set, and may be delayed if the data ready signal is not asserted. The display pipeline transmits the display data upon receiving the line-transmit signal.

Abstract: A method of controlling the mode of parallel operation of a multi-mode parallel graphics processing system (MMPGPS) embodied within a host computing system having (i) host memory space (HMS) for storing one or more graphics-based applications and a graphics library for generating graphics commands and data (GCAD) during the run-time (i.e. execution) of the graphics-based application, (ii) one or more CPUs for executing said graphics-based applications, (iii) a display device for displaying images containing graphics during the execution of said graphics-based applications, and (iv) a multi-mode parallel graphics rendering subsystem supporting multiple modes of parallel operation selected from the group consisting of object division, image division, and time division and having a plurality of graphic processing pipelines (GPPLs) supporting a parallel graphics rendering process that employs one of the object division, image division and/or time division modes of parallel operation.

Abstract: A method for identifying changes between a current image and a previous image comprises generating a mask using a graphics processing unit, the mask identifying differences between the current and previous images using the graphics processing unit to identify at least a portion of the current image based on the mask and copying image data of the current image corresponding to the identified portions from memory associated with the graphics processing unit to memory associated with a central processing unit.

Abstract: Techniques are described for processing computerized images with a graphics processing unit (GPU) using an extended vertex cache. The techniques include creating an extended vertex cache coupled to a GPU pipeline to reduce an amount of data passing through the GPU pipeline. The GPU pipeline receives an image geometry for an image, and stores attributes for vertices within the image geometry in the extended vertex cache. The GPU pipeline only passes vertex coordinates that identify the vertices and vertex cache index values that indicate storage locations of the attributes for each of the vertices in the extended vertex cache to other processing stages along the GPU pipeline. The techniques described herein defer the setup of attribute gradients to just before attribute interpolation in the GPU pipeline. The vertex attributes may be retrieved from the extended vertex cache for attribute gradient setup just before attribute interpolation in the GPU pipeline.

Abstract: A chipset is electrically connected with an external graphic module, which generates a first graphic signal and outputs it to the chipset. The chipset includes an internal graphic module and a control module. The internal graphic module generates a second graphic signal, and the control module receives the first graphic signal and the second graphic signal. The control module divides the first graphic signal into at least two first graphic sub-signals and divides the second graphic signal into at least two second graphic sub-signals, respectively. When under a first output mode, the control module simultaneously outputs one of the first graphic sub-signals and one of the second graphic sub-signals.

Abstract: A computing system capable of parallelizing the operation of multiple graphics processing units (GPUs) supported on a hybrid CPU/GPU fusion-architecture chip and/or on an external graphics card, and employing a multi-mode parallel graphics rendering subsystem having software and hardware implemented components. The computing system includes (i) CPU memory space for storing one or more graphics-based applications, (ii) one or more CPUs for executing the graphics-based applications, (iii) a multi-mode parallel graphics rendering subsystem supporting multiple modes of parallel operation, (iv) a plurality of graphic processing pipelines (GPPLs), implemented using the GPUs, and (vi) an automatic mode control module. During the run-time of the graphics-based application, the automatic mode control module automatically controls the mode of parallel operation of the multi-mode parallel graphics rendering subsystem so that the GPUs are driven in a parallelized manner.

Abstract: The present invention provides a scheme for compressing and decompressing the depth, or Z, components of image data. Image data is grouped into a plurality of tiles. A test is performed to determine if a tile can be compressed so that its size after compression is less than its size before compression. If so, the tile is compressed. A tile table includes a flag that can be set for each tile that is compressed. In one scheme, each tile comprises a 4×4 block of pixels. For each pixel, the visible depth complexity is determined where each visible level of depth complexity is represented by a plane equation. Depending on the depth complexity, a compression scheme is chosen that stores multiple plane equations in cache lines. The compression scheme can be used with unsampled or multisampled data and provides higher levels of compression in multisampled environments.

Abstract: A processing device has plural processing modules executing a processing; and plural connectors each having a linking section, an associating section, and a controller. The linking section is able to link with at least one other connector at an input side or an output side. The associating section associates the connector with one of the processing modules. In accordance with a linked state, the controller controls the processing module associated by the associating section.

Abstract: A computing system capable of parallelizing the operation of multiple graphics processing units (GPUs) supported on an integrated graphic device (IGD) embodied within a bridge circuit, and employing a multi-mode parallel graphics rendering subsystem having software and hardware implemented components. The computing system includes (i) CPU memory space for storing one or more graphics-based applications, (ii) one or more CPUs for executing the graphics-based applications, (iii) an external graphics card supporting at least one GPU and being connected to the bridge circuit by way of a data communication interface, (iv) a multi-mode parallel graphics rendering subsystem supporting multiple modes of parallel operation, (v) a plurality of graphic processing pipelines (GPPLs), implemented using the GPUs, and (vi) an automatic mode control module.

Abstract: A device has a processor for processing a vertex processing stage, a sub-screen dividing stage and a pixel rendering stage of a three-dimensional (3D) graphics pipeline. The processor includes processing threads which balance the work load of the 3D graphics pipeline by prioritizing processing for the pixel rendering stage over other stages. Each processing thread, operating in parallel and independently, checks a level of tasks in a Task list of sub-screen tasks. If the level is below a threshold value, empty or the sub-screen tasks are all locked, the processing thread loops to the vertex processing stage. Otherwise, the processing thread processes a sub-screen task during the pixel rendering stage.

Abstract: A graphics processing pipeline may include at least two or more pipes, such that a lower frequency operation may be executed on one pipe while a higher frequency operation in the same instruction stream is executed at the same time on another pipe. In some cases, the lower frequency operation result may be held for later use in connection with the higher frequency operation on a different pipe. Especially where unused slots can be used for the lower frequency operation, efficiency may be improved.

Abstract: A method of operating a Linear Complementarity Problem (LCP) solver is disclosed, where the LCP solver is characterized by multiple execution units operating in parallel to implement a competent computational method adapted to resolve physics-based LCPs in real-time.

Abstract: An information processor for information registration, capturing means captures a graphics processing command, and database registering means registers, as information about completed work in the database, information about a series of graphics processing commands concerning completed works out of the captured graphics processing commands. In an information processor for information retrieval, proceeding work detecting means detects a work in progress as a proceeding work based on the captured graphics processing command, and information acquiring means searches a database for the information about the work in progress which has been done before based on the graphics processing command concerning the proceeding work and acquires the information about the work in progress which has been done before.

Abstract: Multiple graphics processors in a graphics processing system are interconnected in a unidirectional or bidirectional ring topology, allowing pixels to transferred from any one graphics processor to any other graphics processor. The system can automatically identify one or more “master” graphics processors to which one or more monitors are connected and configures the links of the ring such that one or more other graphics processors can deliver pixels to the master graphics processor, facilitating distributed rendering operations. The system can also automatically detect the connections or lack thereof between the graphics processors.

Abstract: One embodiment of the invention is a method for storing transformed vertex attributes that includes the steps of allocating memory space for a transform feedback buffer, selecting one or more transformed vertex attributes to store in the transform feedback buffer independently of any shader programs executing on any processing units in the graphics rendering pipeline, configuring the transform feedback buffer to store the one or more transformed vertex attributes, and initiating a processing mode wherein vertex data is processed in the graphics rendering pipeline to produce the transformed vertices, the attributes of which are then written to the transform feedback buffer. One advantage is that the transform feedback buffer can be used to store and access transformed vertices, without having to convert the vertex data to a pixel format, store the pixels in a frame buffer, and then convert the pixels back to a vertex format.

Abstract: A system and method are disclosed for recreating graphics processing unit (GPU) state information associated with a migrated virtual machine (VM). A VM running on a first VM host coupled to a first graphics device, comprising a first GPU, is migrated to a second VM host coupled to a second graphics device, in turn comprising a second GPU. A context module coupled to the first GPU reads its GPU state information in its native GPU state representation format and then converts the GPU state information into an intermediary GPU state representation format. The GPU state information is conveyed in the intermediary GPU state representation format to the second VM host, where it is received by a context module coupled to the second GPU. The context module converts the GPU state information related to the first GPU from the intermediary GPU state representation format to the native GPU state representation format of the second GPU.

Abstract: One embodiment of the present invention sets forth a technique for reducing the amount of memory required to store vertex data processed within a processing pipeline that includes a plurality of shading engines. The method includes determining a first active shading engine and a second active shading engine included within the processing pipeline, wherein the second active shading engine receives vertex data output by the first active shading engine. An output map is received and indicates one or more attributes that are included in the vertex data and output by the first active shading engine. An input map is received and indicates one or more attributes that are included in the vertex data and received by the second active shading engine from the first active shading engine.

Abstract: One embodiment of the present invention sets forth a technique for splitting a set of vertices into a plurality of batches for processing. The method includes receiving one or more primitives each containing an associated set of vertices. For each of the one or more primitives, one or more vertices are gathered from the set of vertices, the vertices are arranged into one or more batches, the batch is routed to a processing pipeline line to process each batch as a separate primitive, and the one or more batches are processed to produce results identical to those of processing the entire primitive as a single entity.

Abstract: In a processing pipeline having a plurality of units, an interface unit is provided between a first, upstream pipeline unit that needs to be drained prior to a context switch and a second, downstream pipeline unit that might halt prior to a context switch. The interface unit redirects data that are drained from the first pipeline unit and to be received by the second pipeline unit, to a buffer memory provided in the front end of the processing pipeline. The contents of the buffer memory are subsequently dumped into memory reserved for the context that is being stored. When the processing pipeline is restored with this context, the data that were dumped into memory are retrieved back into the buffer memory and provided to the interface unit. The interface unit receives these commands and directs them to the second pipeline unit.

Abstract: An apparatus and method for fairly arbitrating between clients with varying workloads. The clients are configured in a pipeline for processing graphics data. An arbitration unit selects requests from each of the clients to access a shared resource. Each client provides a signal to the arbitration unit for each clock cycle. The signal indicates whether the client is waiting for a response from the arbitration unit and whether the client is not blocked from outputting processed data to a downstream client. The signals from each client are integrated over several clock cycles to determine a servicing priority for each client. Arbitrating based on the servicing priorities improves performance of the pipeline by ensuring that each client is allocated access to the shared resource based on the aggregate processing load distribution.

Abstract: Provided is a system for compressing multiple-sample-anti-aliasing (MSAA) tile data in a computer graphics pipeline. The system includes a plurality of pixels configured as a tile, where the tile has a plurality of samples of descriptor data for the pixels. Multiple graphics data processing units configured to receive the plurality of samples contain a plurality of coverage masks, which correspond to covered subtiles and compression logic encodes the tile descriptor data for receipt by a buffer.

Abstract: Multiprocessor decoding is accomplished in a first mode by generating with a series of n processors, from a set of data macroblocks, the entropy decoding output of each data macroblock and storing the entropy decoding output of each data macroblock in n storage elements, respectively, associated with the processors and in the second mode decoding the macroblock data from its associated storage element in response to the macroblock entropy decoding output from its associated storage element stored in an nth previous period, predetermined data from one or more adjacent macroblocks, and data produced from a previous processor in the series.

Abstract: Multiple output buffers are supported in a graphics processor. Each output buffer has a unique identifier and may include data represented in a variety of fixed and floating-point formats (8-bit, 16-bit, 32-bit, 64-bit and higher). A fragment program executed by the graphics processor can access (read or write any of the output buffers. Each of the output buffers may be read from and used to process graphics data by an execution pipeline within the graphics processor. Likewise, each output buffer may be written to by the graphics processor, storing graphics data such as lighting parameters, indices, color, and depth.

Abstract: A graphics system adapts a performance level to be sufficient to maintain a performance criterion in an acceptable range. In one embodiment, at least one utilization parameter of the core clock domain and the memory clock domain is monitored. In response to detecting an over-utilization condition, the performance level is increased to maintain the desired minimum number of frames per second. In response to detecting an under-utilization condition, the performance level is decreased to reduce power consumption and increase the lifetime of the graphics system.

Abstract: A media processing framework includes multiple media processing paths. At least one of the media processing paths includes a media processing pipeline which is in-process with respect to an application which interacts with the media processing pipeline. At least one other of the media processing paths includes a media processing pipeline which is out-of-process with respect to the application. The application can specify a custom plug-in presenter module to be set in either the in-process media processing pipeline or the out-of-process media processing pipeline. The application need not be “aware” of the pipeline that is being used, whether the pipeline is in-process or out-of-process, or the security level that is applied to the media processing pipeline. Both the in-process and the out-of-process media processing pipelines can supply media information to a presentation processor, such as a compositing engine.

Abstract: A graphics processing subsystem defines a bounding area as the portion of the display buffer and other memory buffers occupied by one or more rendered objects. When clearing the memory buffers, only the portions of the buffers corresponding to the bounding area need to be cleared. A graphics pipeline includes a bounding area memory to store bounding area values. The bounding area values are modified during rendering so that each rendered primitive falls within the bounding area values. The graphics processing subsystem clears a portion of the memory buffer in response to a clear command specifying a bounding area. The clear command may include a set of bounding area values defining the bounding area, or alternatively a reference to the bounding area memory. For applications that draw objects in isolation, the bounding area will be smaller than the window, resulting in a decreased time requirement for clearing the memory buffer.

Abstract: A technique for handling floating-point special values, e.g., Infinity, NaN, ?Zero, and denorms, during blend operations is provided so that blend operations on fragment color values that contain special values can be performed in compliance with special value handling rules. In particular, the presence of special values is detected or the potential presence of special values is detected. This information is used to qualify when blend optimizations may be performed, so that floating point blend operations can remain conformant to special value handling rules.

Abstract: A system renders a primitive of an image to be displayed, for instance in a mobile 3D graphic pipeline, the primitive including a set of pixels. The system locates the pixels in the area of the primitive, generates, for each pixel located in the area, a set of associated sub-pixels, borrows a set of sub-pixels from neighboring pixels, subjects the set of associated sub-pixels and the borrowed set of pixels to adaptive filtering to create an adaptively filtered set of sub-pixels, and further filters the adaptively filtered set of sub-pixels to compute a final pixel for display. Preferably, the set of associated sub-pixels fulfils at least one of the following: the set includes two associated sub-pixels and the set includes associated sub-pixels placed on pixel edges.

Abstract: Provided are methods for managing texture data in Graphics Processing Units (GPUs). The methods include receiving, into an arbiter, a preload request configured to request processing of texture data in advance of shader processing and receiving, into the arbiter, a dependent read request configured to request processing of texture data after shader processing. The methods also include receiving, into the arbiter, a capacity signal from a texture buffer and determining, utilizing the virtual buffer capacity signal, a selected request corresponding which of the preload request and the dependent read request is granted. The methods further include processing, in a texture processor, texture data corresponding to the selected request.

Abstract: A system and method for a row forwarding of pixel data in a 3-D graphics pipeline. Specifically, in one embodiment a data write unit capable of row forwarding in a graphics pipeline includes a first memory and logic. The first memory stores a plurality of rows of pixel information associated with a pixel. The plurality of rows of pixel information includes data related to surface characteristics of the pixel and includes a first row, e.g., a front row, and a second row, e.g., a rear row. A data write unit includes first logic for accessing a portion of the second row and for storing data accessed therein into a portion of the first row. The data write unit also comprises logic for recirculating the plurality of rows of pixel information to an upstream pipeline module for further processing thereof.

Abstract: The present invention is generally related to the field of image processing, and more specifically to an instruction set for processing images. Vector processing may involve rearranging vector operands in one or more source registers prior to performing vector operations. Typically, rearranging of operands in source registers is done by issuing a plurality of permute instructions that require excessive usage of temporary registers. Furthermore, the permute instructions may cause dependencies between instructions executing in a pipeline, thereby adversely affecting performance. Embodiments of the invention provide a level of muxing between a register file and a vector unit that allow for rearrangement of vector operands in source registers prior to providing the operands to the vector unit, thereby obviating the need for permute instructions.

Abstract: An image pipeline performs image processing operations (for example, Bayer-to-RGB conversion, white balancing, autoexposure, autofocus, color correction, gamma correction, zooming, unsharp masking, mirroring, resizing, color space conversion) on tiles whose sizes are varied, whose widths are less than the width of the output image frame being generated, and whose heights are less than the height of the output image frame. A tile processor program executing on a processor in the camera determines configuration information for configuring each pipeline stage based on user input and camera usage. The configuration information is determined so that the pipeline outputs properly combine to form the output image frame. The sizes, shapes, locations and processing order of the tiles are determined such that a single tile of a particular size is in a desired location with respect to the overall image frame, thereby facilitating such functions as autofocus, autoexposure and face detection.

Abstract: Systems and methods for performing cube mapping computations using a shader program may reduce the need for fixed function cube mapping computation units in graphics processors. Therefore, die area is used more efficiently since a general purpose processing unit may be configured using shader program instructions to perform the cube mapping computations and other computations. The general purpose processing unit is configured to perform floating point computations to identify the cube map face that will be read and process the cube map coordinates. A fixed function unit is also configured to identify the cube map face that will be read to avoid passing the cube map face information from the general purpose processing unit to the fixed function unit.

Abstract: A method and system for patching instructions in a 3-D graphics pipeline. Specifically, in one embodiment, instructions to be executed within a scheduling process for a shader pipeline of the 3-D graphics pipeline are patchable. A scheduler includes a decode table, an expansion table, and a resource table that are each patchable. The decode table translates high level instructions to an appropriate microcode sequence. The patchable expansion table expands a high level instruction to a program of microcode if the high level instruction is complex. The resource table assigns the units for executing the microcode. Addresses within each of the tables can be patched to modify existing instructions and create new instructions. That is, contents in each address in the tables that are tagged can be replaced with a patch value of a corresponding register.

Abstract: A visual server system (10) includes a server (12) having a graphics application (20). The graphics application (20) generates image content and position information. The server (12) streams the image content and the position information for transport over a network link. A plurality of remote clients (14) can receive the image content and position information from the server (12) over the network link. Each of the plurality of remote clients (14) may provide input parameters to the graphics application (20). The input parameters can provide adjustments to the image content and position information provided to each of the plurality of remote clients (14). The graphics application (20) selects from among the input parameters provided by the plurality of remote clients (14) for adjusting the image content and the position information provided to the remote clients (14).

Abstract: The current invention involves new systems and methods for increasing texture filtering performance by reorganizing a texture sampling order used to read and filter texels when anisotropic filtering is used. Texel read performance is improved for anisotropic filtering by reorganizing texel reads when a texel cache is used. The texel reads are paired based on a major axis alignment in pixel space. The paired texel reads for a pixel footprint may also be ordered to improve texel coherency, thereby improving a texture cache hit rate.

Abstract: A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video data. The video decoder includes multiple row decoding engines for decoding the MPEG-2 video data. Each row decoding engine concurrently decodes two or more rows of the MPEG-2 video data. The row decoding engines have a pipelined architecture for concurrently decoding multiple rows of MPEG-2 video data. The video decoder may be integrated on an integrated circuit chip with other video and graphics system components such as transport processors for receiving one or more compressed data streams and for extracting video data, and a video compositor for blending processed video data with graphics.

Abstract: Systems, methods and computer readable media are disclosed for sending a client graphics data across a remote session for an application, where the application makes fixed function pipeline API calls and the client and server support shader pipeline API calls for the remote session. fixed function pipeline graphics calls from sent from the application are intercepted, wrapped, converted into their fixed function pipeline equivalent graphics call or calls and then sent across the communications network to the client according to a protocol of the remote session.

Abstract: Techniques are described for processing graphics images with a graphics processing unit (GPU) using deferred vertex shading. An example method includes the following: generating, within a processing pipeline of a graphics processing unit (GPU), vertex coordinates for vertices of each primitive within an image geometry, wherein the vertex coordinates comprise a location and a perspective parameter for each one of the vertices, and wherein the image geometry represents a graphics image; identifying, within the processing pipeline of the GPU, visible primitives within the image geometry based upon the vertex coordinates; and, responsive to identifying the visible primitives, generating, within the processing pipeline of the GPU, vertex attributes only for the vertices of the visible primitives in order to determine surface properties of the graphics image.

Abstract: A high performance graphics processing and display system architecture supporting a cluster of multiple cores of graphic processing units (GPUs) that cooperate to provide a powerful and highly scalable visualization solution supporting photo-realistic graphics capabilities for diverse applications. The present invention eliminates rendering bottlenecks along the graphics pipeline by dynamically managing various parallel rendering techniques and enabling adaptive handling of diverse graphics applications.

Abstract: Apparatus, systems and methods for display processing line buffers incorporating pipeline overlap are disclosed. For example, an apparatus is disclosed including processing logic to use pixel processing algorithms to process a pixel value of a first portion of an image, and line buffers coupled to the processing logic. The line buffers to hold at least some pixel values of other portions of the image adjacent to the first portion. Where the pixel values of the other portions of the image held by the line buffers correspond to pixel values of the adjacent portions of the image that are to be convolved by the pixel processing algorithms with the pixel value of the first portion. Other implementations are also disclosed.

Abstract: A pluggable graphics system is described herein that leverages high-end graphical capabilities of various mobile devices while keeping overhead for handling the variations to a negligible level. The pluggable graphics system breaks a graphics pipeline into functional blocks and includes base templates for handling different device capabilities for each functional block. During execution, based on capabilities of the device, the system composes appropriate functional blocks together through just-in-time (JIT) compilation to reduce runtime overhead in performance-sensitive code paths. The functional blocks include code designed to perform well with a particular set of hardware capabilities. In addition, for hardware platforms with large registers, the system provides advanced in-place blending that avoids wasteful memory accesses to reduce blending time.

Abstract: An apparatus and method for fairly arbitrating between clients with varying workloads. The clients are configured in a pipeline for processing graphics data. An arbitration unit selects requests from each of the clients to access a shared resource. Each client provides a signal to the arbitration unit for each clock cycle. The signal indicates whether the client is waiting for a response from the arbitration unit and whether the client is not blocked from outputting processed data to a downstream client. The signals from each client are integrated over several clock cycles to determine a servicing priority for each client. Arbitrating based on the servicing priorities improves performance of the pipeline by ensuring that each client is allocated access to the shared resource based on the aggregate processing load distribution.

Abstract: A new, useful, and non-obvious shader processor architecture having a shader register file that acts both as an internal storage register file for temporarily storing data within the shader processor and as a First-In First-Out (FIFO) buffer for a subsequent module. Some embodiments include automatic, programmable hardware conversion between numeric formats, for example, between floating point data and fixed point data.

Abstract: One embodiment of a video processor includes a first media processing device coupled to a first memory and a second media processing device coupled to a second memory. The second media processing device is coupled to the first media processing device via a scalable bus. A software driver configures the media processing devices to provide video processing functionality. The scalable bus carries video data processed by the second media processing device to the first media processing device where the data is combined with video data processed by the first media processing device to produce a processed video frame. The first media processing device transmits the combined video data to a display device. Each media processing device is configured to process separate portions of the video data, thereby enabling the video processor to process video data more quickly than a single-GPU video processor.

Abstract: A graphics processing apparatus 2 includes graphics processing pipelines 8. The graphics processing pipelines 8 include a programmable hardware stage 12, a pipeline memory 22 and writeback circuitry 16. Programmable resolving circuitry 18 is provided by the programmable hardware stage 12 within each pipeline and is responsive to one or more graphics program instructions to read pixel values at a first resolution generated within the pipeline memory 22 by pixel value generating circuitry 18 provided by the programmable hardware stage 12 and to perform a resolving operation upon these pixels values so as to generate pixel values at a second resolution. These pixel values at the second resolution are then written back to a frame buffer memory 6.