Abstract: A PC-based computing system employing a silicon chip having a routing unit, a control unit and profiling unit for parallelizing multiple GPU-driven pipeline cores according to the object division mode of parallelization operation, during a graphics application. The PC-based computing system includes system memory for storing software graphics applications, software drivers and graphics libraries, and an operating system (OS), stored in the system memory, and a central processing unit (CPU), for executing the OS, graphics applications, drivers and graphics libraries. The system also includes a CPU/memory interface module and a CPU bus. The routing unit (i) routes the stream of geometrical data and graphic commands from the graphics application to one or more of the GPU-driven pipeline cores, and (ii) routes pixel data output from one or more of GPU-driven pipeline cores during the composition of frames of pixel data corresponding to final images for display on the display surface.

Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).

Abstract: An intelligent caching data structure and mechanisms for storing visual information via objects and data representing graphics information. The data structure is generally associated with mechanisms that intelligently control how the visual information therein is populated and used. The cache data structure can be traversed for direct rendering, or traversed for pre-processing the visual information into an instruction stream for another entity. Much of the data typically has no external reference to it, thereby enabling more of the information stored in the data structure to be processed to conserve resources. A transaction/batching-like model for updating the data structure enables external modifications to the data structure without interrupting reading from the data structure, and such that changes received are atomically implemented. A method and mechanism are provided to call back to an application program in order to create or re-create portions of the data structure as needed, to conserve resources.

Abstract: A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Abstract: PC-based computing system having an integrated graphics subsystem supporting parallel graphics processing operations across a plurality of different graphics processing units (GPUs) supplied from the same or different vendors. The graphics subsystem include a graphics controller hub (GCH) chip located on a CPU bus, and having Multi-Pipeline Core Logic (MP-CL) circuitry including a routing unit and a control unit. The plurality of different GPUs are interfaced with the GCH chip. Each different GPU supports a GPU-driven pipeline core having a frame buffer (FB) for storing a fragment of pixel data. The GPU-driven pipeline cores are arranged in a parallel architecture and operated according to a parallelization mode of operation, so that said GPU-driven pipeline cores process data in a parallel manner.

Abstract: Methods having corresponding apparatus and computer-readable media embodying instructions executable by a computer to perform the methods comprise placing content of a window of a virtual desktop generated by a graphical user interface into an OpenGL scene; rendering the OpenGL scene to a buffer of a first graphical processing unit (GPU); providing a first portion of the contents of the buffer of the first GPU to a first display device; copying a second portion of the contents of the buffer of the first GPU to a buffer of a second GPU; and providing contents of the buffer of the second GPU to a second display device; wherein the first and second display devices together create a single composite display of the virtual desktop.

Abstract: Provided are a method and system checking output from multiple execution units. Execution units concurrently execute test instructions to generate test output, wherein test instructions are transferred to the execution units from a cache coupled to the execution units over a bus. The test output from the execution units is compared to determine whether the output from the execution units indicates the execution units are properly concurrently executing test instructions. The result of the comparing of the test output are forwarded to a design test unit.

Abstract: A system and method for processing graphics data which requires less read and write bandwidth. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory while reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to a bank of memory. The processing pipeline concurrently processes an amount of graphics data at least equal to that included in a page of memory. A third bank of memory is precharged concurrently with writing data to the first bank and reading data from the second bank in preparation for access when reading data from the second bank of memory is completed.

Abstract: A system of inter-connectable modules that can be used to build consumer electronic sub-systems and products. Familial features are included for easy setup and control. Data is passed between modules using a common interface to permit easy routing and reconfiguration of data flows.

Abstract: A programmable graphics pipeline and method for processing multiple partitioned multimedia data, such as graphics data, image data, video data, or audio data. A preferred embodiment of the programmable graphics pipeline includes an instruction cache, a register file, and a vector functional unit that perform partitioned instructions. In addition, an enhanced rasterization unit is used to generate inverse-mapped source coordinates in addition to destination output coordinates for graphics and other media processing. An enhanced texture address unit generates corresponding memory addresses of source texture data for graphics processing and source media data for media processing. Data retrieved from memory are stored in an enhanced texture cache for use by the vector functional unit. A vector output unit includes a blending unit for graphics data and an output buffer for wide media data.

Abstract: A multi-mode parallel graphics rendering and display system supporting real-time graphics rendering and display operations using a graphics hub device. The system includes a CPU memory space, one or more CPUs for executing graphics-based applications, and a multi-mode parallel graphics rendering system (MPGRS) supporting multiple modes of parallel operation including object division, image division, and time division. The MMPGRS includes a plurality of graphic processing pipelines (GPPLs) that support a parallel graphics rendering process employing one or more modes of parallel operation.

Abstract: Embodiments described herein disclose a system for enabling emulation of a MIMD ISA extension which supports user-level sequencer management and control, and a set of privileged code executed by both operating system managed sequencers and application managed sequencers, including different sets of persistent per-CPU and per-thread data. In one embodiment, a lightweight code layer executes beneath the operating system. This code layer is invoked in response to particular monitored events, such as the need for communication between an operating system managed sequencer and an application managed sequencer. Control is transferred to this code layer, for execution of special operations, after which control returns back to originally executing code. The code layer is normally dormant and can be invoked at any time when either a user application or the operating system is executing.

Abstract: Video conversion using a 3D graphics pipeline of a graphical processing unit (GPU) is disclosed. A plurality of video data formatted in a first video format is accessed from a memory unit. Moreover, the plurality of video data is converted from the first video format to a second video format using a 3D graphics pipeline of the GPU. The plurality of video data formatted in the second video format is sent to the memory unit. The 3D graphics pipeline applies a filtering technique. In an embodiment, the filtering technique is an interpolation technique.

Abstract: A system, method and article of manufacture are provided for programmable processing in a computer graphics pipeline. Initially, data is received from a source buffer. Thereafter, programmable operations are performed on the data in order to generate output. The operations are programmable in that a user may utilize instructions from a predetermined instruction set for generating the same. Such output is stored in a register. During operation, the output stored in the register is used in performing the programmable operations on the data.

Abstract: A processor generates Z-cull information for tiles and groups of tiles. In one embodiment the processor includes an on-chip cache to coalesce Z information for tiles to identify occluded tiles. In a coprocessor embodiment, the processor provides Z-culling information to a graphics processor.

Abstract: A graphics module for the rendering of a bidimensional scene on a displaying screen is described, comprising a sort-middle-type graphics pipeline, said graphics pipeline comprising: a first rasterizer module so configured as to convert an edge-type input primitive received by a path processing module into a primitive of active-edge-type; a first processing module so configured as to associate said primitive of active-edge-type to respective macro-blocks corresponding to portions of the screen and to store said primitive of active-edge-type into a scene buffer; a second processing module so configured as to read said scene buffer and to provide said primitive of active-edge-type to a second rasterizer module.

Abstract: Performing a hash algorithm in a processor architecture to alleviate performance bottlenecks and improve overall algorithm performance. In one embodiment of the invention, the hash algorithm is pipelined within the processor architecture.

Abstract: A three-dimensional graphics data rendering method. The method divides initially inputted first graphics data into a static object and a dynamic object, performs a rendering process with respect to the static object, and updates a predetermined buffer with the rendering result. Then the method performs a transformation process, a portion of the rendering process with respect to the dynamic object, determines an updating area, and stores a rendering result of the buffer corresponding to the updating area in a predetermined storage unit; performs a remaining rendering process with respect to the dynamic object, updates the buffer and outputs a first image whose rendering is completed. Finally, the method restores a rendering result of the updating area to the buffer by referring to the storage unit and utilizes a rendering result of the restored buffer as a rendering result of subsequently inputted second graphics data.

Abstract: A data processing device connected with a data supply device for performing predetermined data processing includes: a communication control unit for controlling communication with the data supply device; a data processing unit for performing the data processing based on input data received from the data supply device; and a device control unit for performing predetermined processing in correspondence with command data received from the data supply device based on the command data. The communication control unit receives the input data and the command data each of which is contained in a packet having a common fixed length from the data supply device. When an identification part at a predetermined position in the reception packet received from the data supply device is set at a predetermined command identification value indicating the command data, the communication control unit supplies data contained in the reception packet to the device control unit.

Abstract: Methods and systems for allocating workloads in a pixel sequential rendering system comprising a plurality of processors are disclosed. Such workloads typically comprise a raster pixel image comprising a plurality of graphical objects. For each scan line (540) of the raster pixel image (510), edges of the plurality of graphical objects (520, 525) that intersect with a current scan line (540) of the raster pixel image (510) are identified in a predetermined order. Spans of pixel locations on the current scan line, each defined by an adjacent pair of edges of the identified edges, are divided into segments (503, 504), one of which comprises varying pixel values. The segments (503, 504) are allocated independently of existing workloads of the processors to respective ones of the processors or processor cores for rendering.

Abstract: Holographic display with which voice and holographic image over internet protocol (VHIOIP) services or communications are provided.

Abstract: A method for high level synchronization between an application and a graphics pipeline comprises receiving an application instruction in an input stream at a predetermined component, such as a command stream processor (CSP), as sent by a central processing unit. The CSP may have a first portion coupled to a next component in the graphics pipeline and a second portion coupled to a plurality of components of the graphics pipeline. A command associated with the application instruction may be forwarded from the first portion to the next component in the graphics pipeline or some other component coupled thereto. The command may be received and thereafter executed. A response may be communicated on a feedback path to the second portion of the CSP. Nonlimiting exemplary application instructions that may be received and executed by the CSP include check surface fault, trap, wait, signal, stall, flip, and trigger.

Abstract: Although GPUs have been harnessed to solve non-graphics problems, these solutions are not widespread because GPUs remain difficult to program. Instead, an interpreter simplifies the task of programming a GPU by providing language constructs such as a set of data types and operations that are more familiar to non-graphics programmers. The interpreter maps these familiar language constructs to the more difficult graphics programming resources such as DirectX®, OpenGL®, Cg®, and/or HLSL®.

Abstract: A method for adapting power consumption of a processor based upon an application demand is provided. The method initiates with determining an application demand based upon a current processing operation. Then, a time interval associated with the application demand is determined. Next, unnecessary power consuming functions for the application demand are determined. Then, a clock frequency for the unnecessary power consuming functions is reduced for the time interval. In one embodiment, the power is terminated to the unnecessary power consuming functions. In another embodiment, the clock frequency of the processor is adjusted for at least a portion of the time interval. A program interface for adapting power consumption of a computer system, processor instructions for adapting power consumption of a computer system and a processor are included.

Abstract: States that are used in configuring a processing pipeline are passed down through a separate pipeline in parallel with the data transmitted down through the processing pipeline. With this separate pipeline, the states for configuring any one stage of the processing pipeline are continuously available in the corresponding stage of the state pipeline, and new states for configuring the processing pipeline can be transmitted down the state pipeline without flushing the processing pipeline. The processing pipeline and the separate pipeline for the states can be divided into multiple sections so that the width of the separate pipeline for the states can be reduced.

Abstract: The present invention relates to a parallel pipeline graphics system. The parallel pipeline graphics system includes a back-end configured to receive primitives and combinations of primitives (i.e., geometry) and process the geometry to produce values to place in a frame buffer for rendering on screen. Unlike prior single pipeline implementation, some embodiments use two or four parallel pipelines, though other configurations having 2?n pipelines may be used. When geometry data is sent to the back-end, it is divided up and provided to one of the parallel pipelines. Each pipeline is a component of a raster back-end, where the display screen is divided into tiles and a defined portion of the screen is sent through a pipeline that owns that portion of the screen's tiles. In one embodiment, each pipeline comprises a scan converter, a hierarchical-Z unit, a z buffer logic, a rasterizer, a shader, and a color buffer logic.

Abstract: Included are embodiments of systems and methods for processing metacommands. In at least one exemplary embodiment a Graphics Processing Unit (GPU) includes a metaprocessor configured to process at least one context register, the metaprocessor including context management logic and a metaprocessor control register block coupled to the metaprocessor, the metaprocessor control register block configured to receive metaprocessor configuration data, the metaprocessor control register block further configured to define metacommand execution logic block behavior. Some embodiments include a Bus Interface Unit (BIU) configured to provide the access from a system processor to the metaprocessor and a GPU command stream processor configured to fetch a current context command stream and send commands for execution to a GPU pipeline and metaprocessor.

Abstract: Embodiments of the present invention include an arithmetic logic unit for use in a graphics pipeline. The arithmetic logic unit comprising a plurality of scalar arithmetic logic subunits wherein each subunit performs a resultant arithmetic logic operation in the form of [a*b “op” c*d] on a set of input operands a, b, c and d. The arithmetic logic unit also for produces a result based thereon wherein “op” represents a programmable operation and wherein further the resultant arithmetic logic operation is software programmable to implement a plurality of different graphics functions.

Abstract: A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream. The pipeline system employs a plurality of interconnected stages to decode and decompress the single bit stream, including a start code detector. When in a search mode, the start code detector searches for a specific start code corresponding to one of multiple compression standards. The start code detector responding to the single serial bit stream generates control tokens and data tokens. A respective one of the tokens includes a plurality of data words. Each data word has an extension bit which indicates a presence of additional words therein. The data words are thereby unlimited in number.

Abstract: A controlling process may enable or disable the launching of a predicated process that has already been queued for launching, e.g. via a pushbuffer. The controlling process generates a report so that launching of the predicated process is enabled or disabled based on the report. The predicate may be global in application to enable or disable all subsequent launch commands. Alternatively, the predicate may be specific to one or more predicated processes. In an embodiment with a central processing unit (CPU) coupled to a graphics processing unit (GPU), the CPU may generate the controlling process that enables or disables the launch of the predicated process. Alternatively or additionally, the GPU may generate the controlling process that enables or disables the launch of the predicated process.

Abstract: A system, method and article of manufacture are provided for programmable processing in a computer graphics pipeline. Initially, data is received from a source buffer. Thereafter, programmable operations are performed on the data in order to generate output. The operations are programmable in that a user may utilize instructions from a predetermined instruction set for generating the same. Such output is stored in a register. During operation, the output stored in the register is used in performing the programmable operations on the data.

Abstract: A method and an apparatus are for displaying an image. The image is broken down in accordance with a scheme, which can be predetermined, into sections, so-called chunks. The chunks are supplied to a pipeline for processing, on the basis of a scheme which can likewise be predetermined. The pipeline includes a large number of pipeline processors, which operate at a specific resolution level. The chunks are then combined again to form an image at the specific resolution level, and are displayed as an intermediate result. This process is repeated iteratively until the highest resolution level is reached.

Abstract: A system, method and apparatus to provide flexible texture filtering. A programmable texture filtering module is introduced into the graphics processing pipeline of a graphic coprocessor and graphic processor integrated with the host. A program from a defined instruction set may then be loaded into texture processing cores to process texture data consistent with the program.

Abstract: Apparatuses and methods for detecting position conflicts during fragment processing are described. Prior to executing a program on a fragment, a conflict detection unit, within a fragment processor checks if there is a position conflict indicating a RAW (read after write) hazard may exist. A RAW hazard exists when there is a pending write to a destination location that source data will be read from during execution of the program. When the fragment enters a processing pipeline, each destination location that may be written during the processing of the fragment is entered in conflict detection unit. During processing, the conflict detection unit is updated when a pending write to a destination location is completed.

Abstract: The present invention related to processing image frames through a pipeline of effects by breaking the image frames into multiple blocks of image data. The example method includes generating a plurality of blocks from each frame, processing each block through a pipeline of effects in a predefined consecutive order, and aggregating the processed blocks to produce an output frame by combining the primary pixels from each processed block. The pipeline of effects may be distributed over a plurality of processing nodes, and each effect may process a block, provided as input to the node. Each processing node may independently process a block using an effect.

Abstract: An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming.

Abstract: Techniques, apparatus and system are described for providing a hardware-type vector graphics acceleration. In one aspect, a hardware-type vector graphics accelerator includes graphics processing modules to communicate with a controller unit. The graphics processing modules include at least one of a rasterizing setup module, a scissor module, a paint generation module, an alpha masking module, and a blending module connected together according to a pipeline architecture to perform two-dimensional (2D) vector graphics acceleration in response to one or more commands received from the controller unit.

Abstract: A drawing processing apparatus capable of executing a drawing processing program having conditional branches efficiently by multipass rendering. The drawing processing apparatus comprises arithmetic processing parts including an object input part, a primitive generating part, a raster part, a pixelation part, a distribution part, and a shader which constitute pipeline stages. The shader divides the program into and executes the same in a plurality of passes depending on conditional branches. The shader generates enable flags determining whether or not respective pixels satisfy branch conditions. The flag generating part generates bind enable flags which are the enable flags on the pixels bound into the processing granularities of the pipeline stages, and feeds back the same to the respective pipeline stages. The arithmetic processing parts in the individual pipeline stages refer to the bind enable flags and limit the submission of data not targeted for arithmetic processing in the branched passes.

Abstract: Optimizing pipeline handler execution. A method may be practiced in a computing environment including an execution pipeline. The method includes acts to optimize execution of handlers in the pipeline. The method includes receiving a payload object. Policy information about the payload object is referenced. The policy information includes at least one property value. Based on the policy information about the payload object, handlers are selected from among the pipeline to execute on the payload object. The policy information may be referenced by strategies. Handlers may be registered with the strategies to facilitate the strategies being used to select handlers.

Abstract: Systems and methods that optimize GPU processing by front loading activities from a set time/binding time to creation time via enhancements to an API that configures the GPU. Such enhancements to the API include: implementing layering arrangements, employing state objects and view components for data objects; incorporating a pipeline stage linkage/signature, employing a detection mechanism to mitigate error conditions. Such an arrangement enables front loading of the work and reduction of associated API calls.

Abstract: A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using the available processing resources to produce resulting data, and the resulting data is passed to an input/output device.

Abstract: An arithmetic logic unit (ALU) in a graphics processor is described. The ALU includes circuitry for performing an operation using a first set of pixel data. The first set of pixel data is resident in a pipeline register coupled to the circuitry. A temporary register is coupled to the circuitry. The temporary register can receive a result of the operation. The temporary register allows a result generated using one set of pixel data to be used with a subsequent set of pixel data in the same ALU. The result of the operation can thus be used in a second operation with a second set of pixel data that resides in the pipeline register after the first set of pixel data.

Abstract: A method of displaying graphics data is described. The method involves accessing the graphics data in a memory subsystem associated with one graphics subsystem. The graphics data is transmitted to a second graphics subsystem, where it is displayed on a monitor coupled to the second graphics subsystem.

Abstract: A graphics processing circuit includes an anti-aliasing and stippling circuit operative to provide a primitive texture coordinate set in response to vertex data, the anti-aliasing and stippling circuit performing anti-aliasing operations, in parallel, with at least one appearance attribute determination operation on the vertex data, a rasterizer, coupled to the anti-aliasing and stippling circuit, operative to generate a pixel texture coordinate set in response to the primitive texture coordinate set, and apply an appearance value to a pixel defined by the pixel texture coordinate set, and a texture circuit, coupled to the rasterizer, operative to retrieve the appearance value from a corresponding one of a plurality of textures in a multi-texture map in response to the pixel texture coordinate set, the multi-texture map including data representing point, line and polygon texture data.

Abstract: An image processing device including a storage section, a parallel processing controller, a sequential processing controller, and a selection section which selectively operates the two control sections. The parallel processing controller connects one or more of the image processing modules such that first buffer modules are connected at least one of preceding and following each image processing module, to formulate a first image processing section, and controls such that individual image processing modules perform image processing in parallel with one another. The first buffer modules perform exclusive access control. The sequential processing controller connects one or more of the image processing modules such that second buffer modules are connected at least one of preceding and following each image processing module, to formulate a second image processing section, and controls such that the individual image processing modules perform image processing sequentially.

Abstract: Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. An interlink module is coupled to receive processed data corresponding to the frames from each of the processors. The interlink module divides a first frame into multiple frame portions by dividing pixels of the first frame using at least one balance point. The interlink module dynamically determines a position for the balance point that minimizes differences between the workload of the processors during processing of commands and/or data of one or more subsequent frames.

Abstract: The present invention discloses a computer with a display panel mounted thereon, which comprises: a frame structure, a display panel and at least one casing board covering the frame structure. The frame structure further comprises: a front frame, a rear frame, a baseplate connecting the bottoms of the front frame and the rear frame, and two support bars connecting the tops of the front frame and the rear frame. The front and rear frames, the baseplate and the support bars define an accommodation space inside the frame structure and at least four installation planes encasing the accommodation space. The display panel is installed on an arbitrary installation plane and electrically connected to the motherboard to receive video signals and present images. The casing boards are installed on the other installation planes where no display panel is installed.

Abstract: Allocation of memory registers for shaders by a processor is described herein. For each shader, registers are allocated based on the shader's level of complexity. Simpler shader instances are restricted to a smaller number of memory registers. More complex shader instances are allotted more registers. To do so, developers' high level shading level (HLSL) language includes template classes of shaders that can later be replaced by complex or simple versions of the shader. The HLSL is converted to bytecode that can be used to rasterize pixels on a computing device.

Abstract: Each row of a row based shader engine comprises a shader pipe array, a texture filter, and a level one texture cache system. The shader pipe array accepts texture requests for a specified pixel from a resource and performs associated rendering calculations, outputting texel data. The texture mapping unit receives texel data from a level one cache system and through formatting and bilinear filtering interpolations, generates a formatted bilinear result based on a specific pixel's corresponding four texels. Utilizing multiple rows of a row based shader engine within the shader engine allows for the parallel processing of multiple simultaneous resource requests. A method for texture filtering utilizing a row based shader engine is also presented.

Abstract: Apparatus and systems utilizing multiple shader engines where each shader engine comprises multiple rows of shader engine filters combined with level one and level two cache systems. Each unified shader engine filter comprises a shader pipe array, and a texture mapping unit with access to a level one cache system and a level two cache. The shader pipe array accepts texture requests for a specified pixel from a resource and performs associated rendering calculations, outputting texel data. The texture mapping unit retrieves texel data stored in a level one cache system, with the ability to read and write to and from a level two cache system, and through formatting and bilinear filtering interpolations generates a formatted bilinear result based on the specific pixel's neighboring texels. Utilizing multiple rows of shader engine filters within a shader engine allows for the parallel processing of multiple simultaneous resource requests.